This graph shows which files directly or indirectly include this file:

Classes
struct	_SIGS

struct	_SYNCPAL

struct	_SYNCRT

struct	DQPKT

struct	wDQPKT

struct	dwDQPKT

struct	DQRDCFG

struct	DQWRVALM

struct	wDQRDVALM

struct	wDQWRVALM

struct	dwDQWRVALM

struct	DQSETCFG

struct	DQEVENT

struct	DQAXMAP

struct	DQGETCFG

struct	DQGETCFG_RQ

struct	DQWRCHNL

struct	DQCHNL

struct	DQWRCHNL32

struct	DQRDCHNL

struct	DQSETCLK

struct	DQSETCL

struct	DQSETTRL

struct	DQSETTRIG

struct	DQWRRD

struct	DQFIFO

struct	DQWRRDFIFO

struct	DQFLASHDATA

struct	DQFPGADATA

struct	DQCRCINFO

struct	DQSETCOMM

struct	DQSETPRM

struct	DQSETCAL

struct	DQIOCTL

struct	DQBURST

struct	DQCLRMEM

struct	DQRBF

struct	DQRBFDEV

struct	NBUFSTR

struct	HW_TEST_DATA

struct	DL_STATUS

struct	DQEECMNDEVS

struct	DQPRMFLAGS

struct	SIMA_ADCT_BITS

struct	SIMA_CTRL_BITS

struct	SIMA_TBUS_BITS

struct	SIMA_STAT_BITS

union	SIMA_ADCT

union	SIMA_CTRL

union	SIMA_TBUS

union	SIMA_STAT

struct	SIMA_MSG_CTRL_STATUS

struct	DQCNAMES_104

struct	DQCALSET_104

struct	DQOPMODEPRM_104

struct	DQCNAMES_2000_

struct	DQCALSET_2000_

struct	DQOPMODEPRM_2000_

struct	DQINITPRM_2000_

struct	DQSDOWNPRM_2000_

struct	DEVEEPROM_2000_

struct	DQCNAMES_201_

struct	DQCALSET_201_

struct	DQOPMODEPRM_201_

struct	DEVEEPROM_201_

struct	DQCNAMES_205_

struct	DQCALSET_205_

struct	DQOPMODEPRM_205_

struct	DEVEEPROM_205_

struct	DQCNAMES_208_

struct	DQCNAMES_207_

struct	DQCALSET_208_

struct	DQOPMODEPRM_208_

struct	DEVEEPROM_208_

struct	DQCFGCH_211

struct	DQCFGLAYER_211

struct	DQCNAMES_211_

struct	CAL_DAC_SET_211

struct	DQCALSET_211_

struct	CAL_DAC_SET_EXT_211

struct	DQCALSET_EXT_AFON_211_

struct	DQCALSET_EXT_AFOFF_211_

struct	DQOPMODEPRM_211_

struct	DEVEEPROM_211_

struct	DQCNAMES_217_

struct	CAL_DAC_SET_217

struct	DQCALSET_217_

struct	DQCALSET_217_X

struct	DQOPMODEPRM_217_

struct	DEVEEPROM_217_

struct	DQCNAMES_224_

struct	DQCALSET_224_

struct	DQOPMODEPRM_224_

struct	DEVEEPROM_224_

struct	DQAI225CALDATA

struct	DQCNAMES_225_

struct	DQCALSET_225_

struct	DQOPMODEPRM_225_

struct	DEVEEPROM_225_

struct	DQ254SetExt

struct	DQCNAMES_254_

struct	DQCALCHAN_254_

struct	DQCALSET_254_

struct	DQOPMODEPRM_254_

struct	DEVEEPROM_254_

struct	WFPRM_254

struct	WFMEASURE_254

struct	DQ255SetExt

struct	DQCNAMES_255_

struct	DQCALCHAN_255_

struct	DQCALSET_255_

struct	DQOPMODEPRM_255_

struct	DEVEEPROM_255_

struct	WFPRM_255

struct	WFMEASURE_255

struct	DQCNAMES_301_

struct	DQCALSET_301_

struct	DQOPMODEPRM_301_

struct	DQINITPRM_301_

struct	DQSDOWNPRM_301_

struct	DEVEEPROM_301_

struct	DQCNAMES_332_

struct	DQCALSET_332_

struct	DQCALSET_333_

struct	DQOPMODEPRM_332_

struct	DQINITPRM_332_

struct	DQSDOWNPRM_332_

struct	DEVEEPROM_332_

struct	DQCNAMES_358_

struct	DQCALSET_358_

struct	DQOPMODEPRM_358_

struct	DQINITPRM_358_

struct	DQSDOWNPRM_358_

struct	DEVEEPROM_358_

struct	DQ_358CAL_HEAD

struct	DQEXCAL_358

struct	DQEXCAL_358_8

struct	EV401_ID

struct	DQCNAMES_401_

struct	DQOPMODEPRM_401_

struct	DQINITPRM_401_

struct	DQSDOWNPRM_401_

struct	DEVEEPROM_401_

struct	DQCNAMES_403_

struct	DQOPMODEPRM_403_

struct	DQINITPRM_403_

struct	DQSDOWNPRM_403_

struct	DEVEEPROM_403_

struct	DQCNAMES_448_

struct	DQOPMODEPRM_448_

struct	DQINITPRM_448_

struct	DQCALSET_448_

struct	DEVEEPROM_448_

struct	DQDIO448DATAOUT

struct	DQCNAMES_416_

struct	DQCNAMES_432_

struct	DQCALSET_416_

struct	DQCALSET_432_

struct	DQOPMODEPRM_416_

struct	DQOPMODEPRM_432_

struct	DQINITPRM_416_

struct	DQSDOWNPRM_416_

struct	DQINITPRM_432_

struct	DQSDOWNPRM_432_

struct	DEVEEPROM_416_

struct	DEVEEPROM_432_

struct	DQDIO416DATAIN

struct	DQDIO416DATAOUT

struct	DQDIO432DATAIN

struct	DQDIO432PWM

struct	DQDIO432CVTD

struct	DQDIO432DATAOUT

struct	DQCNAMES_462_

struct	DQCALSET_462_

struct	DQOPMODEPRM_462_

struct	DQINITPRM_462_

struct	DQSDOWNPRM_462_

struct	DEVEEPROM_462_

struct	DQDIO462DATAIN

struct	DQDIO462DATAOUT

struct	DQMSG_501

struct	DQMSG_501_L

struct	EV501_ID

struct	DQCNAMES_501_

struct	DQCNAMES_508_

struct	DQOPMODEPRM_501_

struct	DQINITPRM_501_

struct	DQSDOWNPRM_501_

struct	DEVEEPROM_501_

struct	DQCNAMES_503_

struct	DQCHNLSET_503_

struct	DQOPMODEPRM_503_

struct	DQINITPRM_503_

struct	DQSDOWNPRM_503_

struct	DEVEEPROM_503_

struct	DQCNAMES_504_

struct	DQOPMODEPRM_504_

struct	DQINITPRM_504_

struct	DQSDOWNPRM_504_

struct	DEVEEPROM_504_

struct	DQCNAMES_550_

struct	DQOPMODEPRM_550_

struct	DQINITPRM_550_

struct	DQSDOWNPRM_550_

struct	DQ553Control

struct	BCCB_Control

struct	BCCB_Status

struct	BCCB_Block

struct	DQBM553Message

struct	DQBM553MessageStor

struct	DQBM553RTSAEntry

struct	DQBM553Filter

struct	DQBM553Trigger

struct	EV553_ID

struct	DQCNAMES_553_

struct	DQOPMODEPRM_553_

struct	DQINITPRM_553_

struct	DQSDOWNPRM_553_

struct	DEVEEPROM_553_

struct	SL553CUST_LUT

struct	DQMSG_566

struct	DQMSG_566_L

struct	DQCNAMES_566_

struct	DQOPMODEPRM_566_

struct	DQINITPRM_566_

struct	DQSDOWNPRM_566_

struct	DEVEEPROM_566_

struct	EV601_ID

struct	DQCNAMES_601_

struct	DQCALSET_601_

struct	DQOPMODEPRM_601_

struct	DEVEEPROM_601_

struct	DQCHNLSET_601_

struct	DQWMSET_601_

struct	DQMSG_601

struct	DQMSG_601_L

struct	DQCNAMES_604_

struct	DQCALSET_604_

struct	DQOPMODEPRM_604_

struct	DEVEEPROM_604_

struct	DQCHNLSET_604_

struct	DQMSG_604

struct	DQCNAMES_651_

struct	DQCALSET_651_

struct	DQINITPRM_651_

struct	DQOPMODEPRM_651_

struct	DQSDOWNPRM_651_

struct	DQPRMFLAGS_651_

struct	DQCNAMES_801_

struct	DQCALSET_801_

struct	DQOPMODEPRM_801_

struct	DEVEEPROM_801_

struct	DQCHNLSET_801_

struct	DQWMSET_801_

struct	DQMSG_801

struct	DQFGC

struct	DQCDU

struct	DQCNAMES_802_

struct	DQCALSET_802_

struct	DQOPMODEPRM_802_

struct	DEVEEPROM_802_

struct	DQCHNLSET_802_

struct	DQWMSET_802_

struct	DQMSG_802

struct	DQMAN

struct	DQCNAMES_90x_

struct	DQOPMODEPRM_90x_

struct	DQINITPRM_90x_

struct	DQSDOWNPRM_90x_

struct	DQCNAMES_91x_

struct	DQCALSET_91x_

struct	DQINITPRM_91x_

struct	DQOPMODEPRM_91x_

struct	DQSDOWNPRM_91x_

struct	DQPRMFLAGS_91x_

struct	DQCNAMES_LAYER_

struct	DQCALSET_LAYER_

struct	DQOPMODEPRM_LAYER_

Macros
#define	MAXCHAN (64)

#define	DQ_ONEVOLTINNV (1000000000)

#define	DQ_MAXDEVN (0x20)

#define	DQ_MASKDEVN (0x1F)

#define	DQ_MAXDEVPHYS (0x10)

#define	DQ_MAXSS (8)

#define	DQ_MASKSS (0x7)

#define	DQ_SS0IN (0)

#define	DQ_SS0OUT (1)

#define	DQ_SS1IN (2)

#define	DQ_SS1OUT (3)

#define	DQ_SS2IN (4)

#define	DQ_SS2OUT (5)

#define	DQ_SS3IN (6)

#define	DQ_SS3OUT (7)

#define	DQ_DIR_MASK (1)

#define	DQ_LN_DATASZ8 (1L)

#define	DQ_LN_DATASZ16 (2L)

#define	DQ_LN_DATASZ24 (3L)

#define	DQ_LN_DATASZ32 (4L)

#define	DQ_IOMODE_NAMEDPRM (0x20)

#define	DQ_IOMODE_MODEMASK (0x3f)

#define	DQ_IOMODE_STORE (0x80)

#define	DQ_IOMODE_GETPRM (0x40)

#define	DQ_IOMODE_INIT (1L)

#define	DQ_IOMODE_CFG (2L)

#define	DQ_IOMODE_OPS (4L)

#define	DQ_IOMODE_SD (8L)

#define	DQ_IOMODE_MASK (0x3fff)

#define	DQ_IOMODE_SLEEP (0x3)

#define	DQ_IOMODE_PWRDN (0x9)

#define	DQ_IOMODE_PWRUP (0xA)

#define	DQ_IOMODE_NAMES (0xB)

#define	DQ_IOMODE_EECMNDEVS (0xC)

#define	DQ_IOMODE_EEFLAGS (0xD)

#define	DQ_IOM_ACCESS_GETPRM (DQ_IOMODE_GETPRM)

#define	DQ_IOM_ACCESS_MODEMASK (DQ_IOMODE_MODEMASK)

#define	DQ_IOM_ACCESS_INIT (DQ_IOMODE_INIT)

#define	DQ_IOM_ACCESS_CALIBR (DQ_IOMODE_CFG)

#define	DQ_IOM_ACCESS_OPERS (DQ_IOMODE_OPS)

#define	DQ_IOM_ACCESS_SHUTDOWN (DQ_IOMODE_SD)

#define	DQ_IOM_ACCESS_NAMEDPRM (DQ_IOMODE_NAMEDPRM)

#define	DQ_IOM_ACCESS_NAMES (DQ_IOMODE_NAMES)

#define	DQ_IOM_ACCESS_EECMNDEVS (DQ_IOMODE_EECMNDEVS)

#define	DQ_IOPRM_INIT (0x1)

#define	DQ_IOPRM_CFG (0x2)

#define	DQ_IOPRM_OPS (0x4)

#define	DQ_IOPRM_SD (0x8)

#define	DQ_IOPRM_SLEEP (0x10)

#define	DQ_IOPRM_PWRDN (0x20)

#define	DQ_IOPRM_PWRUP (0x40)

#define	DQ_IOPRM_NAMES (0x80)

#define	DQ_IOPRM_NBUFS (0x100)

#define	DQ_IOPRM_CLPERINT (0x200)

#define	DQ_IOPRM_RESERVED0 (0x300)

#define	DQ_IOPRM_ADDLDELAY (0x400)

#define	DQ_IOPRM_EECMNDEVS (0x800)

#define	DQ_IOPRM_RQID (0x1000)

#define	DQ_IOPRM_EEFLAGS (0x2000)

#define	DQ_WD_CLEAR_DISABLED (0)

#define	DQ_WD_CLEAR_ON_CONSOLE (1L<<0)

#define	DQ_WD_CLEAR_ON_RECEIVE (1L<<1)

#define	DQ_WD_CLEAR_ON_TRANSMIT (1L<<2)

#define	DQ_WD_CLEAR_ON_OSTASK (1L<<3)

#define	DQ_WD_CLEAR_RESET (1L<<14)

#define	DQ_WD_CLEAR_STATUS (1L<<15)

#define	DQ_FIFO_NBUFS_MIN (64)

#define	DQ_FIFO_NBUFS (1024)

#define	DQ_FIFO_NBUFS_SLOW (512)

#define	DQ_FIFO_NBUFS_MED (1024)

#define	DQ_FIFO_NBUFS_FAST (2048)

#define	DQ_FIFO_NBUFS_MSG (1024)

#define	DQ_FIFO_REDUCE_SLOW (64)

#define	DQ_FIFO_REDUCE_MED (128)

#define	DQ_FIFO_REDUCE_FAST (256)

#define	DQ_FIFO_REDUCE_MSG (128)

#define	DQ_FIFO_CLPERINT (0)

#define	DQ_FIFO_BUF_SEC (5)

#define	DQ_FIFO_BUF_MAX (4096)

#define	DQ_FIFO_ALLOC_AT_ONCE (1)

#define	DQ_MAX_ETH_SIZE_100 (1518)

#define	DQ_MAX_UDP_SIZE_100 (1472)

#define	DQ_MAX_ETH_SIZE (576)

#define	ETH_HDR_SIZE (14)

#define	IP_HDR_SIZE (20)

#define	UDP_HDR_SIZE (8)

#define	UDP_HDR_OFFSET (ETH_HDR_SIZE + IP_HDR_SIZE)

#define	DQ_MAX_INFO_SIZE (2048)

#define	DQ_MAX_INFO_ITEMS (100)

#define	DQ_FIFO_GET_DATA (0x10)

#define	DQ_FIFO_GET_CAL (0x20)

#define	DQ_FIFO_GET_CUSTOM (0x30)

#define	DQ_FIFO_SET_DATA (0x10)

#define	DQ_FIFO_PUT_COEFF (0x20)

#define	DQ_FIFO_PUT_CUSTOM (0x30)

#define	DQTID_PUSH_DATA (0x80000001)

#define	DQIOCTL_CVTCHNL (1)

#define	DQIOCTL_SETPARAM (2)

#define	DQIOCTL_GETPARAM (3)

#define	DQIOCTL_SETFILTER (4)

#define	DQIOCTL_SIGROUTING (5)

#define	DQIOCTL_EXT_DEVICE (0x2601)

#define	DQIOCTL_DLTRIGGER (0x11)

#define	DQIOCTL_DLCFG (0x12)

#define	DQIOCTL_SD_CTRL (0x13)

#define	DQIOCTL_PROGRESS (0x14)

#define	DQIOCTL_GET_DATA (0x15)

#define	DQIOCTL_DL_CTRL (0x16)

#define	DQIOCTL_DLOGGER (0x10)

#define	DQIOCTL_VDD_SETTRL (0x21)

#define	DQIOCTL_VDD_FINISHTRL (0x22)

#define	DQIOCTL_VDD_CONFIG (0x23)

#define	DQIOCTL_VDD_SETTMRSRC (0x24)

#define	DQIOCTL_HW_CPUTEST (0x40)

#define	DQIOCTL_HW_CPUTEST_START (0x41)

#define	DQIOCTL_HW_CPUTEST_ABORT (0x42)

#define	DQIOCTL_HW_CPUTEST_GET_STATUS (0x43)

#define	DQIOCTL_HW_CPUTEST_GET_RESULT (0x44)

#define	DQIOCTL_HW_NWTEST (0x45)

#define	DQIOCTL_HW_IOMTEST (0x80)

#define	HW_IOMTEST_BUS (0x1)

#define	DQ_LN_INTSRC (1<<0)

#define	DQ_SETPASS_SUPASS (1L << 0)

#define	DQ_SETPASS_USRPASS (1L << 1)

#define	DQ_SETPASS_SETSU (1L << 2)

#define	DQ_SETPASS_SETUSR (1L << 3)

#define	DQ_SETPASS_CLEAR (1L << 4)

#define	DQSETLOCK_LOCK (0)

#define	DQSETLOCK_UNLOCK (1)

#define	DQSETLOCK_CHECK (2)

#define	DQSETLOCK_CHECKDIAG (3)

#define	DQSETLOCK_DIAG (4)

#define	DQ_LN_NO_TIMESTAMP_RESET (1L<<21)

#define	DQ_LN_VMAPPED (1L<<20)

#define	DQ_LN_BURST (1L<<19)

#define	DQ_LN_RAW32 (1L<<18)

#define	DQ_FIFO_MODESCAN (0L<<16)

#define	DQ_FIFO_MODEFIFO (2L<<16)

#define	DQ_FIFO_MODECONT (3L<<16)

#define	DQ_LN_MAPPED (1L<<15)

#define	DQ_LN_STREAMING (1L<<14)

#define	DQ_LN_RECYCLE (1L<<13)

#define	DQ_LN_GETRAW (1L<<12)

#define	DQ_LN_TMREN (1L<<11)

#define	DQ_LN_IRQEN (1L<<10)

#define	DQ_LN_PTRIGEDGE1 (1L<<9)

#define	DQ_LN_PTRIGEDGE0 (1L<<8)

#define	DQ_LN_STRIGEDGE1 (1L<<7)

#define	DQ_LN_STRIGEDGE0 (1L<<6)

#define	DQ_LN_CVCKSRC1 (1L<<5)

#define	DQ_LN_CVCKSRC0 (1L<<4)

#define	DQ_LN_CLCKSRC1 (1L<<3)

#define	DQ_LN_CLCKSRC0 (1L<<2)

#define	DQ_LN_ACTIVE (1L<<1)

#define	DQ_LN_ENABLED (1L<<0)

#define	SS_DIR_MASK (0x1)

#define	DQ_DIR_INPUT (0)

#define	DQ_DIR_OUTPUT (1)

#define	DQ_DMAP_RESET_TRL (1L<<31)

#define	DQ_VMAP_FIFO_STATUS (1L<<0)

#define	DQ_VMAP_SPEC_CHANNEL (1L<<1)

#define	DQ_VMAP_FIFO_RQSIZE (1L<<2)

#define	DQ_DMAP_LASTID_IN (0x0FF0L)

#define	DQ_DMAP_LASTID_OUT (0x0FF1L)

#define	DQ_DMAP_IDMASK (0xfff)

#define	DQ_DMAP_MODEMASK (0xf000)

#define	DQ_DMAP_DMAP (0x0000)

#define	DQ_DMAP_VMAP (0x1000)

#define	DQ_LNCL_LAST (0)

#define	DQ_LNCL_NEXT (1UL<<31)

#define	DQ_LNCL_INOUT (1UL<<30)

#define	DQ_LNCL_SS1 (1UL<<29)

#define	DQ_LNCL_SS0 (1UL<<28)

#define	DQ_LNCL_IRQ (1UL<<27)

#define	DQ_LNCL_NOWAIT (1UL<<26)

#define	DQ_LNCL_SKIP (1UL<<25)

#define	DQ_LNCL_CLK (1UL<<24)

#define	DQ_LNCL_CTR (1UL<<23)

#define	DQ_LNCL_WRITE (1UL<<22)

#define	DQ_LNCL_UPDALL (1UL<<21)

#define	DQ_LNCL_TSRQ (1UL<<20)

#define	DQ_LNCL_SLOW (1UL<<19)

#define	DQ_LNCL_DIO (1UL<<18)

#define	DQ_LNCL_RSVD1 (1UL<<17)

#define	DQ_LNCL_RSVD0 (1UL<<16)

#define	DQ_LNCL_DIFF (1UL<<15)

#define	DQ_LNCL_GAIN(G) (((G) & 0xf)<<8)

#define	DQ_LNCL_CHANGAIN(C, G) ((C)\|DQ_LNCL_GAIN(G))

#define	DQ_LNCL_TIMESTAMP (0xff)

#define	DQ_LNCL_READSTATUS (0xfe)

#define	DQ_LNCL_GETGAIN(E) (((E) & 0xf00)>>8)

#define	DQ_LNCL_GETCHAN(E) ((E) & 0xff)

#define	DQ_EXTRACT_SS(flags) (((flags) & (DQ_LNCL_SS1 \| DQ_LNCL_SS0)) >> 28)

#define	DQ_EXTRACT_DIR(flags) (((flags) & DQ_LNCL_INOUT) >> 30)

#define	DQ_SS_DIR(ss, dir) (((ss) << 1) \| (dir))

#define	DQ_LN_CLKID_DUTY1 (1L<<7)

#define	DQ_LN_CLKID_DUTY0 (1L<<6)

#define	DQ_LN_CLKID_TMR1 (1L<<5)

#define	DQ_LN_CLKID_TMR0 (1L<<4)

#define	DQ_LN_CLKID_CVIN (1L<<3)

#define	DQ_LN_CLKID_CVOUT (1L<<2)

#define	DQ_LN_CLKID_CLIN (1L<<1)

#define	DQ_LN_CLKID_CLOUT (1L<<0)

#define	DQ_LN_CALGAIN (1L<<1)

#define	DQ_LN_CALOFFS (1L<<2)

#define	DQ_LN_1us_TIMESTAMP (66-1)

#define	DQ_LN_10us_TIMESTAMP (660-1)

#define	DQ_LN_100us_TIMESTAMP (6600-1)

#define	DQ_LN_1ms_TIMESTAMP (66000-1)

#define	DQ_LN_10ms_TIMESTAMP (660000-1)

#define	DQ_LN_100ms_TIMESTAMP (6600000-1)

#define	DQ_LN_1s_TIMESTAMP (66000000-1)

#define	DQ_FPGAC_PRGEN (1L<<15)

#define	DQ_FPGAC_NCFG (1L<<14)

#define	DQ_FPGAC_MSEL1 (1L<<13)

#define	DQ_FPGAC_MSEL0 (1L<<12)

#define	DQ_FPGAC_DOE1 (1L<<11)

#define	DQ_FPGAC_DOE0 (1L<<10)

#define	DQ_FPGAC_DCLR1 (1L<< 9)

#define	DQ_FPGAC_DCLR0 (1L<< 8)

#define	DQ_FPGAC_ED (1L<< 7)

#define	DQ_FPGAC_ASPGEN (1L<< 6)

#define	DQ_FPGAC_ASDO (1L<< 5)

#define	DQ_FPGAC_NCEO (1L<< 4)

#define	DQ_FPGAC_NCSO (1L<< 3)

#define	DQ_FPGAC_RESERVED2 (1L<< 2)

#define	DQ_FPGAC_RESERVED1 (1L<< 1)

#define	DQ_FPGAC_RESERVED0 (1L<< 0)

#define	DQ_FPGAS_RDY (1L<<12)

#define	DQ_FPGAS_NCFG (1L<<11)

#define	DQ_FPGAS_NSTAT (1L<<10)

#define	DQ_FPGAS_CONFDONE (1L<< 9)

#define	DQ_FPGAS_DCLK (1L<< 8)

#define	DQ_FPGAS_DATA0 (1L<< 7)

#define	DQ_FPGAS_MSEL1 (1L<< 6)

#define	DQ_FPGAS_MSEL0 (1L<< 5)

#define	DQ_FPGAS_ASDO (1L<< 4)

#define	DQ_FPGAS_NCEO (1L<< 3)

#define	DQ_FPGAS_NCSO (1L<< 2)

#define	DQ_FPGAS_DOE (1L<< 1)

#define	DQ_FPGAS_DCLR (1L<< 0)

#define	DQ_TRIGGER_SET_OR (1L<< 5)

#define	DQ_TRIGGER_SET (1L<< 4)

#define	DQ_TRIGGER_ONCE (1L<< 3)

#define	DQ_TRIGGER_RESET (1L<< 2)

#define	DQ_TRIGGER_STOP (1L<< 1)

#define	DQ_TRIGGER_START (1L<< 0)

#define	DQ_EXT_CLKIN (0x30)

#define	DQ_EXT_TRIGIN (0x31)

#define	DQ_EXT_BURST (0x32)

#define	DQ_EXT_CLOCK (0x33)

#define	DQ_EXT_EXT0 (0x34)

#define	DQ_EXT_EXT1 (0x35)

#define	DQ_EXT_CLKIN_J3_10 (DQ_EXT_EXT0)

#define	DQ_EXT_TRIGIN_J3_6 (DQ_EXT_EXT1)

#define	DQ_EXT_INTER0 (0x36)

#define	DQ_EXT_SYNC0 (0x10)

#define	DQ_EXT_SYNC1 (0x11)

#define	DQ_EXT_SYNC2 (0x12)

#define	DQ_EXT_SYNC3 (0x13)

#define	DQ_EXT_RELEASE (0)

#define	DQ_EXT_IMMEDIATE (0x80)

#define	DQ_EXT_START_TRIG (0x20)

#define	DQ_EXT_STOP_TRIG (0x21)

#define	DQ_EXT_CLIN (0x22)

#define	DQ_EXT_CLOUT (0x23)

#define	DQ_EXT_CVIN (0x24)

#define	DQ_EXT_CVOUT (0x25)

#define	DQ_EXT_GPIO_LOGIC0 (0x26)

#define	DQ_EXT_GPIO_LOGIC1 (0x27)

#define	DQ_EXT_INT0 (0x28)

#define	DQ_EXT_INT1 (0x29)

#define	DQ_EXT_CLKOUT_J3_8 (DQ_EXT_INT0)

#define	DQ_EXT_TRIGOUT_J3_4 (DQ_EXT_INT1)

#define	DQ_EXT_DIO0 (0x2A)

#define	DQ_EXT_DIO1 (0x2B)

#define	DQ_EXT_ADCCVT (0x2C)

#define	DQ_EXT_TSTD (0x2D)

#define	DQ_EXT_PUSH_BUTTON (0x2E)

#define	DQ_EXT_ADCBS (0x2F)

#define	DQ_EDGE_RISING (0)

#define	DQ_EDGE_FALLING (1)

#define	DQ_EXT_DIO_DEFAULT (0x0)

#define	DQ_EXT_DIO_INPUT (0x1)

#define	DQ_EXT_DIO_OUTPUT (0x2)

#define	DQ_EXT_DIO_INVERTED (0x10)

#define	DQ_LN_MAX_SYNCX (4)

#define	DQ_LN_MAX_DIOX (4)

#define	DQ_LN_MAX_CLOCKS (4)

#define	DQ_LN_MAX_TRIGS (4)

#define	DQ_EXT_SIG_CMD_DEF (0)

#define	DQ_EXT_SIG_CMD_DIO_RW (1)

#define	DQ_EXT_SIG_CMD_DIO_R (2)

#define	DQ_EXT_SIG_CMD_SET_SYS (0x20)

#define	DQ_ACCESS_DIO_DIO0_ENB (0x1)

#define	DQ_ACCESS_DIO_DIO1_ENB (0x2)

#define	DQ_ACCESS_DIO_DIO2_ENB (0x4)

#define	DQ_ACCESS_DIO_DIO3_ENB (0x8)

#define	DQ_ACCESS_DIO_DIO0_OUT (0x10)

#define	DQ_ACCESS_DIO_DIO0_IN (0)

#define	DQ_ACCESS_DIO_DIO1_OUT (0x20)

#define	DQ_ACCESS_DIO_DIO1_IN (0)

#define	DQ_ACCESS_DIO_DIO2_OUT (0x40)

#define	DQ_ACCESS_DIO_DIO2_IN (0)

#define	DQ_ACCESS_DIO_DIO3_OUT (0x80)

#define	DQ_ACCESS_DIO_DIO3_IN (0)

#define	DQ_EXT_CLIN_OFS (0)

#define	DQ_EXT_CLOUT_OFS (1)

#define	DQ_EXT_CVIN_OFS (2)

#define	DQ_EXT_CVOUT_OFS (3)

#define	DQ_EXT_BOTH_CV_CL_FLAG (0x10)

#define	DQ_EXT_START_TRIG_OFS (0)

#define	DQ_EXT_STOP_TRIG_OFS (1)

#define	DQ_EXT_SYNC0_OFS (0)

#define	DQ_EXT_SYNC1_OFS (1)

#define	DQ_EXT_SYNC2_OFS (2)

#define	DQ_EXT_SYNC3_OFS (3)

#define	DQ_EXT_DIO0_OFFS (0)

#define	DQ_EXT_DIO1_OFFS (1)

#define	DQ_EXT_DIO2_OFFS (2)

#define	DQ_EXT_DIO3_OFFS (3)

#define	DQ_SYNC_DEVN (0xD)

#define	DQ_CPU_DEVN (0xE)

#define	DQ_BROADCAST_DEVN (0xF)

#define	DQ_SYNC_NOT_CONN (0)

#define	DQ_SYNC_INPUT (1)

#define	DQ_SYNC_DRIVER (2)

#define	DQ_SYNC_EXTERNAL (4)

#define	DQ_SYNC_0 (8)

#define	DQ_SYNC_1 (16)

#define	DQ_SYNC_BUTTON (32)

#define	DQ_SYNC_CLOCK (0)

#define	DQ_SYNC_TRIGGER (1)

#define	DQ_SYNC_PPC (0)

#define	DQ_SYNC_PLL (1)

#define	DQ_SYNC_PPC2 (2)

#define	DQ_SYNC_PLL_IMMEDIATE (3)

#define	CY22150_MINP (8)

#define	CY22150_MINQ (5)

#define	CY22150_MAXP (800)

#define	CY22150_MAXQ (129)

#define	CY22150_MIN_VCO (100000000.0)

#define	CY22150_MAX_VCO (365000000.0)

#define	CY22150_BASE (66000000)

#define	DQ_C3PLL_MIN_N (2)

#define	DQ_C3PLL_MAX_N (510)

#define	DQ_C3PLL_MIN_M (2)

#define	DQ_C3PLL_MAX_M (510)

#define	DQ_C3PLL_MIN_VCO (600000000.0)

#define	DQ_C3PLL_MAX_VCO (1300000000.0)

#define	DQ_C3PLL_BASE (66000000)

#define	BUS_FREQUENCY (66000000)

#define	DQ_DEVNAME_SIZE (40)

#define	DQ_CLSZ (0x40)

#define	DQ_CFG_RECORD_SIZE (0x2000) /* our parameters can be as big as 8kB */

#define	DQMAXUDP (530 - DQHSZ)

#define	DQHSZ sizeof (DQPKT)

#define	DQ_ACB_HEADERSZ (ETH_HDR_SIZE + IP_HDR_SIZE + UDP_HDR_SIZE + DQHSZ + DQFIFOHSZ + sizeof(uint32))

#define	DQ_DQPKT_OFFS (ETH_HDR_SIZE + IP_HDR_SIZE + UDP_HDR_SIZE)

#define	DQ_READCOMM (1)

#define	DQ_WRITECOMM (2)

#define	DQFIFOHSZ (4)

#define	EP1C3_FILE_SIZE (78422)

#define	EP1C4_FILE_SIZE (115564)

#define	EP1C6_FILE_SIZE (145902)

#define	EP1C12_FILE_SIZE (209405)

#define	EP1C20_FILE_SIZE (444951)

#define	EP2C5_FILE_SIZE (152998)

#define	EP2C8_FILE_SIZE (247974)

#define	EP2C15_FILE_SIZE (486562)

#define	EP2C20_FILE_SIZE (486562)

#define	EP2C35_FILE_SIZE (857332)

#define	EP2C50_FILE_SIZE (1245424)

#define	EP2C70_FILE_SIZE (1789902)

#define	FPGA_IMAGE_MAX_SIZE (EP2C70_FILE_SIZE)

#define	LOGIC_PROG_DEV_LIST_SZ 16

#define	LPERR_OK (1)

#define	LPERR_BUSY /0xFFFFFF9C/ (-100)

#define	LPERR_CMDRD /0xFFFFFF9B/ (-101)

#define	LPERR_CMDWR /0xFFFFFF9A/ (-102)

#define	LPERR_ADDROUTRANGE /0xFFFFFF99/ (-103)

#define	LPERR_UNABLECOMMSP /0xFFFFFF98/ (-104)

#define	LPERR_MEMALOC /0xFFFFFF97/ (-105)

#define	LPERR_EPCSOVERFULL /0xFFFFFF96/ (-106)

#define	LPERR_BADCRC /0xFFFFFF95/ (-107)

#define	LPERR_IMGVERSIZE /0xFFFFFF94/ (-108)

#define	LPERR_SUPASS /0xFFFFFF93/ (-109)

#define	LPERR_IO2_EMPTY_NOREPROG /0xFFFFFF92/ (-110)

#define	LPERR_IO3_NOT_EMPTY /0xFFFFFF91/ (-111)

#define	LPERR_WRONG_CPU_MODEL /0xFFFFFF90/ (-112)

#define	LPERR_NOREPROG /0xFFFFFF8F/ (-113)

#define	LPERR_IO_NOT_EMPTY /0xFFFFFF8E/ (-114)

#define	LPERR_IO1_12_NOT_EMPTY /0xFFFFFF8D/ (-115)

#define	DNx_ADDR_BUS_TEST_MASK (0x0000FFFC)

#define	DQ_PPC_FLASH_ADDRESS (0xFFC00000)

#define	DQ_PPC_FLASH_SIZE (0x00400000)

#define	DQ_PPC_FLASH_FIRMWARE_OFFSET (0x00010000)

#define	DQ_FIRMWARE_ENTRY_ROM (0xFFC10000)

#define	DQ_UBOOT_ENTRY_ROM (0xFFF00100)

#define	DQ_FLASH_ADDRESS (DQ_PPC_FLASH_ADDRESS)

#define	DQ_FLASH_SIZE (DQ_PPC_FLASH_SIZE)

#define	DQ_FLASH_FIRMWARE_OFFSET (DQ_PPC_FLASH_FIRMWARE_OFFSET)

#define	SDRAM_ADDRESS (0x00000000)

#define	EXT_DEV_ADDRESS2 (0xA0000000)

#define	IOM_BASE_ADDRESS (0xA00E0000)

#define	EXT_DEV_ADDRESS3 (0xA0100000)

#define	EXT_DEV_ADDRESS4 (0xA0200000)

#define	EXT_DEV_ADDRESS5 (0xA0300000)

#define	IOM_BASE_IRQ (2)

#define	EXT_DEV_SIZE (0x01000000)

#define	DL_ERROR_MASK (0x80000000)

#define	DL_IDLE (0)

#define	DL_WAIT_MASTER (0)

#define	DL_OK (1)

#define	DL_RUNNING (2)

#define	DL_STOPPED (4)

#define	DL_ERROR (0x80000000)

#define	DL_ERR_MASTER_CFG (0x80010000)

#define	DL_ERR_ALARM_CFG (0x80020000)

#define	DL_ERR_LAYER_CFG (0x80040000)

#define	DL_ERR_OP_ERROR (0x80080000)

#define	DL_SDSTAT_UNKNOWN (0x0)

#define	DL_SDSTAT_OK (0x1)

#define	DL_SDSTAT_RDONLY (0x2)

#define	DL_SDSTAT_NO_CARD (0x3)

#define	DL_SDSTAT_WR_ERR (0x80010000)

#define	DL_SDSTAT_RD_ERR (0x80020000)

#define	DL_SDSTAT_FULL (0x80040000)

#define	DL_LYSTATE_IDLE (0)

#define	DL_LYSTATE_STRIG (1)

#define	DL_LYSTATE_RUNNING (2)

#define	DL_LYSTATE_ERROR (0x80010000)

#define	DL_LYSTATE_FIFOOVF (0x80020000)

#define	DL_LYSTATR_BUFOVF (0x80040000)

#define	DL_LYSTATR_CFGERR (0x80080000)

#define	DL_LYSTATR_WRONGMOD (0x80100000)

#define	DL_SD_CTRL_GETFREE 1

#define	DL_SD_CTRL_FORMAT 2

#define	DL_SD_CTRL_CANCEL 3

#define	DL_SD_CTRL_RESET 4

#define	DL_SD_CTRL_ISDONE 5

#define	DL_DL_CTRL_CANCEL 1

#define	DL_DL_CTRL_RESET 2

#define	DL_GET_CHN_LST 1

#define	DL_GET_LAST_SCAN 2

#define	LNPRM_MODID 0x101

#define	LNPRM_MODOPT 0x102

#define	LNPRM_IOMSN 0x103

#define	LNPRM_IOMMFG 0x104

#define	LNPRM_IOMFRQ 0x105

#define	LNPRM_TICK 0x106

#define	LNPRM_PERIOD 0x107

#define	LNPRM_WDDLY 0x108

#define	LNPRM_TIME 0x109

#define	LNPRM_OPTIONS 0x10A

#define	LNPRM_COMDLY 0x110

#define	LNPRM_LNID 0x201

#define	LNPRM_LNOPT 0x202

#define	LNPRM_LNSN 0x203

#define	LNPRM_TOTAL 0x204

#define	LNPRM_LNMFG 0x205

#define	LNPRM_LNCAL 0x206

#define	LNPRM_LNEXP 0x207

#define	LNPRM_DQREV 0x208

#define	LNPRM_FWREV 0x209

#define	LNPRM_NOCHANGE 0xF0000000

#define	LNPRM_BYOFFS 0xF0100000

#define	LNPRM_RDONLY 0xF0000000

#define	LNPRM_DEVIOM 0xFE

#define	LNPRM_DEVALL 0xFF

#define	DQ_PPC8347_FLASH_ADDRESS (0xFE000000)

#define	DQ_PPC8347_FLASH_SIZE (0x02000000)

#define	DQ_PPC8347_FLASH_FIRMWARE_OFFSET (0x01800000)

#define	INT_DNR_POWER_ADDRESS 0xA00C0000

#define	INT_GIGE_POWER_ADDRESS 0xA00D0000

#define	INT_GIGE_LOGIC_ADDRESS 0xA00E0000

#define	INT_CM2_LOGIC_ADDRESS 0xA00E0000

#define	DQ_PROLOG 0xBABAFACA /* DqTS id */

#define	DQ_PLGVT1 0xBABAFACB /* DqVT first or not last packet id */

#define	DQ_PLGVTL 0xBABAFACC /* DqVT last or only packet id */

#define	DQPROLOGVER 0xBABAFAC2 /* request supported DQ version */

#define	DQERR_MASK 0xFFFF0000

#define	DQNOERR_MASK 0x0000FFFF

#define	DQERR_NIBMASK 0xF0000000 /* general error/status mask */

#define	DQERR_MULTFAIL 0x80000000 /* high bit - multiple bits indicate error/status */

#define	DQERR_SINGFAIL 0x90000000 /* low bit in first nybble - single error/status */

#define	DQERR_BITS 0x0FFF0000 /* error/status bits or value extracted from here */

#define	DQERR_GENFAIL 0xF0000000 /* general error/status mask */

#define	DQERR_OVRFLW 0x80010000 /* Data extraction too slow - data overflow */

#define	DQERR_STARTED 0x80020000 /* Start trigger is received */

#define	DQERR_STOPPED 0x80040000 /* Stop trigger is received */

#define	DQERR_EXEC 0x90010000 /* exception on command execution */

#define	DQERR_NOMORE 0x90020000 /* no more data is available */

#define	DQERR_MOREDATA 0x90030000 /* more data is available */

#define	DQERR_TOOOLD 0x90040000 /* request is too old (RDFIFO) */

#define	DQERR_INVREQ 0x90050000 /* Invalid request number (RDFIFO) */

#define	DQERR_NIMP 0x90060000 /* DQ not implemented or unknown command */

#define	DQERR_ACCESS 0x90070000 /* password is not cleared - access denied */

#define	DQERR_LOCKED 0x90080000 /* cube is locked */

#define	DQERR_DIAG 0x90090000 /* Command not allowed on diagnostics port */

#define	DQERR_WRONGID 0x900A0000 /* Wrong VMap or DMap ID */

#define	DQERR_OPS 0x90070000 /* IOM is in operation state */

#define	DQERR_PARAM 0x90080000 /* Device cannot complete request with specified parameters */

#define	DQERR_RCV 0x90090000 /* packet receive error */

#define	DQERR_SND 0x900A0000 /* packet send error */

#define	DQERR_NOSEND 0xA1000000 /* do not return packet */

#define	DQERR_PENDING 0xA2000000 /* do not return packet, do not free buffer */

#define	DQERR_KEEP_PKT 0xA4000000 /* keep reply packet */

#define	DQERR_CLEAR_REPLY_MASK 0xffff; /* only packet length */

#define	TRLISTSZ 256

#define	MAXDMAPS (DQ_MAXDEVN * DQ_MAXSS)

#define	CHLISTSZ 128

#define	DQ_CF_UPUSER_SEC (4) /* start user sector CF5272*/

#define	DQ_PPC_UPUSER_SEC (8) /* start user sector PPC5200 */

#define	DQ_PPC8347_UPUSER_SEC (192) /* start user sector MPC8347 */

#define	STS_STATE (0)

#define	STS_POST (1)

#define	STS_FW (2)

#define	STS_LOGIC (3)

#define	STS_STATE_TS_SH 8

#define	STS_STATE_TS_INS(S, TS) ((S & 0xffff00ff)\|((TS<<8) & 0xff00))

#define	STS_STATE_STICKY (0)

#define	STS_LOGIC_DC_OOR (1UL<<0)

#define	STS_LOGIC_DC_FAILED (1UL<<1)

#define	STS_LOGIC_TRIG_START (1UL<<2)

#define	STS_LOGIC_TRIG_STOP (1UL<<3)

#define	STS_LOGIC_CLO_NOT_RUNNING (1UL<<4)

#define	STS_LOGIC_CLI_NOT_RUNNING (1UL<<5)

#define	STS_LOGIC_CVCLK_CLO_ERR (1UL<<6)

#define	STS_LOGIC_CVCLK_CLI_ERR (1UL<<7)

#define	STS_LOGIC_CLCLK_CLO_ERR (1UL<<8)

#define	STS_LOGIC_CLCLK_CLI_ERR (1UL<<9)

#define	STS_LOGIC_CALIBRATING (1UL<<30)

#define	STS_LOGIC_NO_REPORTING (1UL<<31)

#define	STS_LOGIC_STICKY (STS_LOGIC_NO_REPORTING\|STS_LOGIC_CALIBRATING)

#define	STS_FW_CLK_OOR (1UL<<0)

#define	STS_FW_SYNC_ERR (1UL<<1)

#define	STS_FW_CHNL_ERR (1UL<<2)

#define	STS_FW_BUF_SCANS_PER_INT (1UL<<3)

#define	STS_FW_BUF_SAMPS_PER_PKT (1UL<<4)

#define	STS_FW_BUF_RING_SZ (1UL<<5)

#define	STS_FW_BUF_PREBUF_SZ (1UL<<6)

#define	STS_FW_BAD_CONFIG (1UL<<7)

#define	STS_FW_BUF_OVER (1UL<<8)

#define	STS_FW_BUF_UNDER (1UL<<9)

#define	STS_FW_LYR_FIFO_OVER (1UL<<10)

#define	STS_FW_LYR_FIFO_UNDER (1UL<<11)

#define	STS_FW_EEPROM_FAIL (1UL<<12)

#define	STS_FW_GENERAL_FAIL (1UL<<13)

#define	STS_FW_ISO_TIMEOUT (1UL<<14)

#define	STS_FW_CLIO_FAIL (1UL<<15)

#define	STS_FW_OUT_FAIL (1UL<<16)

#define	STS_FW_IO_FAIL (1UL<<17)

#define	STS_FW_NO_MEMORY (1UL<<18)

#define	STS_FW_BAD_OPER (1UL<<19)

#define	STS_FW_LAYER_ERR (1UL<<20)

#define	STS_FW_OVERLOAD (1UL<<21)

#define	STS_FW_DIAG_0 (1UL<<3)

#define	STS_FW_DIAG_1 (1UL<<4)

#define	STS_FW_CONFIG_DONE (1UL<<30)

#define	STS_FW_OPER_MODE (1UL<<31)

#define	STS_POST_MEM_FAIL (1L<<0)

#define	STS_POST_EEPROM_FAIL (1L<<1)

#define	STS_POST_LAYER_FAILED (1L<<2)

#define	STS_POST_FLASH_FAILED (1L<<3)

#define	STS_POST_SDCARD_FAILED (1L<<4)

#define	STS_POST_DC24 (1L<<5)

#define	STS_POST_DCCORE (1L<<6)

#define	STS_POST_BUSTEST_FAILED (1L<<7)

#define	STS_POST_BUSFAIL_DATA (1L<<8)

#define	STS_POST_BUSFAIL_ADDR (1L<<9)

#define	STS_POST_OVERHEAT (1L<<10)

#define	STS_POST_OVERCURRENT (1L<<11)

#define	STS_POST_RESET_FAILED (1L<<12)

#define	STS_POST_UNRECOG_LAYER (1L<<13)

#define	STS_POST_STICKY (STS_POST_MEM_FAIL\|STS_POST_BUSTEST_FAILED\|STS_POST_BUSFAIL_DATA\|STS_POST_BUSFAIL_ADDR)

#define	STS_FW_STICKY (STS_FW_EEPROM_FAIL\|STS_FW_GENERAL_FAIL)

#define	STS_FW_BAD_CONFIG_MASK (STS_FW_CLK_OOR \| STS_FW_BUF_SCANS_PER_INT \| STS_FW_BUF_SAMPS_PER_PKT \| STS_FW_BUF_RING_SZ \| STS_FW_BUF_PREBUF_SZ)

#define	STS_LOGIC_BAD_MASK (STS_LOGIC_DC_OOR \| STS_LOGIC_DC_FAILED \| STS_LOGIC_CVCLK_CLO_ERR \| STS_LOGIC_CVCLK_CLI_ERR \| STS_LOGIC_CLCLK_CLO_ERR \| STS_LOGIC_CLCLK_CLI_ERR)

#define	SET_STS_FLAG(DEV, SS, FG, FLAG) (((pDEVOBJ)(DEV))->status[(SS)&7][FG] \|= FLAG)

#define	SET_STS_FLAGp(DEV, SS, FG, FLAG) {(((pDEVOBJ)(DEV))->status[(SS)&7][FG] \|= FLAG); _printf("line=%d ss=%d sts=%x\n", __LINE__, SS,((pDEVOBJ)(DEV))->status[SS][FG]);}

#define	CLR_STS_FLAG(DEV, SS, FG, FLAG) (((pDEVOBJ)(DEV))->status[(SS)&7][FG] &= (~FLAG))

#define	IF_STS_FLAG(DEV, SS, FG, FLAG) (((pDEVOBJ)(DEV))->status[(SS)&7][FG] & (FLAG))

#define	GET_STS_FLAGS(DEV, SS, FG) (((pDEVOBJ)(DEV))->status[(SS)&7][FG])

#define	DQEVENT_SETUP 1

#define	DQEVENT_DISPATCH 2

#define	DQEVENT_ENABLE 3

#define	DQEVENT_INTERNAL 4

#define	DQEVENT_NOREPLY (1L<<31)

#define	DQEVENT_LAYER 0x1000

#define	DQAXMAP_CLEAR 1

#define	DQAXMAP_TEST 2

#define	DQAXMAP_SET_TIMING 3

#define	DQAXMAP_SET_SLOT 4

#define	DQAXMAP_ENABLE 5

#define	DQAXMAP_NOREPLY (1L<<31)

#define	DQ_PC104_CHAN (2)

#define	DQ_PC104_CALDACS (2)

#define	DQ_PC104_NAMELEN (32)

#define	DQ_PC104_INFOSZ (DQ_MAX_INFO_SIZE)

#define	DQ_PC104_BASE (66000000)

#define	DQ_PC104_MAXCLFRQ (2000)

#define	DQ_PC104_MAXCVFRQ (2000)

#define	DQ_PC104_MAXWAIT (20)

#define	DQ_PC104_LCR_DPEN (1L<<2)

#define	DQ_PC104_LCR_LED (1L<<1)

#define	DQ_PC104_IER_AE (1L<<9)

#define	DQ_PC104_IER_TO (1L<<8)

#define	DQ_PC104_IER_WBD (1L<<7)

#define	DQ_PC104_IER_RBD (1L<<6)

#define	DQ_PC104_IER_WIOD (1L<<5)

#define	DQ_PC104_IER_RIOD (1L<<4)

#define	DQ_PC104_IER_WMD (1L<<3)

#define	DQ_PC104_IER_RMD (1L<<2)

#define	DQ_PC104_IER_IRQB (1L<<1)

#define	DQ_PC104_IER_IRQA (1L<<0)

#define	DQ_PC104_DC12N_2 (1L<<7)

#define	DQ_PC104_DC12N_1 (1L<<4)

#define	DQ_PC104_DC12_5 (1L<<6)

#define	DQ_PC104_DC12_4 (1L<<5)

#define	DQ_PC104_DC12_3 (1L<<3)

#define	DQ_PC104_DC12_2 (1L<<2)

#define	DQ_PC104_DC12_1 (1L<<1)

#define	DQ_PC104_DC5N (1L<<0)

#define	DQ_PC104_CFG (0x2000)

#define	DQ_PC104_STS (0x2004)

#define	DQ_PC104_BA0 (0x2008)

#define	DQ_PC104_BA1 (0x200C)

#define	DQ_PC104_IRQA (0x2010)

#define	DQ_PC104_IRQB (0x2014)

#define	DQ_PC104_LNEN (0x2018)

#define	DQ_PC104_IRQPINS (0x201C)

#define	DQ_PC104_MEMRD (0x2020)

#define	DQ_PC104_MRADDR (0x2020)

#define	DQ_PC104_IORD (0x2024)

#define	DQ_PC104_IORADDR (0x2024)

#define	DQ_PC104_MWADDR (0x2028)

#define	DQ_PC104_MEMWR (0x202C)

#define	DQ_PC104_IOWADDR (0x2030)

#define	DQ_PC104_IOWR (0x2034)

#define	DQ_PC104_BCMD0 (0x2038)

#define	DQ_PC104_BCMD1 (0x203C)

#define	DQ_PC104_DP0 (0x8000)

#define	DQ_PC104_IRQP (0L<<6)

#define	DQ_PC104_IRQN (1L<<6)

#define	DQ_PC104_BUSCLOCK_5_5MHz (1L<<4)

#define	DQ_PC104_BUSCLOCK_6_6MHz (2L<<4)

#define	DQ_PC104_BUSCLOCK_8MHz (3L<<4)

#define	DQ_PC104_OSC_14MHz (1L<<3)

#define	DQ_PC104_BE (1L<<2)

#define	DQ_PC104_WE (1L<<1)

#define	DQ_PC104_ASSERT_RESET (1L<<0)

#define	DQ_PC104_BUSCLOCK_0 (0)

#define	DQ_PC104_STS_BTB (1L<<31)

#define	DQ_PC104_STS_IOCHK (1L<<30)

#define	DQ_PC104_STS_STAE (1L<<19)

#define	DQ_PC104_STS_STTO (1L<<18)

#define	DQ_PC104_STS_IO16TO (1L<<17)

#define	DQ_PC104_STS_M16TO (1L<<16)

#define	DQ_PC104_STS_MIO8TO (1L<<15)

#define	DQ_PC104_STS_IRQ14_15S (1L<<14)

#define	DQ_PC104_STS_IRQ12S (1L<<13)

#define	DQ_PC104_STS_IRQ11S (1L<<12)

#define	DQ_PC104_STS_IRQ10S (1L<<11)

#define	DQ_PC104_STS_IRQ7_9S (1L<<10)

#define	DQ_PC104_STS_IRQ6S (1L<<9)

#define	DQ_PC104_STS_IRQ5S (1L<<8)

#define	DQ_PC104_STS_IRQ4S (1L<<7)

#define	DQ_PC104_STS_IRQ3S (1L<<6)

#define	DQ_PC104_STS_BWD (1L<<5)

#define	DQ_PC104_STS_BRD (1L<<4)

#define	DQ_PC104_STS_IOWD (1L<<3)

#define	DQ_PC104_STS_IORD (1L<<2)

#define	DQ_PC104_STS_MWD (1L<<1)

#define	DQ_PC104_STS_MRD (1L<<0)

#define	DQ_PC104_STS_IRQ3S_SH (6)

#define	DQ_PC104_BA_SELECT (1L<<31)

#define	DQ_PC104_BA_IOSPACE (0L<<30)

#define	DQ_PC104_BA_MEMIO (1L<<30)

#define	DQ_PC104_BA_IOCHKRDY (1L<<29)

#define	DQ_PC104_BA_IOCS16 (1L<<28)

#define	DQ_PC104_BA_MEMCS16 (1L<<27)

#define	DQ_PC104_BA_AEN_A17 (1L<<26)

#define	DQ_PC104_BA_ACCESS_16 (1L<<25)

#define	DQ_PC104_BA_ALL (0xff000000)

#define	DQ_PC104_BAN(N) (((N)&0x1f)<<20)

#define	DQ_PC104_BA(N) ((N)&0xfffff)

#define	DQ_PC104_IRQ14_15S (1L<<8)

#define	DQ_PC104_IRQ12S (1L<<7)

#define	DQ_PC104_IRQ11S (1L<<6)

#define	DQ_PC104_IRQ10S (1L<<5)

#define	DQ_PC104_IRQ7_9S (1L<<4)

#define	DQ_PC104_IRQ6S (1L<<3)

#define	DQ_PC104_IRQ5S (1L<<2)

#define	DQ_PC104_IRQ4S (1L<<1)

#define	DQ_PC104_IRQ3S (1L<<0)

#define	DQ_PC104_ASSIGN_IRQA(N) ((N)&0x1ff)

#define	DQ_PC104_ASSIGN_IRQB(N) (((N)&0x1ff)<<16)

#define	DQ_PC104_DACK (1L<<13)

#define	DQ_PC104_SHBE (1L<<12)

#define	DQ_PC104_BALE (1L<<11)

#define	DQ_PC104_AEN (1L<<10)

#define	DQ_PC104_BCLK (1L<<9)

#define	DQ_PC104_OSC (1L<<8)

#define	DQ_PC104_TC (1L<<7)

#define	DQ_PC104_REFRESH (1L<<6)

#define	DQ_PC104_IOW (1L<<5)

#define	DQ_PC104_IOR (1L<<4)

#define	DQ_PC104_SMEMW (1L<<3)

#define	DQ_PC104_SMEMR (1L<<2)

#define	DQ_PC104_MEMW (1L<<1)

#define	DQ_PC104_MEMR (1L<<0)

#define	DQ_PC104_CDO_ENDIRQ (1L<<28)

#define	DQ_PC104_CDO_ACC16BIT (0L<<27)

#define	DQ_PC104_CDO_ACC8BIT (1L<<27)

#define	DQ_PC104_CDO_IMMDATA (1L<<26)

#define	DQ_PC104_CDO_DIR (1L<<25)

#define	DQ_PC104_CDO_READ (0L<<25)

#define	DQ_PC104_CDO_WRITE (1L<<25)

#define	DQ_PC104_CDO_IOSPCSEL (0L<<24)

#define	DQ_PC104_CDO_MEMSPCSEL (1L<<24)

#define	DQ_PC104_CDO_ADDRESS(N) ((N)&0xffffff)

#define	DQ_PC104_CDO_TRANSIZE(N) ((((N)-1)&0xfff)<<16)

#define	DQ_PC104_CDO_DNAADDRi(N) ((((N)-0x8000)>>2)&0x1fff)

#define	DQ_PC104_CDO_DNAADDR(N) ((N)&0xffff)

#define	DQ_PC104_CL_CLK (1L<<29)

#define	DQ_PC104_SPACESIZE_MASK (DQ_PC104_CDO_ACC8BIT\|DQ_PC104_CDO_MEMSPCSEL)

#define	DQ_PC104_SCRIPT_MASK (0xfffffff)

#define	DQ_PC104_SCRIPTDATA_MASK (0xffff0fff)

#define	DQ_PC104_CL_SW (0)

#define	DQ_PC104_CL_TIMER (1)

#define	DQ_PC104_CL_IRQA (2)

#define	DQ_PC104_CL_IRQB (3)

#define	DQ_PC104_CL_IRQEN (1L<<3)

#define	DQL_IOCTL104_SETCFG (0x8)

#define	DQL_IOCTL104_SETDCDC (0x9)

#define	DQL_IOCTL104_MEMIOWRRD (0xA)

#define	DQL_IOCTL104_START (0xB)

#define	DQL_IOCTL104_BLOCKWRRD (0xC)

#define	DQL_IOCTL104_MEMORYWRRD (0xD)

#define	DQL_IOCTL104_CUSTOMPROC (0xE)

#define	DQ_PC104_READBUS (1)

#define	DQ_PC104_WRITEBUS (2)

#define	DQ_PC104_READMEM (3)

#define	DQ_PC104_WRITEMEM (4)

#define	DQ_PC104_WRITESCRIPT (5)

#define	DQ_PC104_READSTATUS (6)

#define	DQ_PC104_CONFIGURE_BUS (7)

#define	DQ_PC104_CONFIGURE_INTCLK (8)

#define	DQ_PC104_SET_CUSTOM_PROC (1)

#define	DQ_PC104_SET_CUSTOM_PARAM (2)

#define	DQ_PC104_ISR_DEFAULT (0)

#define	DQ_PC104_ISR_SIMA_ICB (1)

#define	DQ_PC104_ISR_SIMA_RSB (2)

#define	DQ_PC104_ISR_SIMA_ASCBA (4)

#define	DQ_PC104_ISR_SIMA_ASCBB (5)

#define	DQ_PC104_ISR_SIMA_ASCBC (6)

#define	DQ_PC104_SIMA_FRAME (0x440)

#define	DQ_PC104_SIMA_MSLOT (0x442)

#define	DQ_PC104_SIMA_BCM (0x444)

#define	DQ_PC104_SIMA_DCNT (0x446)

#define	DQ_PC104_SIMA_ECNT (0x448)

#define	DQ_PC104_SIMA_ERRVLD (0x450)

#define	DQ_PC104_SIMA_ACK (0x7ffe)

#define	DQ_PC104_SIMA_MCTRL (0x900)

#define	DQ_PC104_SIMA_MCTRL_STAT (0x90E)

#define	DQ_PC104_SIMA_CLO_ENTRIES (32)

#define	SIMA_ADCT_OF (0)

#define	SIMA_CTRL_OF (2)

#define	SIMA_LENG_OF (4)

#define	SIMA_TBUS_OF (6)

#define	SIMA_OFFS_OF (8)

#define	SIMA_SEGM_OF (10)

#define	SIMA_TIME_OF (12)

#define	SIMA_STAT_OF (14)

#define	SIMA_OF_SIZE (0x10)

#define	DQ_PC104_CHNUM (0x1)

#define	DQ_PC104_CHTYPE (0xE)

#define	DQ_SIMA_RDBLK0 (0x8000)

#define	DQ_SIMA_RDBLK1 (0x9000)

#define	DQ_SIMA_WRBLK0 (0xA000)

#define	DQ_SIMA_WRBLK1 (0xB000)

#define	DQ_SIMA_RX_BUFSEL (0)

#define	DQ_SIMA_TX_BUFSEL (1)

#define	DQ_SIMA_WRRDBLK(N, W) ((((N)>0)?0x8000:0x9000)+(((W)>0)?0x2000:0))

#define	DQ_SIMA_WRRDBLKi(N, W) (((DQ_SIMA_WRRDBLK((N),(W))-0x8000)>>2)&0x1fff)

#define	DQ_SIMA_RDBLK0i (DQ_SIMA_RDBLK0>>2)

#define	DQ_SIMA_RDBLK1i (DQ_SIMA_RDBLK1>>2)

#define	DQ_SIMA_WRBLK0i (DQ_SIMA_WRBLK0>>2)

#define	DQ_SIMA_WRBLK1i (DQ_SIMA_WRBLK1>>2)

#define	DQ_PC104_BLKMEM0 (0xF000)

#define	DQ_PC104_BLKMEM1 (0xF800)

#define	DQ_PC104_BLKSCRATCH (0xFFC0)

#define	DQ_PC104_BLKMEM0i ((DQ_PC104_BLKMEM0-0x8000)>>2)

#define	DQ_PC104_BLKMEM1i ((DQ_PC104_BLKMEM1-0x8000)>>2)

#define	DQ_PC104_BLKSCRATCHi ((DQ_PC104_BLKSCRATCH-0x8000)>>2)

#define	DQ_PC104_VMAP_SIMA_CTRL (0x0)

#define	DQ_PC104_VMAP_SIMA_STS (0x0)

#define	DQ_PC104_VMAP_SIMA_SLOT(BRD, SLOT) ((((BRD)&1)<<15)\|(((SLOT)&0xFF)+0x10))

#define	DQ_PC104_VMAP_SIMA_R90E (0x40)

#define	DQ_PC104_VMAP_SIMA_GET_BRD(N) (((N)&0x8000)>>15)

#define	DQ_PC104_VMAP_SIMA_BUFF(CHAN) (((CHAN)&0xff) - 0x10)

#define	DQ_PC104_VMAP_SIMA_CARD(CHAN) ((CHAN)>>15)

#define	DQ_PC104_MAXWAIT_BUF (5)

#define	DQ_PC104_SIMA_FRMSZ_RD (1)

#define	DQ_PC104_SIMA_FRMSZ_WR (2)

#define	PC104_SIMA_ICB_BUFS (4)

#define	PC104_SIMA_ICB_BUFSZ (768)

#define	PC104_SIMA_RSB_BUFS (24)

#define	PC104_SIMA_RSB_BUFSZ (64)

#define	PC104_SIMA_BUFSIZE (16384)

#define	DNR_PWR (0x20)

#define	DNR_PWR_1G (0x40)

#define	DNA_PWR_1G (0x41)

#define	DNR_LB (0x42)

#define	DNR_QTB (0x43)

#define	DNA_LB (0x44)

#define	DNA_QTB (0x45)

#define	DQ_L2_CHAN (16)

#define	DQ_L2_CHAN_MESR (13)

#define	DQ_L2_CHAN_MAX (64)

#define	DQ_L2_INFOSZ (DQ_MAX_INFO_SIZE)

#define	DQ_L2_BASE (BUS_FREQUENCY)

#define	DQ_L2_MAXCLFRQ (10)

#define	DQ_L2_MAXCVFRQ (10)

#define	DQ_L2_DNRP_OL_CH (0x10)

#define	DQ_L2_DNRP_UL_CH (0x20)

#define	DQ_L2_DNRP_LED_CH (0x30)

#define	DQ_L2_DNRP_FAN_CH (0x31)

#define	DQ_L2_DNRP_LED_MNGD (0x32)

#define	DQ_L2_DNRP_FAN_MNGD (0x33)

#define	DQ_L2_SET_CONFIG (1)

#define	DQ_L2_SET_LED (2)

#define	DQ_L2_SET_LIMITS (4)

#define	DQ_L4_SET_CONFIG (DQ_L2_SET_CONFIG)

#define	DQ_L4_SET_LED (DQ_L2_SET_LED)

#define	DQ_L4_SET_LIMITS (DQ_L2_SET_LIMITS)

#define	DQ_L2_ADC_TEMP2 (12)

#define	DQ_L2_ADC_TEMP1 (11)

#define	DQ_L2_ADC_I_IN (10)

#define	DQ_L2_ADC_V_FAN (9)

#define	DQ_L2_ADC_V_1_2 (8)

#define	DQ_L2_ADC_V_1_5 (7)

#define	DQ_L2_ADC_V_IN (6)

#define	DQ_L2_ADC_V_24NIC (5)

#define	DQ_L2_ADC_V_24DNR (4)

#define	DQ_L2_ADC_V_3_3NIC (3)

#define	DQ_L2_ADC_V_3_3DNR (2)

#define	DQ_L2_ADC_V_2_5NIC (1)

#define	DQ_L2_ADC_V_2_5DNR (0)

#define	DQ_L4_ADC_TEMP2 (15)

#define	DQ_L4_ADC_I_1_5 (14)

#define	DQ_L4_ADC_TEMP1 (13)

#define	DQ_L4_ADC_I_3_3 (12)

#define	DQ_L4_ADC_GND_3 (11)

#define	DQ_L4_ADC_I_IN (10)

#define	DQ_L4_ADC_V_FAN (9)

#define	DQ_L4_ADC_V_1_2 (8)

#define	DQ_L4_ADC_V_1_5 (7)

#define	DQ_L4_ADC_V_IN (6)

#define	DQ_L4_ADC_GND_2 (5)

#define	DQ_L4_ADC_V_24DNR (4)

#define	DQ_L4_ADC_V_CAP (3)

#define	DQ_L4_ADC_V_3_3DNR (2)

#define	DQ_L4_ADC_GND (1)

#define	DQ_L4_ADC_V_2_5DNR (0)

#define	DQ_LT2448_GETVAL(V) (((V>>5)&0xffffff)^0x800000)

#define	DQ_LDIAG_ADC_TEMP2 (15)

#define	DQ_LDIAG_ADC_GND_8 (14)

#define	DQ_LDIAG_ADC_TEMP1 (13)

#define	DQ_LDIAG_ADC_GND_7 (12)

#define	DQ_LDIAG_ADC_GND_6 (11)

#define	DQ_LDIAG_ADC_GND_5 (10)

#define	DQ_LDIAG_ADC_GND_4 (9)

#define	DQ_LDIAG_ADC_V_1_2 (8)

#define	DQ_LDIAG_ADC_V_1_5 (7)

#define	DQ_LDIAG_ADC_V_IN (6)

#define	DQ_LDIAG_ADC_GND_3 (5)

#define	DQ_LDIAG_ADC_V_24 (4)

#define	DQ_LDIAG_ADC_GND_2 (3)

#define	DQ_LDIAG_ADC_V_3_3 (2)

#define	DQ_LDIAG_ADC_GND (1)

#define	DQ_LDIAG_ADC_V_2_5 (0)

#define	DQ_LDIAG_CVT_TEMP2(N) ((N-0x800000)/644)

#define	DQ_LDIAG_CVT_TEMP1(N) ((N-0x800000)/644)

#define	DQ_LDIAG_CVT_V_1_2(N) (((N-0x800000)0.000000149)11)

#define	DQ_LDIAG_CVT_V_1_5(N) (((N-0x800000)0.000000149)11)

#define	DQ_LDIAG_CVT_V_IN(N) (((N-0x800000)0.000000149)23.1)

#define	DQ_LDIAG_CVT_V_24(N) (((N-0x800000)0.000000149)11)

#define	DQ_LDIAG_CVT_V_3_3(N) (((N-0x800000)0.000000149)11)

#define	DQ_LDIAG_CVT_GND(N) ((N-0x800000)*0.000000149)

#define	DQ_LDIAG_CVT_V_2_5(N) (((N-0x800000)0.000000149)11)

#define	DQ_L2_CVT_TEMP2(N) (((N-0x800000)0.000000149)339)

#define	DQ_L2_CVT_TEMP1(N) (((N-0x800000)0.000000149)339)

#define	DQ_L2_CVT_I_IN(N) (((N-0x800000)0.000000149)12)

#define	DQ_L2_CVT_V_FAN(N) (((N-0x800000)0.000000149)23.1)

#define	DQ_L2_CVT_V_1_2(N) (((N-0x800000)0.000000149)23.1)

#define	DQ_L2_CVT_V_1_5(N) (((N-0x800000)0.000000149)23.1)

#define	DQ_L2_CVT_V_IN(N) (((N-0x800000)0.000000149)45.3)

#define	DQ_L2_CVT_V_24NIC(N) (((N-0x800000)0.000000149)23.1)

#define	DQ_L2_CVT_V_24DNR(N) (((N-0x800000)0.000000149)23.1)

#define	DQ_L2_CVT_V_3_3NIC(N) (((N-0x800000)0.000000149)23.1)

#define	DQ_L2_CVT_V_3_3DNR(N) (((N-0x800000)0.000000149)23.1)

#define	DQ_L2_CVT_V_2_5NIC(N) (((N-0x800000)0.000000149)23.1)

#define	DQ_L2_CVT_V_2_5DNR(N) (((N-0x800000)0.000000149)23.1)

#define	LM6p (0.943)

#define	LP6p (1.06)

#define	LM10p (0.909)

#define	LP10p (1.1)

#define	DQ_L2_LIM_TEMP2(N) ((N>(273-40))&&(N<(273+90)))

#define	DQ_L2_LIM_TEMP1(N) ((N>(273-40))&&(N<(273+90)))

#define	DQ_L2_LIM_I_IN(N) ((N>0.1)&&(N<3.0))

#define	DQ_L2_BLIM_I_IN(N) ((N>0.01)&&(N<5.0))

#define	DQ_L2_LIM_V_FAN(N) (N>0)

#define	DQ_L2_LIM_V_1_2(N) ((N>(1.271LM6p))&&(N<(1.271LP6p)))

#define	DQ_L2_LIM_V_1_5(N) ((N>(1.576LM6p))&&(N<(1.576LP6p)))

#define	DQ_L2_LIM_V_IN(N) ((N>11)&&(N<30))

#define	DQ_L2_LIM_V_24NIC(N) ((N>22.5)&&(N<26.0))

#define	DQ_L2_LIM_V_24DNR(N) ((N>22.5)&&(N<26.0))

#define	DQ_L2_LIM_V_3_3NIC(N) ((N>(3.3LM6p))&&(N<(3.3LP6p)))

#define	DQ_L2_LIM_V_3_3DNR(N) ((N>(3.3LM6p))&&(N<(3.3LP6p)))

#define	DQ_L2_LIM_V_2_5NIC(N) ((N>(2.5LM6p))&&(N<(2.5LP6p)))

#define	DQ_L2_LIM_V_2_5DNR(N) ((N>(2.5LM6p))&&(N<(2.5LP6p)))

#define	DQ_L2_BLIM_V_1_2(N) ((N>(1.271LM10p))&&(N<(1.271LP10p)))

#define	DQ_L2_BLIM_V_1_5(N) ((N>(1.576LM10p))&&(N<(1.576LP10p)))

#define	DQ_L2_BLIM_V_IN(N) ((N>9)&&(N<36))

#define	DQ_L2_BLIM_V_24NIC(N) ((N>21.6)&&(N<27.0))

#define	DQ_L2_BLIM_V_24DNR(N) ((N>21.6)&&(N<27.0))

#define	DQ_L2_BLIM_V_3_3NIC(N) ((N>(3.3LP10p))&&(N<(3.3LP10p)))

#define	DQ_L2_BLIM_V_3_3DNR(N) ((N>(3.3LP10p))&&(N<(3.3LP10p)))

#define	DQ_L2_BLIM_V_2_5NIC(N) ((N>(2.5LM10p))&&(N<(2.5LP10p)))

#define	DQ_L2_BLIM_V_2_5DNR(N) ((N>(2.5LM10p))&&(N<(2.5LP10p)))

#define	DQ_L2_SAFE_TEMP_HI (273+40)

#define	DQ_L2_SAFE_TEMP_LO (273+35)

#define	DQ_L4_CVT_TEMP2(N) ((N-0x800000)/644)

#define	DQ_L4_CVT_I_IN_1_5(N) (((N-0x800000)*0.00000745))

#define	DQ_L4_CVT_TEMP1(N) ((N-0x800000)/644)

#define	DQ_L4_CVT_I_IN_3_3(N) (((N-0x800000)*0.00000745))

#define	DQ_L4_CVT_V_GND3(N) (((N-0x800000)*0.000000149))

#define	DQ_L4_CVT_I_IN(N) (((N-0x800000)*0.00000178))

#define	DQ_L4_CVT_V_FAN(N) (((N-0x800000)0.000000149)23.1)

#define	DQ_L4_CVT_V_1_2(N) (((N-0x800000)0.000000149)23.1)

#define	DQ_L4_CVT_V_1_5(N) (((N-0x800000)0.000000149)23.1)

#define	DQ_L4_CVT_V_IN(N) (((N-0x800000)0.000000149)47.5)

#define	DQ_L4_CVT_V_GND2(N) (((N-0x800000)*0.000000149))

#define	DQ_L4_CVT_V_24DNR(N) (((N-0x800000)0.000000149)23.1)

#define	DQ_L4_CVT_V_U_CAP(N) (((N-0x800000)0.000000149)23.1)

#define	DQ_L4_CVT_V_3_3DNR(N) (((N-0x800000)0.000000149)23.1)

#define	DQ_L4_CVT_V_GND(N) (((N-0x800000)*0.000000149))

#define	DQ_L4_CVT_V_2_5DNR(N) (((N-0x800000)0.000000149)23.1)

#define	DQ_L4_LIM_TEMP2(N) ((N>(273-40))&&(N<(273+90)))

#define	DQ_L4_LIM_TEMP1(N) ((N>(273-40))&&(N<(273+90)))

#define	DQ_L4_LIM_I_IN(N) ((N>0.1)&&(N<4.0))

#define	DQ_L4_LIM_I_IN_3_3(N) ((N>0.1)&&(N<3.0))

#define	DQ_L4_LIM_I_IN_1_5(N) ((N>0.1)&&(N<3.0))

#define	DQ_L4_BLIM_I_IN(N) ((N>0.01)&&(N<5.0))

#define	DQ_L4_BLIM_I_IN_3_3(N) ((N>0.1)&&(N<3.0))

#define	DQ_L4_BLIM_I_IN_1_5(N) ((N>0.1)&&(N<3.0))

#define	DQ_L4_LIM_V_FAN(N) (N)

#define	DQ_L4_LIM_V_1_2R(N) ((N>(1.271LM6p))&&(N<(1.271LP6p)))

#define	DQ_L4_LIM_V_1_2A(N) ((N>(1.21LM6p))&&(N<(1.21LP6p)))

#define	DQ_L4_LIM_V_1_5(N) ((N>(1.576LM6p))&&(N<(1.576LP6p)))

#define	DQ_L4_LIM_V_IN(N) ((N>11)&&(N<30))

#define	DQ_L4_LIM_V_24NIC(N) ((N>22.5)&&(N<26.0))

#define	DQ_L4_LIM_V_24DNR(N) ((N>22.5)&&(N<26.0))

#define	DQ_L4_LIM_V_3_3NIC(N) ((N>(3.3LM6p))&&(N<(3.3LP6p)))

#define	DQ_L4_LIM_V_3_3DNR(N) ((N>(3.3LM6p))&&(N<(3.3LP6p)))

#define	DQ_L4_LIM_V_2_5NIC(N) ((N>(2.5LM6p))&&(N<(2.5LP6p)))

#define	DQ_L4_LIM_V_2_5DNR(N) ((N>(2.5LM6p))&&(N<(2.5LP6p)))

#define	DQ_L4_BLIM_V_1_2R(N) ((N>(1.271LM10p))&&(N<(1.271LP10p)))

#define	DQ_L4_BLIM_V_1_2A(N) ((N>(1.21LM10p))&&(N<(1.21LP10p)))

#define	DQ_L4_BLIM_V_1_5(N) ((N>(1.576LM10p))&&(N<(1.576LP10p)))

#define	DQ_L4_BLIM_V_IN(N) ((N>9)&&(N<36))

#define	DQ_L4_BLIM_V_24NIC(N) ((N>21.6)&&(N<27.0))

#define	DQ_L4_BLIM_V_24DNR(N) ((N>21.6)&&(N<27.0))

#define	DQ_L4_BLIM_V_3_3NIC(N) ((N>(3.3LP10p))&&(N<(3.3LP10p)))

#define	DQ_L4_BLIM_V_3_3DNR(N) ((N>(3.3LP10p))&&(N<(3.3LP10p)))

#define	DQ_L4_BLIM_V_2_5NIC(N) ((N>(2.5LM10p))&&(N<(2.5LP10p)))

#define	DQ_L4_BLIM_V_2_5DNR(N) ((N>(2.5LM10p))&&(N<(2.5LP10p)))

#define	DQ_L4_SAFE_TEMP_HI (273+40)

#define	DQ_L4_SAFE_TEMP_LO (273+35)

#define	DQ_L2_PLIM(V, N, T) ((V>(N-NT))&&(V<(N+NT)))

#define	DQ_L2_LED_VIN (1L<<0)

#define	DQ_L2_LED_IIN (1L<<1)

#define	DQ_L2_LED_1_5 (1L<<2)

#define	DQ_L2_LED_FAN (1L<<3)

#define	DQ_L2_LED_USR (1L<<4)

#define	DQ_L2_LED_IO (1L<<5)

#define	DQ_L2_LED_OVRT (1L<<6)

#define	DQ_L2_LED_ATT (1L<<7)

#define	DQ_L2_LED_24_DNR (1L<<8)

#define	DQ_L2_LED_24_NIC (1L<<9)

#define	DQ_L2_LED_3_3_DNR (1L<<10)

#define	DQ_L2_LED_3_3_NIC (1L<<11)

#define	DQ_L2_LED_STOP_UPDATE (1L<<31)

#define	DQ_L2_LED_USR_ (DQ_L2_LED_USR\|DQ_L2_LED_IO\|DQ_L2_LED_ATT)

#define	DQ_L2_LED_MASK (DQ_L2_LED_USR_\|(DQ_L2_LED_USR_<<16))

#define	DQ_L2_LED_BLINK(N) ((N<<16)\|N)

#define	DQ_L2_OVERHEAT_IGNORE (10)

#define	DQ_L4_LED_OVRT (1L<<0)

#define	DQ_L4_LED_ATT (1L<<1)

#define	DQ_L4_LED_RW (1L<<2)

#define	DQ_L4_LED_USR (1L<<3)

#define	DQ_L4_LED_IO (1L<<4)

#define	DQ_L4_LED_3_3_DNR (1L<<5)

#define	DQ_L4_LED_PG (1L<<6)

#define	DQ_L4_LED_24_DNR (1L<<7)

#define	DQ_L4_LED_USR_ (DQ_L4_LED_USR\|DQ_L4_LED_IO\|DQ_L4_LED_ATT)

#define	DQ_L4_LED_MASK (DQ_L4_LED_USR_\|(DQ_L4_LED_USR_<<16))

#define	DQ_L4_LED_BLINK(N) ((N<<16)\|N)

#define	DQ_L2_DNRP_CHECK_us (100*1000)

#define	DQ_L2_CFG_UONLY (1L<<31)

#define	DQ_L2_CFG_24BIT (1L<<30)

#define	DQ_L2_CFG_ADCFE (1L<<29)

#define	DQ_L2_CFG_ADCDIV (1L<<20)

#define	DQ_L2_STS_FAN1STS (1L<<19)

#define	DQ_L2_STS_FAN0STS (1L<<18)

#define	DQ_L2_STS_DC24OFF (1L<<17)

#define	DQ_L2_STS_FANOFF (1L<<16)

#define	DQ_L2_CFG_MASK (DQ_L2_STS_DC24OFF\|DQ_L2_STS_FANOFF)

#define	DQ_L2_LED_BLINK0 (1L<<16)

#define	DQ_L2_LED_LEDON0 (1L<<0)

#define	DQ_L2_EST_ESTS0 (1L<<16)

#define	DQ_L2_EST_CURSTS0 (1L<<0)

#define	DQL_IOCTL2000_GETPASS (10L)

#define	DQL_IOCTL2000_SETPASS (11L)

#define	DQ_L2_NAMELEN (20)

#define	DQ_L2_NO_IP (1)

#define	DQ_L2_PROGRAM_IP (2)

#define	DQ_AI201_CHAN (24)

#define	DQ_AI201_CHANSVC (32)

#define	DQ_AI201_INFOSZ (DQ_MAX_INFO_SIZE)

#define	DQ_AI201_BASE (BUS_FREQUENCY)

#define	DQ_AI201_GAINS (4)

#define	DQ_AI201_SPAN (30.0)

#define	DQ_AI201_OFFSET (15.0)

#define	DQ_AI201_STEP (DQ_AI201_SPAN/0xFFFF)

#define	DQ_AI201_STEP_10 (DQ_AI201_STEP/10)

#define	DQ_AI201_STEP_100 (DQ_AI201_STEP/100)

#define	DQ_AI201_STEP_1000 (DQ_AI201_STEP/1000)

#define	DQ_AI201_STEP_2 (DQ_AI201_STEP/2)

#define	DQ_AI201_STEP_5 (DQ_AI201_STEP/5)

#define	DQ_AI201_OFFSET_10 (DQ_AI201_OFFSET/10)

#define	DQ_AI201_OFFSET_100 (DQ_AI201_OFFSET/100)

#define	DQ_AI201_OFFSET_1000 (DQ_AI201_OFFSET/1000)

#define	DQ_AI201_OFFSET_2 (DQ_AI201_OFFSET/2)

#define	DQ_AI201_OFFSET_5 (DQ_AI201_OFFSET/5)

#define	DQ_AI201_GAIN_1 (0)

#define	DQ_AI201_GAIN_10 (1)

#define	DQ_AI201_GAIN_100 (2)

#define	DQ_AI201_GAIN_1000 (3)

#define	DQ_AI201_GAIN_1_100 (0)

#define	DQ_AI201_GAIN_2_100 (1)

#define	DQ_AI201_GAIN_5_100 (2)

#define	DQ_AI201_GAIN_10_100 (3)

#define	DQ_AI201_GAINV_0 (1)

#define	DQ_AI201_GAINV_1 (10)

#define	DQ_AI201_GAINV_2 (100)

#define	DQ_AI201_GAINV_3 (1000)

#define	DQ_AI201_MAXCLFRQ (120000)

#define	DQ_AI201_MAXCVFRQ (120000)

#define	DQ_AI201_CALDACS (4)

#define	DQ_AI201_VREFS (2)

#define	DQ_LT1608_GETVALS(V) ((V&0xffff)^0x8000)

#define	DQ_LT1608_GETVAL(V) (V)

#define	DQ_AI201_CL_TIMES (2)

#define	DQ_AI201_FIFO_CH (128)

#define	DQ_AI201_MODESCAN (DQ_FIFO_MODESCAN)

#define	DQ_AI201_MODEFIFO (DQ_FIFO_MODEFIFO)

#define	DQ_AI201_MODECONT (DQ_FIFO_MODECONT)

#define	DQ_AI201_FIFO_GET_DATA (DQ_FIFO_GET_DATA)

#define	DQ_AI201_NAMELEN (20)

#define	DQ_ONESTEP201 (45776UL)

#define	DQ_OFFSETD201 (1500000000UL)

#define	DQ_ONESTEP201_10 (30518UL)

#define	DQ_OFFSETD201_10 (1000000000UL)

#define	DQ_AI205_CHAN (4)

#define	DQ_AI205_CHANSVC (4)

#define	DQ_AI205_INFOSZ (DQ_MAX_INFO_SIZE)

#define	DQ_AI205_BASE (BUS_FREQUENCY)

#define	DQ_AI205_FIRNUM (3)

#define	DQ_AI205_DEFDECR (5)

#define	DQ_AI205_MAXDECR (32)

#define	DQ_AI205_MAXTAPS (128)

#define	DQ_AI205_COEFF_WIDTH (16)

#define	DQ_AI205_FIR_TOTAL (1<<(DQ_AI205_COEFF_WIDTH-1))

#define	DQ_AI205_SPAN (200.0)

#define	DQ_AI205_OFFSET (100.0)

#define	DQ_AI205_STEP (DQ_AI205_SPAN/0x3FFFF)

#define	DQ_AI205_STEP16 (DQ_AI205_SPAN/0xFFFF)

#define	DQ_AI205_STEP_10 (DQ_AI205_STEP/10)

#define	DQ_AI205_STEP_100 (DQ_AI205_STEP/100)

#define	DQ_AI205_STEP_1000 (DQ_AI205_STEP/1000)

#define	DQ_AI205_OFFSET_10 (DQ_AI205_OFFSET/10)

#define	DQ_AI205_OFFSET_100 (DQ_AI205_OFFSET/100)

#define	DQ_AI205_OFFSET_1000 (DQ_AI205_OFFSET/1000)

#define	DQ_AI205_SPAN_801 (8.192)

#define	DQ_AI205_OFFSET_801 (4.096)

#define	DQ_AI205_STEP_801 (DQ_AI205_SPAN_801/0x3FFFF)

#define	DQ_AI205_STEP16_801 (DQ_AI205_SPAN_801/0xFFFF)

#define	DQ_AI205_STEP_10_801 (DQ_AI205_STEP_801/10)

#define	DQ_AI205_STEP_100_801 (DQ_AI205_STEP_801/100)

#define	DQ_AI205_STEP_1000_801 (DQ_AI205_STEP_801/1000)

#define	DQ_AI205_OFFSET_10_801 (DQ_AI205_OFFSET_801/10)

#define	DQ_AI205_OFFSET_100_801 (DQ_AI205_OFFSET_801/100)

#define	DQ_AI205_OFFSET_1000_801 (DQ_AI205_OFFSET_801/1000)

#define	DQ_AI205_CALDACS (8)

#define	AI205_STARTRATE (DQ_AI205_BASE/100-1)

#define	AI205_SHOW_SUM (0x80)

#define	DQ_AI205_CL_TIMES (2)

#define	DQ_AI205_FIFO_CH (128)

#define	DQ_AI205_FIFO_BUFSZ (256)

#define	DQ_AD7776_GETVALS(V) (V&0x3ffff)

#define	DQ_AD7776_GETVAL(V) (V)

#define	DQ_AD7776_GETVAL16(V) (V&0x3ffff >> 2)

#define	DQ_AD7776_GETCH(V) ((V>>28)&3)

#define	DQ_AI205_GAIN_1 (0)

#define	DQ_AI205_GAIN_10 (1)

#define	DQ_AI205_GAIN_100 (2)

#define	DQ_AI205_GAIN_1000 (3)

#define	DQ_AI205_GAINV_0 (1)

#define	DQ_AI205_GAINV_1 (10)

#define	DQ_AI205_GAINV_2 (100)

#define	DQ_AI205_GAINV_3 (1000)

#define	DQ_AI205_MODESCAN (DQ_FIFO_MODESCAN)

#define	DQ_AI205_MODEFIFO (DQ_FIFO_MODEFIFO)

#define	DQ_AI205_MODECONT (DQ_FIFO_MODECONT)

#define	DQ_AI205_TSCOPY (1L << 18)

#define	DQ_AI205_FIFO_COEF (DQ_FIFO_PUT_COEFF)

#define	DQ_AI205_FIFO_DATA (DQ_FIFO_SET_DATA)

#define	DQ_AI205_FIFO_MODE (DQ_FIFO_PUT_CUSTOM)

#define	DQ_AI205_FIFO_GET_DATA (DQ_FIFO_GET_DATA)

#define	DQ_AI205_CFILTMINENT (3)

#define	DQ_AI205_CFILT00 (0x00)

#define	DQ_AI205_CFILT01 (0x01)

#define	DQ_AI205_CFILT02 (0x02)

#define	DQ_AI205_CFILT10 (0x10)

#define	DQ_AI205_CFILT11 (0x11)

#define	DQ_AI205_CFILT12 (0x12)

#define	DQ_AI205_CFILT20 (0x20)

#define	DQ_AI205_CFILT21 (0x21)

#define	DQ_AI205_CFILT22 (0x22)

#define	DQ_AI205_CFILT30 (0x30)

#define	DQ_AI205_CFILT31 (0x31)

#define	DQ_AI205_CFILT32 (0x32)

#define	DQ_AI205_CFILT_GETCHAN(D) ((D & 0xf0)>>4)

#define	DQ_AI205_CFILT_GETFILT(D) (D & 0xf)

#define	DQ_AI205_CFILT_CHANFILT(C, F) (((C&0x3)<<4)\|(F&0x3))

#define	DQ_AI205_DATAFIFO (1)

#define	AI205_FIR_DISABLED (0)

#define	AI205_FIR_DEFAULT (1)

#define	AI205_FIR_DECRAT_ONLY (2)

#define	AI205_FIR_PROGRAMMED (6)

#define	AI205_DEFTAPS (128)

#define	AI205_DEFDCR (0)

#define	DQ_AI205_NAMELEN (32)

#define	DQ_ONESTEP205 (7629UL)

#define	DQ_OFFSETD205 (1000000000UL)

#define	DQ_AI208_CHAN (8)

#define	DQ_AI208_INFOSZ (DQ_MAX_INFO_SIZE)

#define	DQ_AI208_BASE (BUS_FREQUENCY)

#define	DQ_AI208_GAINS (12)

#define	DQ_AI208_RS (4990)

#define	DQ_AI208_SHUNT_NOMINAL (200000)

#define	DQ_AI208_SHUNT_STEPS (256)

#define	DQ_AI208_MAXCLFRQ (20000)

#define	DQ_AI208_MAXCVFRQ (20000)

#define	DQ_AI208_CALDACS (4)

#define	DQ_AI208_VREFS (2)

#define	DQ_AI208_MAX_CH_LIST (32)

#define	DQ_AI208_SPAN (20.0)

#define	DQ_AI208_OFFSET (10.0)

#define	DQ_AI208_STEP (DQ_AI208_SPAN/0xFFFF)

#define	DQ_AI208_STEP18 (DQ_AI208_SPAN/0x3FFFF)

#define	DQ_AI208_GAINV (1)

#define	DQ_AI208_GAINV_2 (DQ_AI208_GAINV*2)

#define	DQ_AI208_GAINV_4 (DQ_AI208_GAINV*4)

#define	DQ_AI208_GAINV_8 (DQ_AI208_GAINV*8)

#define	DQ_AI208_GAINV_10 (DQ_AI208_GAINV*10)

#define	DQ_AI208_GAINV_20 (DQ_AI208_GAINV*20)

#define	DQ_AI208_GAINV_40 (DQ_AI208_GAINV*40)

#define	DQ_AI208_GAINV_80 (DQ_AI208_GAINV*80)

#define	DQ_AI208_GAINV_100 (DQ_AI208_GAINV*100)

#define	DQ_AI208_GAINV_200 (DQ_AI208_GAINV*200)

#define	DQ_AI208_GAINV_400 (DQ_AI208_GAINV*400)

#define	DQ_AI208_GAINV_800 (DQ_AI208_GAINV*800)

#define	DQ_AI208_STEP_2 (DQ_AI208_STEP/2)

#define	DQ_AI208_STEP_4 (DQ_AI208_STEP/4)

#define	DQ_AI208_STEP_8 (DQ_AI208_STEP/8)

#define	DQ_AI208_STEP_10 (DQ_AI208_STEP/10)

#define	DQ_AI208_STEP_20 (DQ_AI208_STEP/20)

#define	DQ_AI208_STEP_40 (DQ_AI208_STEP/40)

#define	DQ_AI208_STEP_80 (DQ_AI208_STEP/80)

#define	DQ_AI208_STEP_100 (DQ_AI208_STEP/100)

#define	DQ_AI208_STEP_200 (DQ_AI208_STEP/200)

#define	DQ_AI208_STEP_400 (DQ_AI208_STEP/400)

#define	DQ_AI208_STEP_800 (DQ_AI208_STEP/800)

#define	DQ_AI208_STEP18_2 (DQ_AI208_STEP18/2)

#define	DQ_AI208_STEP18_4 (DQ_AI208_STEP18/4)

#define	DQ_AI208_STEP18_8 (DQ_AI208_STEP18/8)

#define	DQ_AI208_STEP18_10 (DQ_AI208_STEP18/10)

#define	DQ_AI208_STEP18_20 (DQ_AI208_STEP18/20)

#define	DQ_AI208_STEP18_40 (DQ_AI208_STEP18/40)

#define	DQ_AI208_STEP18_80 (DQ_AI208_STEP18/80)

#define	DQ_AI208_STEP18_100 (DQ_AI208_STEP18/100)

#define	DQ_AI208_STEP18_200 (DQ_AI208_STEP18/200)

#define	DQ_AI208_STEP18_400 (DQ_AI208_STEP18/400)

#define	DQ_AI208_STEP18_800 (DQ_AI208_STEP18/800)

#define	DQ_AI208_OFFSET_2 (DQ_AI208_OFFSET/2)

#define	DQ_AI208_OFFSET_4 (DQ_AI208_OFFSET/4)

#define	DQ_AI208_OFFSET_8 (DQ_AI208_OFFSET/8)

#define	DQ_AI208_OFFSET_10 (DQ_AI208_OFFSET/10)

#define	DQ_AI208_OFFSET_20 (DQ_AI208_OFFSET/20)

#define	DQ_AI208_OFFSET_40 (DQ_AI208_OFFSET/40)

#define	DQ_AI208_OFFSET_80 (DQ_AI208_OFFSET/80)

#define	DQ_AI208_OFFSET_100 (DQ_AI208_OFFSET/100)

#define	DQ_AI208_OFFSET_200 (DQ_AI208_OFFSET/200)

#define	DQ_AI208_OFFSET_400 (DQ_AI208_OFFSET/400)

#define	DQ_AI208_OFFSET_800 (DQ_AI208_OFFSET/800)

#define	DQ_AI208_GAIN_1 (0)

#define	DQ_AI208_GAIN_2 (1)

#define	DQ_AI208_GAIN_4 (2)

#define	DQ_AI208_GAIN_8 (3)

#define	DQ_AI208_GAIN_10 (4)

#define	DQ_AI208_GAIN_20 (5)

#define	DQ_AI208_GAIN_40 (6)

#define	DQ_AI208_GAIN_80 (7)

#define	DQ_AI208_GAIN_100 (8)

#define	DQ_AI208_GAIN_200 (9)

#define	DQ_AI208_GAIN_400 (10)

#define	DQ_AI208_GAIN_800 (11)

#define	EXC_V2R(V) ((uint16)(V * (65535.0/10.0))&0xffff)

#define	AI208_MINEXCITE (1.5)

#define	AI208_MAXEXCITE (10.0)

#define	DQ_AI207_CHAN (16)

#define	DQ_AI207_CHAN_SE (32)

#define	DQL_FE207_AGND (32)

#define	DQL_FE207_CJC (33)

#define	DQL_FE207_REF (34)

#define	DQL_FE208_SPSM (0x0)

#define	DQL_FE208_PPG (0x10)

#define	DQL_FE208_PSPG (0x20)

#define	DQL_FE208_PSSM (0x30)

#define	DQL_FE208_SCUR (0x40)

#define	DQL_ISTR208_GEN7 (1L<<15)

#define	DQL_ISTR208_GEN6 (1L<<14)

#define	DQL_ISTR208_GEN5 (1L<<13)

#define	DQL_ISTR208_GEN4 (1L<<12)

#define	DQL_ISTR208_GEN3 (1L<<11)

#define	DQL_ISTR208_GEN2 (1L<<10)

#define	DQL_ISTR208_GEN1 (1L<<9)

#define	DQL_ISTR208_GEN0 (1L<<8)

#define	DQL_ISTR208_18BIT (1L<<5)

#define	DQL_ISTR208_PD (1L<<4)

#define	DQL_ISTR208_RESET (1L<<3)

#define	DQL_ISTR208_LED (1L<<2)

#define	DQL_ISTR208_ADCEN (1L<<1)

#define	DQL_ISTR208_RSV0 (1L<<0)

#define	DQ_AI208_ALL_EXCITED (1L<<19)

#define	DQ_AI208_MODESCAN (DQ_FIFO_MODESCAN)

#define	DQ_AI208_MODEFIFO (DQ_FIFO_MODEFIFO)

#define	DQ_AI208_MODECONT (DQ_FIFO_MODECONT)

#define	DQ_AI208_FIFO_GET_DATA (DQ_FIFO_GET_DATA)

#define	DQL_IOCTL208_SET_SSPERCHAN (1)

#define	DQL_IOCTL208_SET_EXC_A (2)

#define	DQL_IOCTL208_SET_EXC_B (3)

#define	DQL_IOCTL208_SET_EXC_CH (4)

#define	DQL_IOCTL208_SET_Ra (5)

#define	DQL_IOCTL208_SET_Rb (6)

#define	DQL_IOCTL208_READ_SS (10)

#define	DQL_IOCTL208_READ_PP (11)

#define	DQL_IOCTL208_READ_PS (12)

#define	DQL_IOCTL208_READ_AGND (13)

#define	DQL_IOCTL208_READ_REF (14)

#define	DQL_IOCTL208_READ_Rs (15)

#define	DQL_IOCTL208_READ_Rx (16)

#define	DQL_IOCTL208_READ_Ra (17)

#define	DQL_IOCTL208_READ_Rb (18)

#define	DQL_IOCTL208_READ_5k (19)

#define	DQL_IOCTL208_READ_PSM (20)

#define	DQL_IOCTL208_READ_5kB (21)

#define	DQ_AI208_NAMELEN (20)

#define	DQ_AI207_NAMELEN (14)

#define	DQ_AI211_CHAN (4)

#define	DQ_AI211_INFOSZ DQ_MAX_INFO_SIZE

#define	DQ_AI211_BASE BUS_FREQUENCY

#define	DQ_AI211_BASE_24MHZ (24000000)

#define	DQ_AI211_DEFDECR (0)

#define	DQ_AI211_DEFTAPS (254)

#define	DQ_AI211_MAXDECR (65536)

#define	DQ_AI211_MAXTAPS (256)

#define	DQ_AI211_COEFF_WIDTH (20)

#define	DQ_AI211_FIR_TOTAL (1<<(DQ_AI211_COEFF_WIDTH-1))

#define	DQ_AI211_ADC_CLOCK_FACTOR (8)

#define	DQ_AI211_SPAN_V (50.0)

#define	DQ_AI211_SPAN_H (0xFFFFFF)

#define	DQ_AI211_STEP (DQ_AI211_SPAN_V/DQ_AI211_SPAN_H)

#define	DQ_AI211_HEX_TO_V(HEX) (HEX*DQ_AI211_STEP-DQ_AI211_SPAN_V/2)

#define	DQ_AI211_GETCH(V) ((V>>28)&3)

#define	DQ_AI211_CALDACS (8)

#define	AI211_SEL_CHAN_0 (0x01)

#define	AI211_SEL_CHAN_1 (0x02)

#define	AI211_SEL_CHAN_2 (0x04)

#define	AI211_SEL_CHAN_3 (0x08)

#define	AI211_SEL_CHAN_ALL (0x0f)

#define	DQ_AI211_MODESCAN (DQ_FIFO_MODESCAN)

#define	DQ_AI211_MODEFIFO (DQ_FIFO_MODEFIFO)

#define	DQ_AI211_MODECONT (DQ_FIFO_MODECONT)

#define	AI211_FIR_SET_DEFAULT (0x8)

#define	AI211_FIR_COEFF_LOAD (0x4)

#define	AI211_FIR_SET_DECIMATION_RATE (0x2)

#define	AI211_FIR_ENABLE (0x1)

#define	AI211_FIR_DISABLE (0x0)

#define	AI211_FIRFIRST_DISABLE (0x10)

#define	AI211_FIRFIRST_ENABLE (0)

#define	DQAI211_CFGCH_DEFAULTSET (1L<<11)

#define	DQAI211_BIASDRIVESET (1L<<0)

#define	DQAI211_BIASONOFFSET (1L<<1)

#define	DQAI211_COMPHISET (1L<<2)

#define	DQAI211_COMPLOSET (1L<<3)

#define	DQAI211_ALARMCTRLSET (1L<<4)

#define	DQAI211_HPFSET (1L<<5)

#define	DQAI211_OFFSETSET (1L<<6)

#define	DQAI211_ANAFILTSET (1L<<7)

#define	DQAI211_MAINENBSET (1L<<8)

#define	DQAI211_SECENBSSET (1L<<9)

#define	DQAI211_SECNSET (1L<<10)

#define	DQ211_DRIVE_CURRENT(I) (((I)/8.0)*255)

#define	DQ_211_BIAS_ON (1)

#define	DQ_211_BIAS_OFF (0)

#define	DQ_211_MAX_BIAS (0xff)

#define	DQ_211_COMP_HI_STD (0xfa0)

#define	DQ_211_COMP_HI_DEFAULT (0xfff)

#define	DQ_211_COMP_LO_STD (0x0c0)

#define	DQ_211_COMP_LO_DEFAULT (0x0)

#define	DQ_211_ALARM_ON (0x3)

#define	DQ_211_ALARM_OFF (0)

#define	DQ_211_ALARM_RED (0x4)

#define	DQ_211_ALARM_GREEN (0x8)

#define	DQ_211_ALARM_ORANGE (0x0c)

#define	DQ_211_HPF_DC (1L<<0)

#define	DQ_211_HPF_POINT1_HZ (1L<<1)

#define	DQ_211_HPF_1_HZ (1L<<2)

#define	DQ_211_HPF_10_HZ (1L<<3)

#define	DQ_211_OFFSET_TEST_ON (1)

#define	DQ_211_OFFSET_TEST_OFF (0)

#define	DQ_211_ANALOG_FILTER_ON (1)

#define	DQ_211_ANALOG_FILTER_OFF (0)

#define	DQ_211_MAIN_FLOW_OFF (0)

#define	DQ_211_MAIN_FLOW_ON (1)

#define	DQ_211_SEC_ENB_OFF (0)

#define	DQ_211_SEC_ENB_LED (0x1)

#define	DQ_211_SEC_N_STD (100)

#define	DQ_211_SEC_N_OFF (0)

#define	DQAI211_CFGLAYER_DEFAULTSET (1L<<0)

#define	DQAI211_CLKSRCSET (1L<<1)

#define	DQAI211_CLKDIVSET (1L<<2)

#define	DQAI211_FMTRSET (1L<<3)

#define	DQAI211_AVGFACTORSET (1L<<4)

#define	DQAI211_DECFACTORSET (1L<<8)

#define	DQAI211_FIR_BY_DECFACTOR (1L<<5)

#define	DQAI211_DC_DC_ON (1L<<6)

#define	DQAI211_DC_DC_OFF (1L<<7)

#define	DQ_211_CLK_66MHZ (0)

#define	DQ_211_CLK_24MHZ (0x10)

#define	DQ_211_CLK_SYNC2 (0x18)

#define	DQ_211_CLK_SYNC0_BUS (0x8)

#define	DQ_211_CLK_SYNC1_BUS (0x9)

#define	DQ_211_CLK_SYNC2_BUS (0xa)

#define	DQ_211_CLK_SYNC3_BUS (0xb)

#define	DQ_211_CLK_DIV_MAX (0x3ff)

#define	DQ_211_FMTR_NORMAL (0)

#define	DQ_211_FMTR_REDUCED (1)

#define	DQ_AI211_SPAN (50.0)

#define	DQ_AI211_OFFSET (25.0)

#define	DQ_AI211_STEP16 (DQ_AI211_SPAN/0xFFFF)

#define	DQ_AI211_STEP_2 (DQ_AI211_STEP/2)

#define	DQ_AI211_STEP_5 (DQ_AI211_STEP/5)

#define	DQ_AI211_STEP_10 (DQ_AI211_STEP/10)

#define	DQ_AI211_OFFSET_2 (DQ_AI211_OFFSET/2)

#define	DQ_AI211_OFFSET_5 (DQ_AI211_OFFSET/5)

#define	DQ_AI211_OFFSET_10 (DQ_AI211_OFFSET/10)

#define	DQIOCTL_SET211CHANNEL (0x08)

#define	DQIOCTL_SET211LAYER (0x09)

#define	DQIOCTL_GET211_CFGAMG (0x10)

#define	DQ_AI211_MAXAVG (15)

#define	DQ_AI211_MAXDEC (16)

#define	AI211_MAXCVFRQ (125000)

#define	AI211_MINCVFRQ_AVG (AI211_MAXCVFRQ/2)

#define	AI211_CLID_FMTR0_CHN0 (3UL<<28)

#define	AI211_CLID_FMTR0_INFOO (1UL<<27)

#define	AI211_CLID_FMTR0_INFOU (1UL<<26)

#define	AI211_CLID_FMTR0_SMSB0 (3UL<<24)

#define	AI211_CLID_FMTR0_ADCD0 (1UL<<0)

#define	AI211_CFGAMG_DEFAULT_STATE (0x020A)

#define	AI211_CFGAMG_FMTR (1UL<<16)

#define	AI211_CFGAMG_L1COMP (1UL<<15)

#define	AI211_CFGAMG_L1STATE (1UL<<14)

#define	AI211_CFGAMG_L0COMP (1UL<<13)

#define	AI211_CFGAMG_L0STATE (1UL<<12)

#define	AI211_CFGAMG_GAIN(G) ((G&3UL)<<10)

#define	AI211_CFGAMG_GAIN_MASK (3UL<<10)

#define	AI211_CFGAMG_BW_10HZ (1UL<<9)

#define	AI211_CFGAMG_BW_1HZ (1UL<<8)

#define	AI211_CFGAMG_BW_0_1HZ (1UL<<7)

#define	AI211_CFGAMG_BW_DC (1UL<<6)

#define	AI211_CFGAMG_OFFSET (1UL<<5)

#define	AI211_CFGAMG_FLOFF (1UL<<4)

#define	AI211_CFGAMG_IDIS (1UL<<3)

#define	AI211_CFGAMG_S_ADCEN (1UL<<2)

#define	AI211_CFGAMG_M_ADCENFEN (1UL<<1)

#define	DQ_AI211_GAINS (4)

#define	DQ_AI211_GAIN_1 (0)

#define	DQ_AI211_GAIN_2 (1)

#define	DQ_AI211_GAIN_5 (2)

#define	DQ_AI211_GAIN_10 (3)

#define	DQ_AI211_CAL_SETS (8)

#define	DQ_AI211_SETS (4)

#define	DQ_AI211_SETS1 (4)

#define	DQ_AI211_CAL_SETS1 (4)

#define	DQ_AI211_CAL_SET_0 (0)

#define	DQ_AI211_CAL_SET_1 (1)

#define	DQ_AI211_CAL_SET_2 (2)

#define	DQ_AI211_CAL_SET_3 (3)

#define	DQ_AI211_CAL_SET_4 (4)

#define	DQ_AI211_CAL_SET_5 (5)

#define	DQ_AI211_CAL_SET_6 (6)

#define	DQ_AI211_CAL_SET_7 (7)

#define	DQ_AI211_NAMELEN (32)

#define	DQ_AI217_CHAN (16)

#define	DQ_AI217_CJC_CHAN (1)

#define	DQ_AI217_CJC_OFFSET (16)

#define	DQ_AI217_CJC_AVG (0x20)

#define	DQ_AI217_FIR_BANKS (4)

#define	DQ_AI217_INFOSZ (DQ_MAX_INFO_SIZE)

#define	DQ_AI217_BASE (BUS_FREQUENCY)

#define	DQ_AI217_MODESCAN (DQ_FIFO_MODESCAN)

#define	DQ_AI217_MODEFIFO (DQ_FIFO_MODEFIFO)

#define	DQ_AI217_MODECONT (DQ_FIFO_MODECONT)

#define	DQ_AI217_DEFTAPS (128)

#define	DQ_AI217_MAXDECR (65536)

#define	DQ_AI217_MAXTAPS (128)

#define	DQ_AI217_COEFF_WIDTH (24)

#define	DQ_AI217_FIR_TOTAL (1<<(DQ_AI217_COEFF_WIDTH-1))

#define	DQ_AI217_ADC_CLOCK_FACTOR (8.0)

#define	DQ_AI217_SPAN_V (20.0)

#define	DQ_AI217_SPAN_H (0xFFFFFF)

#define	DQ_AI217_STEP (DQ_AI217_SPAN_V/DQ_AI217_SPAN_H)

#define	DQ_AI217_HEX_TO_V(HEX) (HEX*DQ_AI217_STEP-DQ_AI217_SPAN_V/2)

#define	DQ_AI217_SEL_QFIR_A (0x01)

#define	DQ_AI217_SEL_QFIR_B (0x02)

#define	DQ_AI217_SEL_QFIR_C (0x04)

#define	DQ_AI217_SEL_QFIR_D (0x08)

#define	DQ_AI217_SEL_QFIR_ALL (0x0f)

#define	DQ_AI217_FIR_SET_INDEX (0x80)

#define	DQ_AI217_FIR_SET_DEFAULT (0x8)

#define	DQ_AI217_FIR_COEFF_LOAD (0x4)

#define	DQ_AI217_FIR_SET_DECIMATION_RATE (0x2)

#define	DQ_AI217_FIR_ENABLE (0x1)

#define	DQ_AI217_FIR_DISABLE (0x0)

#define	DQ_AI217_SPAN (20.0)

#define	DQ_AI217_OFFSET (10.0)

#define	DQ_AI217_STEP_2 (DQ_AI217_STEP/2.0)

#define	DQ_AI217_STEP_4 (DQ_AI217_STEP/4.0)

#define	DQ_AI217_STEP_4_CJC (DQ_AI217_STEP/4.0)

#define	DQ_AI217_STEP_8 (DQ_AI217_STEP/8.0)

#define	DQ_AI217_STEP_16 (DQ_AI217_STEP/16.0)

#define	DQ_AI217_STEP_32 (DQ_AI217_STEP/32.0)

#define	DQ_AI217_STEP_64 (DQ_AI217_STEP/64.0)

#define	DQ_AI217_OFFSET_2 (DQ_AI217_OFFSET/2.0)

#define	DQ_AI217_OFFSET_4 (DQ_AI217_OFFSET/4.0)

#define	DQ_AI217_OFFSET_4_CJC (0.0)

#define	DQ_AI217_OFFSET_8 (DQ_AI217_OFFSET/8.0)

#define	DQ_AI217_OFFSET_16 (DQ_AI217_OFFSET/16.0)

#define	DQ_AI217_OFFSET_32 (DQ_AI217_OFFSET/32.0)

#define	DQ_AI217_OFFSET_64 (DQ_AI217_OFFSET/64.0)

#define	DQ_AI217_MAXPLLCLFRQ (120000.0)

#define	DQ_AI217_SNAP_FREQ (7500.0)

#define	DQ_AI217_MINPLLCLFRQ (100.0)

#define	DQ_AI217_MAXCLFRQ (29891.30 * 4.0)

#define	DQ_AI217_MAXCLOCL (DQ_AI217_MAXCLFRQ4DQ_AI217_ADC_CLOCK_FACTOR)

#define	DQ_AI217_MINCLOCL (DQ_AI217_MAXCLOCL/2)

#define	DQ_AI217_STARTRATE (DQ_AI217_BASE/1000-1)

#define	DQ_AI217_MAX_AVG (0x14)

#define	DQ_AI217_SET_CJC_AVG (0x100)

#define	AI217_DEFAULT_GAIN_CAL (0x0b8ba00)

#define	AI217_DEFAULT_OFFS_CAL (0)

#define	AI217_DEFAULT_CJC_GAIN_CAL (0x0800000)

#define	AI217_DEFAULT_CJC_OFFS_CAL (0)

#define	DQ_AI217_GAINS (8)

#define	DQ_AI217_GAINS_NORM (7)

#define	DQ_AI217_GAIN_1 (0)

#define	DQ_AI217_GAIN_2 (1)

#define	DQ_AI217_GAIN_4 (2)

#define	DQ_AI217_GAIN_8 (3)

#define	DQ_AI217_GAIN_16 (4)

#define	DQ_AI217_GAIN_32 (5)

#define	DQ_AI217_GAIN_64 (6)

#define	DQ_AI217_GAIN_4_CJC (7)

#define	DQ_AI217_PGAERR_CHKERR (1UL<<7)

#define	DQ_AI217_PGAERR_IARERR (1UL<<6)

#define	DQ_AI217_PGAERR_BUFA (1UL<<5)

#define	DQ_AI217_PGAERR_ICAERR (1UL<<4)

#define	DQ_AI217_PGAERR_ERRFLAG (1UL<<3)

#define	DQ_AI217_PGAERR_OUTERR (1UL<<2)

#define	DQ_AI217_PGAERR_GAINERR (1UL<<1)

#define	DQ_AI217_PGAERR_IOVERR (1UL<<0)

#define	DQ_AI217_GET_PARAM_PGA (0)

#define	DQ_UNUSED (0)

#define	DQ_AI217_NAMELEN (32)

#define	DQ_AI224_CHAN (4)

#define	DQ_AI224_DACS (4)

#define	DQ_AI224_DAC_CAL_MULTIPLIER (53687)

#define	DQ_AI224_DAC_CAL_SHIFT (14)

#define	DQ_AI224_INFOSZ DQ_MAX_INFO_SIZE

#define	DQ_AI224_BASE BUS_FREQUENCY

#define	DQ_AI224_BASE_28MHZ (28160000)

#define	DQ_AI224_GAINS (DQ_AI224_GAIN_400+1)

#define	DQ_AI224_MAXCLFRQ (600000)

#define	DQ_AI224_MAXCVFRQ (600000)

#define	DQ_AI224_PT_PT_ADC_RATE (512000.0)

#define	DQ_AI224_CALDACS (0)

#define	DQ_AI224_VREFS (0)

#define	DQ_AI224_RS (4990)

#define	DQ_AI224_SHUNT_NOMINAL (200000)

#define	DQ_AI224_SHUNT_STEPS (256)

#define	DQ_AI224_SHUNT_FREQ (100000)

#define	DQ_AI224_FIR_STAGES (2)

#define	DQ_AI224_CUST_FIR0 (0)

#define	DQ_AI224_CUST_FIR1 (1)

#define	DQ_AI224_DEF_FIR0 (0xe)

#define	DQ_AI224_DEF_FIR1 (0xf)

#define	DQ_AI224_MAXDECR (0x7ff)

#define	DQ_AI224_MAXTAPS0 (0x60)

#define	DQ_AI224_MAXTAPS1 (0x1a0)

#define	DQ_AI224_TAPMASK0 (0x7f)

#define	DQ_AI224_TAPMASK1 (0x1FF)

#define	DQ_AI224_COEFF_WIDTH (16)

#define	DQ_AI224_FIR_TOTAL (1<<(DQ_AI224_COEFF_WIDTH-1))

#define	DQ_AI224_MAX_CH_LIST (DQ_AI224_CHAN*2)

#define	DQ_AI224_SPAN (20.0)

#define	DQ_AI224_OFFSET (10.0)

#define	DQ_AI224_STEP (DQ_AI224_SPAN/0xFFFF)

#define	DQ_AI224_STEP18 (DQ_AI224_SPAN/0x3FFFF)

#define	DQ_AI224_GAIN_1 (0)

#define	DQ_AI224_GAIN_2 (1)

#define	DQ_AI224_GAIN_4 (2)

#define	DQ_AI224_GAIN_8 (3)

#define	DQ_AI224_GAIN_20 (4)

#define	DQ_AI224_GAIN_40 (5)

#define	DQ_AI224_GAIN_80 (6)

#define	DQ_AI224_GAIN_100 (7)

#define	DQ_AI224_GAIN_200 (8)

#define	DQ_AI224_GAIN_400 (9)

#define	DQ_AI224_GAINV_0 (1)

#define	DQ_AI224_GAINV_1 (2)

#define	DQ_AI224_GAINV_2 (4)

#define	DQ_AI224_GAINV_3 (8)

#define	DQ_AI224_GAINV_4 (20)

#define	DQ_AI224_GAINV_5 (40)

#define	DQ_AI224_GAINV_6 (80)

#define	DQ_AI224_GAINV_7 (100)

#define	DQ_AI224_GAINV_8 (200)

#define	DQ_AI224_GAINV_9 (400)

#define	DQ_AI224_STEP18_2 (DQ_AI224_STEP18/2)

#define	DQ_AI224_STEP18_4 (DQ_AI224_STEP18/4)

#define	DQ_AI224_STEP18_8 (DQ_AI224_STEP18/8)

#define	DQ_AI224_STEP18_20 (DQ_AI224_STEP18/20)

#define	DQ_AI224_STEP18_40 (DQ_AI224_STEP18/40)

#define	DQ_AI224_STEP18_80 (DQ_AI224_STEP18/80)

#define	DQ_AI224_STEP18_100 (DQ_AI224_STEP18/100)

#define	DQ_AI224_STEP18_200 (DQ_AI224_STEP18/200)

#define	DQ_AI224_STEP18_400 (DQ_AI224_STEP18/400)

#define	DQ_AI224_OFFSET_2 (DQ_AI224_OFFSET/2)

#define	DQ_AI224_OFFSET_4 (DQ_AI224_OFFSET/4)

#define	DQ_AI224_OFFSET_8 (DQ_AI224_OFFSET/8)

#define	DQ_AI224_OFFSET_20 (DQ_AI224_OFFSET/20)

#define	DQ_AI224_OFFSET_40 (DQ_AI224_OFFSET/40)

#define	DQ_AI224_OFFSET_80 (DQ_AI224_OFFSET/80)

#define	DQ_AI224_OFFSET_100 (DQ_AI224_OFFSET/100)

#define	DQ_AI224_OFFSET_200 (DQ_AI224_OFFSET/200)

#define	DQ_AI224_OFFSET_400 (DQ_AI224_OFFSET/400)

#define	DQ_AI224_ANULL_FACTOR(G)

#define	DQ_AI224_MUX_SS (0x00)

#define	DQ_AI224_MUX_CS (0x10)

#define	DQ_AI224_MUX_EXCP (0x20)

#define	DQ_AI224_MUX_PPS (0x30)

#define	DQ_AI224_MUX_NULL (0x40)

#define	DQ_AI224_MUX_PS (0x50)

#define	DQ_AI224_MUX_EXCN (0x60)

#define	DQ_AI224_MUX_5K (0x70)

#define	DQ_AI224_SET_CHAN(M, N) (((M))\|((N)&0x7))

#define	DQ_AI224_AVG_FLAG (0x4)

#define	DQL_IOCTL224_SETCFG (0x8)

#define	DQL_IOCTL224_SETEXC (0x9)

#define	DQL_IOCTL224_SETSHUNT (0xA)

#define	DQL_IOCTL224_MEASSHUNT (0xB)

#define	DQL_IOCTL224_SETAVG (0xC)

#define	DQ_AI224_SHUNT_DISABLED (0)

#define	DQ_AI224_SHUNT_A (2)

#define	DQ_AI224_SHUNT_B (3)

#define	DQ_AI224_SET_DC_EXC (1)

#define	DQ_AI224_SET_AC_EXC (2)

#define	DQ_AI224_SET_BCOMP (3)

#define	DQ_AI224_SET_NULL (4)

#define	DQ_AI224_FIR_DISABLE (0x0)

#define	DQ_AI224_FIR_ENABLE (0x1)

#define	DQ_AI224_FIR_SET_DECRATE (0x2)

#define	DQ_AI224_FIR_COEFF_LOAD (0x4)

#define	DQ_AI224_FIR_SET_DEFAULT (0x8)

#define	DQ_AI224_V_SHUNT_A (0x1)

#define	DQ_AI224_V_SHUNT_B (0x2)

#define	DQ_AI224_V_R5K (0x3)

#define	DQ_AI224_SEL_CHAN_0 (0x01)

#define	DQ_AI224_SEL_CHAN_1 (0x02)

#define	DQ_AI224_SEL_CHAN_2 (0x04)

#define	DQ_AI224_SEL_CHAN_3 (0x08)

#define	DQ_AI224_SEL_CHAN_ALL (0x0f)

#define	DQ_AI224_MAXAVG (0x14)

#define	DQ_AI224_MIN_SAMPLE_RATE (586.0)

#define	DQ_AI224_MODESCAN (DQ_FIFO_MODESCAN)

#define	DQ_AI224_MODEFIFO (DQ_FIFO_MODEFIFO)

#define	DQ_AI224_MODECONT (DQ_FIFO_MODECONT)

#define	DQ_AI224_MAX_PTS_PERIOD (256)

#define	DQ_AI224_ZERO_LEVEL (0x8000)

#define	DQ_AI224_EXC_RMS_DEFAULT (0x1f0000)

#define	DQ_AI224_MAX_DIV (99)

#define	DQ_AI224_MAX_DIV2 (199)

#define	DQ_AI224_MAX_DIV3 (329)

#define	DQ_AI224_MAX_FRQ (600000)

#define	DQ_AI224_FIFO_GET_DATA (DQ_FIFO_GET_DATA)

#define	DQ_AI224_ENABLE_EXC_A (1L<<0)

#define	DQ_AI224_ENABLE_EXC_B (1L<<1)

#define	DQ_AO224_PHASE_SET(PHASE, DELAY) (((PHASE)<<18)\|((DELAY)&0x3ffff))

#define	DQ_AI224_CALCHAN (8)

#define	DQ_AI224_NAMELEN (20)

#define	DQ_AI224_WFAVG (16)

#define	DQ_AI225_CHAN (26)

#define	DQ_AI225_INFOSZ DQ_MAX_INFO_SIZE

#define	DQ_AI225_BASE BUS_FREQUENCY

#define	DQ_AI225_CALLEVEL 1024000000

#define	DQ_AI225_MAXCHAN 128

#define	DQ_AI225_MAXRATE 3200

#define	DQ_AI225_CLPERINT 16

#define	DQ_AI225_FIFO_GET_DATA DQ_FIFO_GET_DATA

#define	DQ_AI225_FIFO_GET_CAL DQ_FIFO_GET_CAL

#define	DQ_AI225_CLENTRIES_DEF 1

#define	DQ_AI225_TS_CHAN (26)

#define	DQ_AI225_CHAN_(SM) (((SM)&(1L<<DQ_AI225_TS_CHAN))?(DQ_AI225_CHAN+1):(DQ_AI225_CHAN))

#define	DQ_AI225RANGE 2.5

#define	DQ_AI225BINRANGE 0xffffff

#define	DQ_AI225HALFRANGE 1.25

#define	DQ_AI225ONEVOLTNV 1000000000

#define	DQ_AI225_GAIN_1 0

#define	DQ_AI225_SPAN (2.5)

#define	DQ_AI225_OFFSET (1.25)

#define	DQ_AI225_STEP (DQ_AI225_SPAN/(double)0xffffff)

#define	DQ_ACCESS_DIO_CFG_DIO1_IN (2)

#define	DQ_ACCESS_DIO_CFG_DIO1_OUT (1)

#define	DQ_ACCESS_DIO_CFG_READ_DI_ONLY (0)

#define	DQ_ACCESS_DIO2_OUT (1L<<0)

#define	DQ_ACCESS_DIO1_OUT (1L<<1)

#define	DQ_ACCESS_DIO_STATUS_DIO2_OUT (1L<<0)

#define	DQ_ACCESS_DIO_STATUS_DIO1_OUT (1L<<1)

#define	DQ_ACCESS_DIO_STATUS_DIO0_IN (1L<<2)

#define	DQ_ACCESS_DIO_STATUS_DIO1_IN (1L<<3)

#define	DQ_AI225_CLSETSPD(S) ((S&0xf)<<12)

#define	DQ_AI225_CLGETSPD(L) ((L&0xf000)>>12)

#define	DQ_AI225_CLSPDMASK (0xf000)

#define	DQ_LT2440_6_9S 6875

#define	DQ_LT2440_13_7S 13750

#define	DQ_LT2440_27_5S 27500

#define	DQ_LT2440_55S 55000

#define	DQ_LT2440_110S 110000

#define	DQ_LT2440_220S 220000

#define	DQ_LT2440_440S 440000

#define	DQ_LT2440_880S 880000

#define	DQ_LT2440_1760S 1760000

#define	DQ_LT2440_3520S 3520000

#define	DQ_LT2440_SPDS(N) (3000000 >> (N-1))

#define	DQIOCTL_DIO_SIGROUTING (0x0a)

#define	DQIOCTL_DIO_READ_DI_ONLY (0x0b)

#define	DQ_LT2440_GETVAL(V) (((V>>5)&0xffffff)^0x800000)

#define	DQ_LT2440_ISOVRRANGE(V) (((V&(1L<<28))&&(V&(1L<<29)))?1:0)

#define	DQ_LT2440_ISUNDRANGE(V) ((V&((1L<<28)\|(1L<<29)))?0:1)

#define	DQ_LT2440_FF01(V) (V&3)

#define	DQ_LT2440_XTRABITS(V) ((V>>2)&7)

#define	DQ_AI225_CL_TIMES 2

#define	DQ_AI225_FIFO_CH 128

#define	DQ_AI225_FIFO_BUFSZ 16

#define	DQ_AI225_MODESCAN (DQ_FIFO_MODESCAN)

#define	DQ_AI225_MODEFIFO (DQ_FIFO_MODEFIFO)

#define	DQ_AI225_MODECONT (DQ_FIFO_MODECONT)

#define	DQ_AI225_NAMELEN (16)

#define	DQ_AI254_CHAN 4

#define	DQ_AI254_DACS 4

#define	DQ_AI254_ADCS 2

#define	DQ_AI254_INFOSZ DQ_MAX_INFO_SIZE

#define	DQ_AI254_BASE BUS_FREQUENCY

#define	DQ_AI254_GAINS 4

#define	DQ_AI254_CLOCK33 33000000

#define	DQ_AI254_CLOCK24 24000000

#define	DQ_AI254_MINCLFRQ 400

#define	DQ_AI254_MAXCLFRQ 20000

#define	DQ_AI254_MAXCVFRQ4 320000

#define	DQ_AI254_MAXCVFRQ2 640000

#define	DQ_AI254_CALDACS 0

#define	DQ_AI254_VREFS 0

#define	DQ_AI254_MAX_CH_LIST 32

#define	DQ_AI254_SPAN (80.0)

#define	DQ_AI254_OFFSET (40.0)

#define	DQ_AI254_STEP (DQ_AI254_SPAN/0xFFFF)

#define	DQ_AI254_STEP16 (DQ_AI254_SPAN/0xFFFF)

#define	DQ_AI254_SUM2RMS (1.114303027)

#define	DQ_AI254_AMP2RMS (1.414213562)

#define	DQ_AI254_MIN_FRQ_SMOKE_TEST 350.0

#define	DQ_AI254_MAX_FRQ_SMOKE_TEST 22000.0

#define	DQ_AI254_EXC_SPAN (20.0)

#define	DQ_AI254_EXC_OFFSET (10.0)

#define	DQ_AI254_EXC_STEP (DQ_AI254_EXC_SPAN/0xFFFF)

#define	DQ_AI254_GAINV 1

#define	DQ_AI254_GAINV_2 (DQ_AI254_GAINV*2)

#define	DQ_AI254_GAINV_5 (DQ_AI254_GAINV*5)

#define	DQ_AI254_GAINV_10 (DQ_AI254_GAINV*10)

#define	DQ_AI254_STEP_2 (DQ_AI254_STEP/2)

#define	DQ_AI254_STEP_5 (DQ_AI254_STEP/5)

#define	DQ_AI254_STEP_10 (DQ_AI254_STEP/10)

#define	DQ_AI254_GAIN_1 0

#define	DQ_AI254_GAIN_2 1

#define	DQ_AI254_GAIN_4 2

#define	DQ_AI254_GAIN_8 3

#define	DQ_AI254_GAIN_5 2

#define	DQ_AI254_GAIN_10 3

#define	DQ_AI254_DIV_CAL (0x00)

#define	DQ_AI254_DIV_RAW (0x10)

#define	DQ_AI254_AVG (0x20)

#define	DQ_AI254_ZC (0x30)

#define	DQ_AI254_LAST_A (0x40)

#define	DQ_AI254_MAX_A (0x48)

#define	DQ_AI254_LAST_B (0x50)

#define	DQ_AI254_MAX_B (0x58)

#define	DQ_AI254_LAST_Sa (0x60)

#define	DQ_AI254_MIN_A (0x68)

#define	DQ_AI254_LAST_Sb (0x70)

#define	DQ_AI254_MIN_B (0x78)

#define	DQ_AI254_STATUS (0x18)

#define	DQ_AI254_CHTYPE (0xf8)

#define	DQ_AI254_CHNUM (0x3)

#define	DQ_AI254_GAIN_A (0x00)

#define	DQ_AI254_GAIN_B (0x10)

#define	DQ_AI254_PHASE_A (0x20)

#define	DQ_AI254_PHASE_B (0x30)

#define	DQ_AI254_PHASE_AUTO (0x40)

#define	DQ_AI254_FFIFO (0x50)

#define	DQ_AI254_AOUT0_WR (0x60)

#define	DQ_AI254_AOUT1_WR (0x70)

#define	DQ_AI254_AOUT2_WR (0x80)

#define	DQ_AI254_AOUT3_WR (0x90)

#define	DQL_IOCTL254_SETCFG (0x8)

#define	DQL_IOCTL254_SETEXC (0x9)

#define	DQL_IOCTL254_GETEXC (0xA)

#define	DQL_IOCTL254_START (0xB)

#define	DQL_IOCTL254_SETWF (0xC)

#define	DQL_IOCTL254_DIO (0xD)

#define	DQL_IOCTL254_GETWF (0xE)

#define	DQL_IOCTL254_SETEXT (0xF)

#define	DQ_AI254_MODE_INT_5 0

#define	DQ_AI254_MODE_INT_4 1

#define	DQ_AI254_MODE_EXT_5 2

#define	DQ_AI254_MODE_EXT_4 3

#define	DQ_AI254_MODE_SIM_5 4

#define	DQ_AI254_MODE_SIM_4 5

#define	DQ_AI254_MODE_SETAVG (1L<<0)

#define	DQ_AI254_MODE_SETMMAVG (1L<<1)

#define	DQ_AI254_MODE_SETZEROC (1L<<2)

#define	DQ_AI254_MODE_USEREFB (1L<<16)

#define	DQ_AI254_MODE_USE_SXAVG (1L<<30)

#define	DQ_AI254_MODESCAN (DQ_FIFO_MODESCAN)

#define	DQ_AI254_MODEFIFO (DQ_FIFO_MODEFIFO)

#define	DQ_AI254_MODECONT (DQ_FIFO_MODECONT)

#define	DQ_AI254_MAX_PTS_PERIOD 256

#define	DQ_AI254_ZERO_LEVEL 0x8000

#define	DQ_AI254_EXC_RMS_DEFAULT 0x1f0000

#define	DQ_AI254_MAX_DIV 99

#define	DQ_AI254_MAX_DIV2 199

#define	DQ_AI254_MAX_DIV3 329

#define	DQ_AI254_MAX_FRQ 330000

#define	DQ_AI254_FIFO_GET_DATA DQ_FIFO_GET_DATA

#define	DQ_AI254_ENABLE_EXC_A (1L<<0)

#define	DQ_AI254_ENABLE_EXC_B (1L<<1)

#define	DQ_AO254_PHASE_SET(PHASE, DELAY) (((PHASE)<<18)\|((DELAY)&0x3ffff))

#define	DQ_AI254_USROFFS_1 0x0

#define	DQ_AI254_USRGAIN_1 0x800000

#define	DQ_AI254_CALCHAN 8

#define	DQ_AI254_NAMELEN 20

#define	DQ_AI254_WFAVG 16

#define	DQ_AI255_CHAN 2

#define	DQ_AI255_DACS 4

#define	DQ_AI255_ADCS 4

#define	DQ_AI255_CHANNEL_A 0

#define	DQ_AI255_CHANNEL_B 1

#define	DQ_AI255_CHANNEL_C 2

#define	DQ_AI255_CHANNEL_D 3

#define	DQ_AI255_INFOSZ DQ_MAX_INFO_SIZE

#define	DQ_AI255_BASE BUS_FREQUENCY

#define	DQ_AI255_GAINS 4

#define	DQ_AI255_CLOCK33 33000000

#define	DQ_AI255_CLOCK24 24000000

#define	DQ_AI255_MAXCLFRQ 20000

#define	DQ_AI255_MAXCVFRQ 330000

#define	DQ_AI255_CALDACS 0

#define	DQ_AI255_VREFS 0

#define	DQ_AI255_MAX_CH_LIST 32

#define	DQ_AI255_SPAN (80.0)

#define	DQ_AI255_AMPL (40.0)

#define	DQ_AI255_OFFSET (40.0)

#define	DQ_AI255_STEP (DQ_AI255_SPAN/0xFFFF)

#define	DQ_AI255_STEP18 (DQ_AI255_SPAN/0x3FFFF)

#define	DQ_AI255_360 0x19228

#define	DQ_AI255_ACC_LIM (DQ_AI255_360>>1)

#define	DQ_AI255_GAINV 1

#define	DQ_AI255_GAINV_2 (DQ_AI255_GAINV*2)

#define	DQ_AI255_GAINV_5 (DQ_AI255_GAINV*5)

#define	DQ_AI255_GAINV_10 (DQ_AI255_GAINV*10)

#define	DQ_AI255_STEP_2 (DQ_AI255_STEP/2)

#define	DQ_AI255_STEP_5 (DQ_AI255_STEP/5)

#define	DQ_AI255_STEP_10 (DQ_AI255_STEP/10)

#define	DQ_AI255_GAIN_1 0

#define	DQ_AI255_GAIN_2 1

#define	DQ_AI255_GAIN_4 2

#define	DQ_AI255_GAIN_8 3

#define	DQ_AI255_GAIN_5 2

#define	DQ_AI255_GAIN_10 3

#define	DQ_AI255_ANGLE_CAL (0x00)

#define	DQ_AI255_ACCEL_CAL (0x10)

#define	DQ_AI255_STATUS (0x18)

#define	DQ_AI255_RAW_DATA (0x20)

#define	DQ_AI255_ZC (0x30)

#define	DQ_AI255_LAST_A (0x40)

#define	DQ_AI255_LAST_B (0x44)

#define	DQ_AI255_LAST_C (0x48)

#define	DQ_AI255_LAST_D (0x4C)

#define	DQ_AI255_LAST_SxA (0x50)

#define	DQ_AI255_LAST_SxB (0x54)

#define	DQ_AI255_LAST_SxC (0x58)

#define	DQ_AI255_LAST_SxD (0x5C)

#define	DQ_AI255_MIN_A (0x60)

#define	DQ_AI255_MIN_B (0x64)

#define	DQ_AI255_MIN_C (0x68)

#define	DQ_AI255_MIN_D (0x6C)

#define	DQ_AI255_MAX_A (0x70)

#define	DQ_AI255_MAX_B (0x74)

#define	DQ_AI255_MAX_C (0x78)

#define	DQ_AI255_MAX_D (0x7C)

#define	DQ_AI255_CHTYPE (0xfc)

#define	DQ_AI255_GAIN_A (0x00)

#define	DQ_AI255_GAIN_B (0x04)

#define	DQ_AI255_GAIN_C (0x08)

#define	DQ_AI255_GAIN_D (0x0C)

#define	DQ_AI255_PHASE_A (0x10)

#define	DQ_AI255_PHASE_B (0x14)

#define	DQ_AI255_PHASE_C (0x18)

#define	DQ_AI255_PHASE_D (0x1C)

#define	DQ_AI255_FFIFO (0x20)

#define	DQ_AI255_AOUT0_WR (0x30)

#define	DQ_AI255_AOUT1_WR (0x40)

#define	DQ_AI255_AOUT2_WR (0x50)

#define	DQ_AI255_AOUT3_WR (0x60)

#define	DQL_IOCTL255_SETCFG (0x8)

#define	DQL_IOCTL255_SETEXC (0x9)

#define	DQL_IOCTL255_GETEXC (0xA)

#define	DQL_IOCTL255_START (0xB)

#define	DQL_IOCTL255_SETWF (0xC)

#define	DQL_IOCTL255_DIO (0xD)

#define	DQL_IOCTL255_GETWF (0xE)

#define	DQL_IOCTL255_SETEXT (0xF)

#define	DQ_AI255_MODE_SI_INT 0

#define	DQ_AI255_MODE_RI_INT 1

#define	DQ_AI255_MODE_SI_EXT 2

#define	DQ_AI255_MODE_RI_EXT 3

#define	DQ_AI255_MODE_SS_INT 4

#define	DQ_AI255_MODE_RS_INT 5

#define	DQ_AI255_MODE_SS_EXT 6

#define	DQ_AI255_MODE_RS_EXT 7

#define	DQ_AI255_MODE_EN_AOUT 8

#define	DQ_AI255_MODE_EN_AIN 9

#define	DQ_AI255_MODE_DISABLE 0xf

#define	DQ_AI255_MODE_SETAVG (1L<<0)

#define	DQ_AI255_MODE_SETZEROC (1L<<1)

#define	DQ_AI255_MODESCAN (DQ_FIFO_MODESCAN)

#define	DQ_AI255_MODEFIFO (DQ_FIFO_MODEFIFO)

#define	DQ_AI255_MODECONT (DQ_FIFO_MODECONT)

#define	DQ_AI255_MAX_PTS_PERIOD 256

#define	DQ_AI255_ZERO_LEVEL 0x8000

#define	DQ_AI255_EXC_RMS_DEFAULT 0x1f0000

#define	DQ_AI255_MAX_DIV 99

#define	DQ_AI255_MAX_DIV2 199

#define	DQ_AI255_MAX_DIV3 329

#define	DQ_AI255_MAX_FRQ 330000

#define	DQ_AI255_FIFO_GET_DATA DQ_FIFO_GET_DATA

#define	DQ_AI255_ENABLE_EXC_A (1L<<0)

#define	DQ_AI255_ENABLE_EXC_B (1L<<1)

#define	DQ_AI255_ENABLE_EXC_C (1L<<2)

#define	DQ_AI255_ENABLE_EXC_D (1L<<3)

#define	DQ_AI255_FL_HWLOOP (1L<<1)

#define	DQ_AO255_PHASE_SET(PHASE, DELAY) (((PHASE)<<18)\|((DELAY)&0x3ffff))

#define	DQ_AI255_AOUT_FFCMD_WZ (8L<<28)

#define	DQ_AI255_AOUT_FFCMD_PHA (0L<<28)

#define	DQ_AI255_AOUT_FFCMD_PHB (1L<<28)

#define	DQ_AI255_AOUT_FFCMD_PHC (2L<<28)

#define	DQ_AI255_AOUT_FFCMD_PHD (3L<<28)

#define	DQ_AI255_AOUT_FFCMD_GA (4L<<28)

#define	DQ_AI255_AOUT_FFCMD_GB (5L<<28)

#define	DQ_AI255_AOUT_FFCMD_GC (6L<<28)

#define	DQ_AI255_AOUT_FFCMD_GD (7L<<28)

#define	DQ_AI255_COIL_X(D) (-(D)-30)

#define	DQ_AI255_COIL_Y(D) (-(D)-150)

#define	DQ_AI255_COIL_Z(D) (-(D)-270)

#define	DQ_AI255_COIL_X_r(D) (-(D)-30.0/360.0*6.283185307)

#define	DQ_AI255_COIL_Y_r(D) (-(D)-150.0/360.0*6.283185307)

#define	DQ_AI255_COIL_Z_r(D) (-(D)-270.0/360.0*6.283185307)

#define	AI255_CHANONLY_MASK 0x1

#define	AI255_GAIN_MASK 0x3

#define	DQ_AI255_CALCHAN 8

#define	DQ_AI255_NAMELEN 20

#define	DQ_AI255_WFAVG 16

#define	DQ_AO301_CHAN 8

#define	DQ_AO301_CHANSVC 32

#define	DQ_AO301_INFOSZ DQ_MAX_INFO_SIZE

#define	DQ_AO301_BASE BUS_FREQUENCY

#define	DQ_AO301_DMAPCV ((DQ_AO301_BASE/8000)-1)

#define	DQ_AO301_STARTRATE DQ_AO301_DMAPCV

#define	DQ_AO301_MAXCLFRQ 100000

#define	DQ_AO301_MAXCVFRQ 800000

#define	DQ_AO301_MIDSCALE 0x8000

#define	DQ_AO301_SPAN (20.0)

#define	DQ_AO301_OFFSET (10.0)

#define	DQ_AO301_STEP (DQ_AO301_SPAN/0xFFFF)

#define	DQ_AO308_352_SPAN (27.034)

#define	DQ_AO308_352_OFFSET (13.517)

#define	DQ_AO308_352_STEP (DQ_AO308_352_SPAN/0xFFFF)

#define	DQ_AO308_353_SPAN (80.0)

#define	DQ_AO308_353_OFFSET (40.0)

#define	DQ_AO308_353_STEP (DQ_AO308_353_SPAN/0xFFFF)

#define	DQ_AO332_CHAN (32)

#define	DQ_AO332_CHANMASK (DQ_AO332_CHAN-1)

#define	DQ_AO332_CHANSVC (32)

#define	DQ_AO332_INFOSZ (DQ_MAX_INFO_SIZE)

#define	DQ_AO332_BASE (BUS_FREQUENCY)

#define	DQ_AO332_DMAPCV ((DQ_AO332_BASE/8000)-1)

#define	DQ_AO332_STARTRATE (DQ_AO332_DMAPCV)

#define	DQ_AO332_MAXCLFRQ (100000)

#define	DQ_AO332_MAXCVFRQ (800000)

#define	DQ_AO332_MIDSCALE (0x8000)

#define	DQ_AO332_SPAN (20.0)

#define	DQ_AO332_OFFSET (10.0)

#define	DQ_AO332_STEP (DQ_AO332_SPAN/0xFFFF)

#define	DQ_AO333_ADC_SPAN (20.0)

#define	DQ_AO333_ADC_OFFSET (10.0)

#define	DQ_AO333_ADC_STEP24 (DQ_AO333_ADC_SPAN/(double)0xffffff)

#define	DQ_AO333_ADC_STEP (DQ_AO333_ADC_SPAN/(double)0xffff)

#define	DQIOCTL_AO333_CALIBRATE (0x08)

#define	DQIOCTL_AO333_CALIBRATE_RESULT (0x09)

#define	DQ_AO333_DEF_OFFSET_CAL (0x69)

#define	DQ_AO333_MAX_OFFSET_CAL_DEV (0x120)

#define	DQ_AO333_DEF_GAIN_CAL (0x7c60)

#define	DQ_AO333_MAX_GAIN_CAL_DEV (0x0600)

#define	DQ_AO333_DEF_GAIN_SF_CAL (0x0b)

#define	DQ_AO333_CAL_READINGS_AVGD (6)

#define	DQ_AO333_ADC_RESULT (0x2100)

#define	DQ_AO333_I2C_NEW_DATA (0x2018)

#define	DQ_AO333_I2C_CTRL (0x2000)

#define	DQ_AO333_I2C_CTRL_RDY_ALL (1L<<1)

#define	DQ_AO333_CAL_P9_5V (0xf999)

#define	DQ_AO333_CAL_N9_5V (0x0667)

#define	DQ_AO333_CAL_0V (DQ_AO332_MIDSCALE)

#define	DQ_AO333_MAX_N9_5V_DEV (0x2a)

#define	AO333_CAL_ADC_RA_HIGH (-99)

#define	AO333_CAL_ADC_RA_LOW (-98)

#define	AO333_CAL_ADC_RD_FAIL (-97)

#define	AO333_CAL_ADC_OFFSET_RANGE (-96)

#define	AO333_CAL_ADC_N9_5_LIMIT (-95)

#define	AO333_CAL_ADC_GAIN_RANGE (-94)

#define	AO333_CAL_ADC_EE_ERR (-93)

#define	AO333_CAL_ADC_SUCCESS (1)

#define	DQL_EXT_DEV_PREAMBLE (0xa3<<24)

#define	DQL_EXT_DEV_CMDMASK (0x7)

#define	DQL_EXT_DEV_CMDMASK_SHFT (21)

#define	DQL_EXT_DEV_DATAMASK (0xfffff)

#define	DQL_EXT_DEV_DATAMASK_SHFT (1)

#define	DQL_EXT_DEV_RETURN_PREABLE_MASK (0xe0000000)

#define	DQL_EXT_DEV_RETURN_PREABLE (0xa0000000)

#define	DQ_AI301_CL_TIMES 2

#define	DQ_AI301_FIFO_CH 128

#define	DQ_AI301_FIFO_BUFSZ 16

#define	DQ_AO301_POS10 (1L << 19)

#define	DQ_AO301_NEG10 (2L << 19)

#define	DQ_AO301_BI10 (3L << 19)

#define	DQ_AO301_OFF (0L << 19)

#define	DQ_AO301_ENCOUT (1L << 18)

#define	DQ_AO301_MODESCAN (DQ_FIFO_MODESCAN)

#define	DQ_AO301_MODEFIFO (DQ_FIFO_MODEFIFO)

#define	DQ_AO301_MODECONT (DQ_FIFO_MODECONT)

#define	DQ_AO301_MODEWFGEN (3L << 16)

#define	DQ_AO301_FIFO_SET_DATA DQ_FIFO_SET_DATA

#define	DQL_ISTR301_DIO0INV (1L<<7)

#define	DQL_ISTR301_DIO0MODE (5)

#define	DQL_ISTR301_DIO0DEF (0L<<5)

#define	DQL_ISTR301_DIO0OUT (1L<<5)

#define	DQL_ISTR301_DIO0GPIN (2L<<5)

#define	DQL_ISTR301_DIO0GPOUT (3L<<5)

#define	DQL_ISTR301_DIO0VAL (1L<<4)

#define	DQL_ISTR301_DIO0SRC (0)

#define	DQL_ISTR301_DIO0INT0 (0L<<0)

#define	DQL_ISTR301_DIO0INT1 (1L<<0)

#define	DQL_ISTR301_DIO0SRC2 (2L<<0)

#define	DQL_ISTR301_DIO0SRC3 (3L<<0)

#define	DQL_ISTR301_DIO1INV (1L<<15)

#define	DQL_ISTR301_DIO1MODE (13)

#define	DQL_ISTR301_DIO1DEF (0L<<13)

#define	DQL_ISTR301_DIO1OUT (1L<<13)

#define	DQL_ISTR301_DIO1GPIN (2L<<13)

#define	DQL_ISTR301_DIO1GPOUT (3L<<13)

#define	DQL_ISTR301_DIO1VAL (1L<<12)

#define	DQL_ISTR301_DIO1SRC (8)

#define	DQL_ISTR301_DIO1INT0 (0L<<8)

#define	DQL_ISTR301_DIO1INT1 (1L<<8)

#define	DQL_ISTR301_DIO1SRC2 (2L<<8)

#define	DQL_ISTR301_DIO1SRC3 (3L<<8)

#define	DQL_ISTR301_DIO2INV (1L<<23)

#define	DQL_ISTR301_DIO2MODE (21)

#define	DQL_ISTR301_DIO2DEF (0L<<21)

#define	DQL_ISTR301_DIO2OUT (1L<<21)

#define	DQL_ISTR301_DIO2GPIN (2L<<21)

#define	DQL_ISTR301_DIO2GPOUT (3L<<21)

#define	DQL_ISTR301_DIO2VAL (1L<<20)

#define	DQL_ISTR301_DIO2SRC (16)

#define	DQL_ISTR301_DIO2INT0 (0L<<16)

#define	DQL_ISTR301_DIO2INT1 (1L<<16)

#define	DQL_ISTR301_DIO2SRC2 (2L<<16)

#define	DQL_ISTR301_DIO2SRC3 (3L<<16)

#define	DQL_AO301_SYNC_WRITE (0xC1000000)

#define	DQ_AO301_CALSZ 4

#define	DQ_AO301_DCALSZ 16

#define	DQ_AO301_NAMELEN 32

#define	DQ_AO332_CALSZ (32)

#define	DQ_AO332_NAMELEN 12

#define	DQL_IOCTL301_WRITEWF (10L)

#define	DQL_IOCTL301_CTRLWF (11L)

#define	DQL_IOCTL3XX_READ_TEST (12L)

#define	DQ_IOCTL3XX_RD_TEST_INIT (0L)

#define	DQ_IOCTL3XX_RD_TEST_CVT (1L)

#define	DQ_IOCTL3XX_RD_TEST_END (2L)

#define	DQ_3XX_RD_TEST_SPAN (2.5)

#define	DQ_3XX_RD_TEST_STEP (DQ_3XX_RD_TEST_SPAN/(double)0xffffff)

#define	DQ_3XX_RD_TEST_OFFSET (DQ_3XX_RD_TEST_SPAN/2.0)

#define	DQ_308_RD_TEST_SF_350 ((10240.0)/(240.0))

#define	DQ_308_RD_TEST_SF_353 ((39240.0)/(240.0))

#define	DQ_308_RD_TEST_SF_V15 ((19840.0)/(240.0))

#define	DQ_308_RD_TEST_SF_VEX ((51240.0)/(240.0))

#define	DQ_308_RD_TEST_CHANS (12)

#define	DQ_332_RD_TEST_CHANS (32)

#define	DQ_AO3xx_STOP_WF (0)

#define	DQ_AO3xx_START_WF (1)

#define	DQ_AO3xx_PAUSE_WF (2)

#define	DQ_AO3xx_CONT_WF (3)

#define	DQ_AO3xx_PROG_WF (4)

#define	DQ_AO358_CHAN (8)

#define	DQ_AO358_CH_MASK (DQ_AO358_CHAN-1)

#define	DQ_AO358_FIFO_CH (128)

#define	DQ_AO358_CL_TIMES (2)

#define	DQ_AO358_ADC_CHAN_CHAN (5)

#define	DQ_AO358_ADC_CHANS (DQ_AO358_CHAN*DQ_AO358_ADC_CHAN_CHAN)

#define	DQ_AO358_ADC_CHAN_MASK (0x07)

#define	DQ_AO358_INFOSZ (DQ_MAX_INFO_SIZE)

#define	DQ_AO358_BASE (BUS_FREQUENCY)

#define	DQ_AO358_DMAPCV ((DQ_AO358_BASE/8000)-1)

#define	DQ_AO358_STARTRATE (DQ_AO358_DMAPCV)

#define	DQ_AO358_MAXCLFRQ (10000)

#define	DQ_AO358_MAXCVFRQ (DQ_AO358_MAXCLFRQ*DQ_AO358_CHAN)

#define	DQ_AO358_DEF_MIDPOS (800)

#define	DQ_AO358_LCR_LED (1L<<1)

#define	DQ_AO358_LCR_DCDIS (1L<<0)

#define	DQ_AO358_EE_CHK_STS (0x01)

#define	DQ_AO358_EE_RD_ID_ADDR (0x21)

#define	DQ_AO358_EE_RD (0x22)

#define	DQ_AO358_EE_WR_OPEN (0x31)

#define	DQ_AO358_EE_ERASE (0x32)

#define	DQ_AO358_EE_WR (0x33)

#define	DQ_AO358_EE_WR_CLOSE (0x34)

#define	DQ_AO358_EE_ERASE_SECTOR (0x35)

#define	DQ_AO358_EE_RD_MAX_LEN (1024)

#define	DQ_AO358_EE_WR_MAX_LEN (256)

#define	DQ_AO358_EE_ID_1M (0x10)

#define	DQ_AO358_EE_ID_4M (0x12)

#define	DQ_AO358_EE_ESTS_COMPLETE (1L<<31)

#define	DQ_AO358_EE_ESTS_ERR (1L<<30)

#define	DQ_AO358_EE_ESTS_BUSY (1L<<4)

#define	DQ_AO358_EE_ESTS_RFF (1L<<3)

#define	DQ_AO358_EE_ESTS_RFHF (1L<<2)

#define	DQ_AO358_EE_ESTS_WFE (1L<<1)

#define	DQ_AO358_EE_ESTS_WFHF (1L<<0)

#define	DQ_AO358_EE_INVALID_RDSTS (1L<<31)

#define	DQ_AO358_EE_RDSTS_BP (3L<<2)

#define	DQ_AO358_EE_RDSTS_WEL (1L<<1)

#define	DQ_AO358_EE_RDSTS_WIP (1L<<0)

#define	DQ_AO358_EE_CHKSTS_RETLEN (5)

#define	DQ_UNUSED_FOR_THIS_CMD (0)

#define	DQ_AO358_WRITE_STOP ((3L<<22)\|(3L<<10))

#define	DQ_AO358_WR_CH_SHIFT (28)

#define	DQ_AO358_FINE_SHIFT (12)

#define	DQ_AO358_COARSE_SHIFT (0)

#define	DQ_AO358_WR_CMD_ACB (1<<24)

#define	DQ_AO358_CFCH_MERGE(C, F, CH) (((C)&0x3FF)\|(((F)&0x3FF)<<DQ_AO358_FINE_SHIFT)\|((CH)<<DQ_AO358_WR_CH_SHIFT))

#define	DQ_AO358_SUBCH_I_SENSE (0)

#define	DQ_AO358_SUBCH_EX1 (1)

#define	DQ_AO358_SUBCH_EX2 (2)

#define	DQ_AO358_SUBCH_VS_N (3)

#define	DQ_AO358_SUBCH_THERM (4)

#define	DQ_AO358_MAKE_CL(CH, SUBCH) ((((CH)&DQ_AO358_CH_MASK)<<3)\|((SUBCH)& DQ_AO358_ADC_CHAN_MASK))

#define	DQ_AO358_CL_MASK (0x3f)

#define	DQ_AO385_AI_SPAN (5.0)

#define	DQ_AO385_OFFSET (DQ_AO385_AI_SPAN/2.0)

#define	DQ_AO385_STEP (DQ_AO385_AI_SPAN/(double)0xffffff)

#define	DQ_AO385_EXC_SCALER (51.75124)

#define	DQ_AO385_350_I_SHUNT (4.7)

#define	DQ_AO385_T_SLOPE (314.0)

#define	DQ_AO385_T_OFFSET (273.0)

#define	DQ_AO385_R4_MIN_350 (344.75)

#define	DQ_AO385_R4_MAX_350 (355.25)

#define	DQ_AO385_AO_SPAN_350 (DQ_AO385_R4_MAX_350-DQ_AO385_R4_MIN_350)

#define	DQ_AO385_RLUT_SZ (65536)

#define	DQ_AO385_RFINE_AT_CAL (256)

#define	DQ_AO385_RPOT_MASK (0x3ff)

#define	DQ_AO385_RPOT_MAX (1023.0)

#define	DQ_AO358_RPOTNOM_350 (20000.0)

#define	DQ_AO358_RWIPER_350 (60.0)

#define	DQ_AO358_R123_350 (1050.011)

#define	DQ_AO358_RPAR_350 (365.0)

#define	DQ_AO358_RDIV_350 (20804.0)

#define	DQ_AO358_RPROTC_350 (3000.0)

#define	DQ_AO358_RPROTF_350 (120000.0)

#define	DQ_AO358_RF_0X100_350 (5004.887586)

#define	DQ_AO358_RSTART_350 (344.75)

#define	DQ_AO358_CONVERGE_LIMIT (500)

#define	DQ_AO358_R4DELTA (12.37112)

#define	DQ_AO358_R4FDELTA (0.09885)

#define	DQ_AO358_NAMELEN (32)

#define	DQL_IOCTL358_WRITEWF (10L)

#define	DQL_IOCTL358_CTRLWF (11L)

#define	DQL_IOCTL358_RW_XEEPROM (0x0f)

#define	DQ_L401_CHAN 24

#define	DQ_L401_INFOSZ DQ_MAX_INFO_SIZE

#define	DQ_L401_BASE BUS_FREQUENCY

#define	DQ_L401_MAXCLFRQ 100000

#define	DQ_L401_MAXCVFRQ 100000

#define	DQL_IOCTL401_CFG_DI_CHANGE (1L)

#define	DQL_IOCTL401_WAIT_DI_CHANGE (2L)

#define	DqAdv401ConfigEvents_PARAMSZ 2

#define	DQ_LTC1661_VAL(V) ((V & 0x3ff)<<2)

#define	DQ_L401_MODESCAN (DQ_FIFO_MODESCAN)

#define	DQ_L401_MODEDGE (1UL << 16)

#define	DQ_L401_MODEFIFO (DQ_FIFO_MODEFIFO)

#define	DQ_L401_MODECONT (DQ_FIFO_MODECONT)

#define	DQ_L401_HYSTEN (1UL<<18)

#define	DIO401_2_4_5_CMDRDWR (DQL_CL_CMD1)

#define	DQ_L401_NAMELEN 20

#define	DQ_DIO403_LINES 48

#define	DQ_DIO403_CHAN 2

#define	DQ_DIO403_CHANSVC 2

#define	DQ_DIO403_INFOSZ DQ_MAX_INFO_SIZE

#define	DQ_DIO403_BASE BUS_FREQUENCY

#define	DQ_DIO403_PORTS 6

#define	DQ_DIO448_LINES 48

#define	DQ_DIO448_CHAN 2

#define	DQ_DIO448_CHANSVC 52

#define	DQ_DIO448_INFOSZ DQ_MAX_INFO_SIZE

#define	DQ_DIO448_BASE BUS_FREQUENCY

#define	DQL_IOCTL403_CFG_DI_CHANGE (11L)

#define	DQL_IOCTL403_WAIT_DI_CHANGE (12L)

#define	DQ_DIO448_PORTS 2

#define	DQ_DIO448_RANGE 45.0

#define	DQ_DIO448_STEP 0.000686646

#define	DQ_DIO448_CALDACS 4

#define	DQ_DIO448_CVT_CHNL(V) ((((float)V)*DQ_DIO448_STEP)-(DQ_DIO448_RANGE/2))

#define	DQ_DIO448_MIN_uVCnt 600

#define	DQ_DIO448_MAX_uVCnt 800

#define	DQ_DIO448_MAX_Offset 250

#define	DQ_DIO448_MAX_Hyst 30.0

#define	DQ_DIO403_MAXCVFRQ 10000

#define	DQ_DIO403_MODESCAN (DQ_FIFO_MODESCAN)

#define	DQ_DIO403_MODEFIFO (DQ_FIFO_MODEFIFO)

#define	DQ_DIO403_MODECONT (DQ_FIFO_MODECONT)

#define	DQ_DIO403_ENPORT5 (1UL << 28)

#define	DQ_DIO403_ENPORT4 (1UL << 27)

#define	DQ_DIO403_ENPORT3 (1UL << 26)

#define	DQ_DIO403_ENPORT2 (1UL << 25)

#define	DQ_DIO403_ENPORT1 (1UL << 24)

#define	DQ_DIO403_ENPORT0 (1UL << 23)

#define	DQ_DIO403_FIFO_GET_DATA DQ_FIFO_GET_DATA

#define	DQ_DIO403_FIFO_SET_DATA DQ_FIFO_SET_DATA

#define	DQL_CHAN448_CHSE(N) (((N)&0x3f)\|0x40)

#define	DQL_CHAN448_CHDF(N) (((N)&0x1f)\|0x40)

#define	DQL_CHAN448_PWR0 0x30

#define	DQL_CHAN448_PWR1 0x31

#define	DQL_CHAN448_GNDPIN 0x32

#define	DQL_CHAN448_VREF25 0x33

#define	DQL_CHAN448_STATUS 0x34

#define	DQL_CHAN448_TCJC 0x58

#define	DQL_CHAN448_GNDPINDI 0x59

#define	DQL_CHAN448_VREF25DI 0x5A

#define	DQL_CHAN448_GNDDI 0x5B

#define	DQL_CHAN448_ADCCHAN 0x40

#define	DQ_DIO403_NAMELEN 10

#define	DQ_DIO448_NAMELEN 10

#define	DQDIO448_CFGSET (1L<<0)

#define	DQDIO448_ADCDLYSET (1L<<1)

#define	DQDIO448_SETPARAM_SET 0

#define	DQDIO448_GETPARAM_GET 0

#define	DQL_IOCTL448_SET_LEVELS (0x6)

#define	DQL_IOCTL448_SET_DBREGS (0x7)

#define	DQ_DIO416_CHAN (16)

#define	DQ_DIO416_INFOSZ DQ_MAX_INFO_SIZE

#define	DQ_DIO416_BASE BUS_FREQUENCY

#define	DQ_DIO416_MAXCLFRQ 100000

#define	DQ_DIO416_MAXCVFRQ 100000

#define	DQ_DIO432_CHAN (32)

#define	DQ_DIO432_INFOSZ DQ_MAX_INFO_SIZE

#define	DQ_DIO432_BASE BUS_FREQUENCY

#define	DQ_DIO432_MAXCLFRQ 100000

#define	DQ_DIO432_MAXCVFRQ 100000

#define	DQL_DIO416S (0x2000)

#define	DQL_DIO416_CFG (0x2000)

#define	DQL_DIO416_PORT0OUT (0x2004)

#define	DQL_DIO416_DISCFG (0x2008)

#define	DQL_DIO416_DISSTS (0x2008)

#define	DQL_DIO416_ADCSTS (0x200C)

#define	DQL_DIO416_ADCSPD (0x200C)

#define	DQL_DIO416_PORT0OCS (0x2010)

#define	DQL_DIO416_PORT0OCM (0x2010)

#define	DQL_DIO416_PORT0UCS (0x2014)

#define	DQL_DIO416_PORT0UCM (0x2014)

#define	DQL_DIO416_RDCNT (0x2018)

#define	DQL_DIO416_ADCDATA0 (0x201C)

#define	DQL_DIO416_ADCCFG0 (0x201C)

#define	DQL_DIO416_ADCDATA1 (0x2020)

#define	DQL_DIO416_ADCCFG1 (0x2020)

#define	DQL_DIO416_DISDIV (0x2024)

#define	DQL_DIO416_DOUTACT (0x2028)

#define	DQL_DIO416_OCLS (0x2040)

#define	DQL_DIO416_OCLE (0x207C)

#define	DQL_DIO416_UCLS (0x2080)

#define	DQL_DIO416_UCLE (0x20BC)

#define	DQL_DIO416_ADCS (0x20C0)

#define	DQL_DIO416_ADCE (0x20FC)

#define	DQL_DIO416E (0x20FC)

#define	DQ_L416_ADCSPD_190 (1)

#define	DQ_L416_ADCSPD_130 (2)

#define	DQ_L416_ADCSPD_85 (3)

#define	DQ_L416_ADCSPD_45 (4)

#define	DQ_L416_ADCSPD_22 (5)

#define	DQ_L416_ADCSPD_12 (6)

#define	DQ_L416_ADCSPD_6_5 (7)

#define	DQ_L416_ADCSPD_3_2 (8)

#define	DQ_L416_ADCSPD_1_6 (9)

#define	DQ_L416_ADCSPD_0_8 (15)

#define	DQ_L416_ADCSPD_UONLY (31)

#define	DQ_L416_ADCSPD_NOBUSY (30)

#define	DQ_L416_ADCSPD_24BIT (29)

#define	DQ_L416_ADCSPD_ADCFE (28)

#define	DQ_L416_ADCSPD_DIVMSB (27)

#define	DQ_L416_ADCSPD_DIVLSB (20)

#define	DQ_L416_ADCSPD_ASL1BIT (19)

#define	DQ_L416_ADCSPD_MSB (3)

#define	DQ_L416_ADCSPD_LSB (0)

#define	DQ_L416_ADCSTS_ADC1CH_MSB (18)

#define	DQ_L416_ADCSTS_ADC1CH_LSB (16)

#define	DQ_L416_ADCSTS_ADC0CH_MSB (14)

#define	DQ_L416_ADCSTS_ADC0CH_LSB (12)

#define	DQ_L416_ADCSTS_ADC1TO (11)

#define	DQ_L416_ADCSTS_ADC1SM_MSB (10)

#define	DQ_L416_ADCSTS_ADC1SM_LSB (8)

#define	DQ_L416_ADCSTS_ADC0TO (7)

#define	DQ_L416_ADCSTS_ADC0SM_MSB (6)

#define	DQ_L416_ADCSTS_ADC0SM_LSB (4)

#define	DQ_L416_ADCDATA_OR (3)

#define	DQ_L416_ADCDATA_UR (1)

#define	DQ_L416_ADCDATA_OK (0)

#define	DQ_L416_ADCDATA_STS1 (28)

#define	DQ_L416_ADCDATA_STS0 (27)

#define	DQ_L416_ADCDATA_MSB (23)

#define	DQ_L416_ADCDATA_LSB (0)

#define	DQ_LSR416_VCCIS (23)

#define	DQ_LSR416_CLKIN_TRIG (22)

#define	DQ_LSR416_CLOUT (20)

#define	DQL_DIO432_BASES (0x2000)

#define	DQL_DIO432_BASEE (0x20FC)

#define	DQL_DIO432_DIN (0x2000)

#define	DQL_DIO432_DOUT (0x2004)

#define	DQL_DIO432_BLK0S (0x2100)

#define	DQL_DIO432_BLK0E (0x22FC)

#define	DQL_DIO432_BLK0 (0x100)

#define	DQL_DIO432_BLK1S (0x2300)

#define	DQL_DIO432_BLK1E (0x24FC)

#define	DQL_DIO432_BLK1 (0x300)

#define	DQL_DIO432_BLK2S (0x2500)

#define	DQL_DIO432_BLK2E (0x25FC)

#define	DQL_DIO432_BLK2 (0x500)

#define	DQL_DIO432_BLK3S (0x2600)

#define	DQL_DIO432_BLK3E (0x26FC)

#define	DQL_DIO432_BLK3 (0x600)

#define	DQL_DIO432_DIOS (0x2700)

#define	DQL_DIO432_CLKDIV (0x2708)

#define	DQL_DIO432_PWMDIV (0x270C)

#define	DQL_DIO432_DIODIVS (0x2800)

#define	DQL_DIO432_DIODIVE (0x287C)

#define	DQL_DIO432_DIOCFGS (0x2880)

#define	DQL_DIO432_DIOCFGE (0x28FC)

#define	DQL_DIO432_DIOUSRS (0x2900)

#define	DQL_DIO432_DIOUSRE (0x297C)

#define	DQL_DIO432_DIOE (0x297C)

#define	DQL_DIO432_VINCFG (0x00)

#define	DQL_DIO432_VINSTS (0x04)

#define	DQL_DIO432_USERCFG (0x08)

#define	DQL_DIO432_USERDATA (0x0C)

#define	DQL_DIO432_ADCDATAS (0x80)

#define	DQL_DIO432_ADCDATAE (0xBC)

#define	DQL_DIO432_VINCFG_UONLY (31)

#define	DQL_DIO432_VINCFG_24BIT (30)

#define	DQL_DIO432_VINCFG_ADCFE (29)

#define	DQL_DIO432_VINCFG_ASL1BIT (28)

#define	DQL_DIO432_VINCFG_DIVMSB (27)

#define	DQL_DIO432_VINCFG_DIVLSB (20)

#define	DQL_DIO432_VINCFG_SPEEDMSB (19)

#define	DQL_DIO432_VINCFG_SPEEDLSB (16)

#define	DQL_DIO432_VINCFG_DIMSB (15)

#define	DQL_DIO432_VINCFG_DILSB (0)

#define	DQL_DIO432_DIO_OFFSET(CH) (((CH&0x1F)<(DQ_DIO432_CHAN/2))?DQL_DIO432_BLK0:DQL_DIO432_BLK1)

#define	DQL_DIO432_VIN_OFFSET(CH) (((CH&0x1F)<(DQ_DIO432_CHAN/2))?DQL_DIO432_BLK2:DQL_DIO432_BLK3)

#define	DQL_DIO432_OFFSET0 (DQL_DIO432_BLK0)

#define	DQL_DIO432_OFFSET1 (DQL_DIO432_BLK1)

#define	DQL_IS_DIO432(N) ((N == 0x432)\|\|(N == 0x433))

#define	DQL_DIO432_VIN_CH_MAP(N) (DQL_DIO432_BASES \| DQL_DIO432_VIN_OFFSET(N) \| DQL_DIO432_ADCDATAS \| ((N&0xF) <<2))

#define	DQL_DIO432_IIN_CH_IDX(N) (((N&0xF) < 8L) ? (((N&0xF) << 3)+4L) : ((N&0xF)<<3))

#define	DQL_DIO432_IIN_CH_MAP(N) (DQL_DIO432_BASES \| DQL_DIO432_DIO_OFFSET(N) \| DQL_DIO416_ADCS \| DQL_DIO432_IIN_CH_IDX(N))

#define	DQL_DIO432_OCL_CH_MAP(N) (DQL_DIO432_BASES \| DQL_DIO432_DIO_OFFSET(N) \| DQL_DIO416_OCLS \| ((N&0xF) <<2))

#define	DQL_DIO432_UCL_CH_MAP(N) (DQL_DIO432_BASES \| DQL_DIO432_DIO_OFFSET(N) \| DQL_DIO416_UCLS \| ((N&0xF) <<2))

#define	DQ_L416_MAXCURRENT (2.0)

#define	DQ_L416_MINCURRENT (-2.0)

#define	DQ_L432_MAXCURRENT (2.0)

#define	DQ_L432_MINCURRENT (-2.0)

#define	DQ_L432_MAXVOLTAGE (63.75)

#define	DQ_L432_MINVOLTAGE (-63.75)

#define	DQ_L416_MAXRAW (0x00FFFFFF)

#define	DQ_L416_MINRAW (0x00000000)

#define	DQ_L432_MAXRAW_16BIT (0x0000FFFF)

#define	DQ_L432_MAXRAW_24BIT (0x00FFFFFF)

#define	DQ_L432_MINRAW (0x00000000)

#define	DQ_L416_MODESCAN (DQ_FIFO_MODESCAN)

#define	DQ_L416_MODEFIFO (DQ_FIFO_MODEFIFO)

#define	DQ_L416_MODECONT (DQ_FIFO_MODECONT)

#define	DIO416_CMDRDWR (DQL_CL_CMD1)

#define	DQDIO432_SETPARAM_SET 0

#define	DQDIO432_SETPARAM_PWM 1

#define	DQDIO432_GETPARAM_GET 0

#define	DQDIO432_GETPARAM_PWM 1

#define	DQL_IOCTL432_SETDCDC (0x8)

#define	DQ_L416_NAMELEN 20

#define	DQ_L432_NAMELEN 10

#define	DQDIO432_PWM_DISABLED 0

#define	DQDIO432_PWM_SOFTSTART 1

#define	DQDIO432_PWM_SOFTSTOP 2

#define	DQDIO432_PWM_SOFTBOTH 3

#define	DQDIO432_PWM_MODE 4

#define	DQDIO432_CFGSET (1L<<0)

#define	DQDIO432_DISCFGSET (1L<<1)

#define	DQDIO432_ADCSPDSET (1L<<2)

#define	DQDIO432_PORT0OCMSET (1L<<3)

#define	DQDIO432_PORT0UCMSET (1L<<4)

#define	DQDIO432_RDCNTSET (1L<<5)

#define	DQDIO432_DISDIVSET (1L<<6)

#define	DQ_DIO432_PORT0OCS_CH 0x40

#define	DQ_DIO432_PORT1OCS_CH 0x41

#define	DQ_DIO432_PORT0ACT_CH 0x42

#define	DQ_DIO432_PORT1ACT_CH 0x43

#define	DQ_DIO462_CHAN (12)

#define	DQ_DIO462_CH_MASK (0xf)

#define	DQ_DIO462_INFOSZ (DQ_MAX_INFO_SIZE)

#define	DQ_DIO462_BASE (BUS_FREQUENCY)

#define	DQ_DIO462_ADC_CHAN_CHAN (5)

#define	DQ_DIO462_ADC_CHANS (DQ_DIO462_CHAN*DQ_DIO462_ADC_CHAN_CHAN)

#define	DQ_DIO462_ADC_CHAN_MASK (0x07)

#define	DQ_DIO462_MAXCVFRQ (100000.0)

#define	DQ_DIO462_SUBCH_V_NO (0)

#define	DQ_DIO462_SUBCH_I_AC (1)

#define	DQ_DIO462_SUBCH_I_DC (2)

#define	DQ_DIO462_SUBCH_V_NC (3)

#define	DQ_DIO462_SUBCH_THERM (4)

#define	DQ_DIO462_DISABLE_BREAKER (5)

#define	DQ_DIO462_UNDER_LIMIT_OFFS (0x10)

#define	DQ_DIO462_MAKE_CL(CH, SUBCH) ((((CH)&DQ_DIO462_CH_MASK)<<3)\|((SUBCH)& DQ_DIO462_ADC_CHAN_MASK))

#define	DQ_DIO462_CL_MASK (0x7f)

#define	DQ_DIO462_CL_UNCALFLAG (0x80)

#define	DQ_DIO462_ISO_DC_NUM (4)

#define	DQ_DIO462_DEF_GAIN_CAL (0x8000)

#define	DQ_DIO462_DEF_OFFSET_CAL (0)

#define	DQ_DIO462_ISH (0.02)

#define	DQ_DIO462_ADC_VREF (3.0)

#define	DQ_DIO462_I_SCALER (1.0/DQ_DIO462_ISH)

#define	DQ_DIO462_IAC_ADCGAIN (1.0)

#define	DQ_DIO462_IAC_BGAIN (19.21)

#define	DQ_DIO462_IAC_SPAN ((DQ_DIO462_ADC_VREF)/DQ_DIO462_IAC_ADCGAIN)

#define	DQ_DIO462_IAC_STEP (DQ_DIO462_IAC_SPAN/(double)0xffff)

#define	DQ_DIO462_IAC_OFFSET ((DQ_DIO462_IAC_SPAN/2.0)+(DQ_DIO462_IAC_STEP/2.0))

#define	DQ_DIO462_IAC_SCALER ((DQ_DIO462_I_SCALER)/DQ_DIO462_IAC_BGAIN)

#define	DQ_DIO462_IDC_ADCGAIN (8.0)

#define	DQ_DIO462_IDC_SPAN ((DQ_DIO462_ADC_VREF)/DQ_DIO462_IDC_ADCGAIN)

#define	DQ_DIO462_IDC_STEP (DQ_DIO462_IDC_SPAN/(double)0xffff)

#define	DQ_DIO462_IDC_OFFSET ((DQ_DIO462_IDC_SPAN/2.0)+(DQ_DIO462_IDC_STEP/2.0))

#define	DQ_DIO462_IDC_SCALER (-DQ_DIO462_I_SCALER)

#define	DQ_DIO462_V_ADCGAIN (1.0)

#define	DQ_DIO462_V_SPAN (DQ_DIO462_ADC_VREF/DQ_DIO462_V_ADCGAIN)

#define	DQ_DIO462_V_STEP (DQ_DIO462_V_SPAN/(double)0xffff)

#define	DQ_DIO462_V_OFFSET ((DQ_DIO462_V_SPAN/2.0)+(DQ_DIO462_V_STEP/2.0))

#define	DQ_DIO462_V_SCALER (101.0)

#define	DQ_DIO462_T_SLOPE ((0.0000935)/DQ_DIO462_V_STEP)

#define	DQ_DIO462_T_OFFSET (273.0)

#define	DQ_DIO462_ADC_EOC (1L<<18)

#define	DQ_DIO462_ADC_SIG (1L<<16)

#define	DQ_DIO462_ADC_MSB (1L<<15)

#define	DQ_L462_MAX_P_DCVOLT (151.5)

#define	DQ_L462_MAX_N_DCVOLT (-30.0)

#define	DQ_L462_MAX_N_DCSPAN (-DQ_DIO462_V_SPAN/2.0)

#define	DQ_L462_MAX_ACCURRENT (3.0)

#define	DQ_L462_MAX_P_DCCURRENT (3.0)

#define	DQ_L462_MAX_N_DCCURRENT (-3.0)

#define	DQL_LCR_462_LED (1L<<1)

#define	DQL_LCR_462_DCEN (1L<<0)

#define	DQDIO462_SETPARAM_SET (0x10)

#define	DQDIO462_SETPARAM_LIMITS (0x11)

#define	DQDIO462_GETPARAM_GET (0x10)

#define	DQ_DIO462_ADC0_CFG_G1 (0xB080)

#define	DQ_DIO462_ADC1_CFG_G1 (0xB880)

#define	DQ_DIO462_ADC1_CFG_G8 (0xB882)

#define	DQ_DIO462_ADC2_CFG_G1 (0xB180)

#define	DQ_DIO462_ADC2_CFG_G8 (0xB182)

#define	DQ_DIO462_ADC3_CFG_G1 (0xB980)

#define	DQ_DIO462_ADC4_CFG (0xB0C0)

#define	DQ_DIO462_ADC_SETTLE_1 (0x10)

#define	DQ_DIO462_ADC0_CFG_G1_2X (0xB088)

#define	DQ_DIO462_ADC1_CFG_G1_2X (0xB888)

#define	DQ_DIO462_ADC1_CFG_G8_2X (0xB88b)

#define	DQ_DIO462_ADC2_CFG_G1_2X (0xB188)

#define	DQ_DIO462_ADC2_CFG_G2_2X (0xB189)

#define	DQ_DIO462_ADC2_CFG_G4_2X (0xB18a)

#define	DQ_DIO462_ADC2_CFG_G8_2X (0xB18b)

#define	DQ_DIO462_ADC3_CFG_G1_2X (0xB988)

#define	DQ_DIO462_ADC_SETTLE_1_2X (0x8)

#define	DQ_DIO462_DCDCCFG_MAX (0x5f)

#define	DQ_DIO462_DCDCCFG_MIN (0x1E)

#define	DQ_DIO462_DCDCCFG (0x5f)

#define	DQ_DIO462_DCDCX_START (0x3)

#define	DQ_DIO462_DCDCX_WIDTH (0xb)

#define	DQ_DIO462_DCDCX_CH_SP (DQ_DIO462_DCDCCFG/4)

#define	DQ_DIO462_DCDCX_0 (DQ_DIO462_DCDCX_START+(0DQ_DIO462_DCDCX_CH_SP)+((DQ_DIO462_DCDCX_START+DQ_DIO462_DCDCX_WIDTH+(0DQ_DIO462_DCDCX_CH_SP))<<16))

#define	DQ_DIO462_DCDCX_1 (DQ_DIO462_DCDCX_START+(1DQ_DIO462_DCDCX_CH_SP)+((DQ_DIO462_DCDCX_START+DQ_DIO462_DCDCX_WIDTH+(1DQ_DIO462_DCDCX_CH_SP))<<16))

#define	DQ_DIO462_DCDCX_2 (DQ_DIO462_DCDCX_START+(2DQ_DIO462_DCDCX_CH_SP)+((DQ_DIO462_DCDCX_START+DQ_DIO462_DCDCX_WIDTH+(2DQ_DIO462_DCDCX_CH_SP))<<16))

#define	DQ_DIO462_DCDCX_3 (DQ_DIO462_DCDCX_START+(3DQ_DIO462_DCDCX_CH_SP)+((DQ_DIO462_DCDCX_START+DQ_DIO462_DCDCX_WIDTH+(3DQ_DIO462_DCDCX_CH_SP))<<16))

#define	DQ_DIO462_DCDCX(N) (DQ_DIO462_DCDCX_START+((N)DQ_DIO462_DCDCX_CH_SP)+((DQ_DIO462_DCDCX_START+DQ_DIO462_DCDCX_WIDTH+((N)DQ_DIO462_DCDCX_CH_SP))<<16))

#define	DQ_DIO462_DFLT_RDCNT (3)

#define	DQ_L462_MAXCURRENT (3.0)

#define	DQ_L462_MINCURRENT (-3.0)

#define	DQ_L462_MAXRAW (0x0FFFF)

#define	DQ_L462_MINRAW (0x0)

#define	DQ_L462_NAMELEN (20)

#define	DQDIO462_CFGSET (1L<<0)

#define	DQDIO462_PORTOCMSET (1L<<3)

#define	DQDIO462_PORTUCMSET (1L<<4)

#define	DQDIO462_RDCNTSET (1L<<5)

#define	DQDIO462_ADCCFG0SET (1L<<7)

#define	DQDIO462_ADCCFG1SET (1L<<8)

#define	DQDIO462_ADCCFG2SET (1L<<9)

#define	DQDIO462_ADCCFG3SET (1L<<10)

#define	DQDIO462_ADCCFG4SET (1L<<11)

#define	DQDIO462_DCDCCFGSET (1L<<12)

#define	DQDIO462_DCDCXSET (1L<<13)

#define	DQ_L500_BAUD_110 (0UL << 28)

#define	DQ_L500_BAUD_300 (1UL << 28)

#define	DQ_L500_BAUD_600 (2UL << 28)

#define	DQ_L500_BAUD_1200 (3UL << 28)

#define	DQ_L500_BAUD_2400 (4UL << 28)

#define	DQ_L500_BAUD_4800 (5UL << 28)

#define	DQ_L500_BAUD_9600 (6UL << 28)

#define	DQ_L500_BAUD_14400 (7UL << 28)

#define	DQ_L500_BAUD_19200 (8UL << 28)

#define	DQ_L500_BAUD_28800 (9UL << 28)

#define	DQ_L500_BAUD_38400 (10UL << 28)

#define	DQ_L500_BAUD_57600 (11UL << 28)

#define	DQ_L500_BAUD_115200 (12UL << 28)

#define	DQ_L500_WIDTH_5 (0UL << 26)

#define	DQ_L500_WIDTH_6 (1UL << 26)

#define	DQ_L500_WIDTH_7 (2UL << 26)

#define	DQ_L500_WIDTH_8 (3UL << 26)

#define	DQ_L500_PARITY_EVEN (0UL << 24)

#define	DQ_L500_PARITY_ODD (1UL << 24)

#define	DQ_L500_PARITY_NONE (2UL << 24)

#define	DQ_L500_STOP_1 (0UL << 22)

#define	DQ_L500_STOP_1_5 (1UL << 22)

#define	DQ_L500_STOP_2 (2UL << 22)

#define	DQL_IOCTL500_SET_MSG_TIMER 1

#define	DQL_IOCTL500_SET_MSG_TERM 2

#define	DQL_IOCTL500_SET_MSG_LEN 3

#define	DQ_L501_CHAN (4)

#define	DQ_L508_CHAN (8)

#define	DQ_L501_INFOSZ (DQ_MAX_INFO_SIZE)

#define	DQ_L501_BASE_66 (66000000)

#define	DQ_L501_BASE_24 (24000000)

#define	DQ_L501_BASE_29 (29454545)

#define	DQ_L501_BASE_CUSTOM (0)

#define	DQ_L501_MFIFO_1 (1000000)

#define	DQ_L501_MAXCLFRQ (2000)

#define	DQ_L501_MAXCVFRQ (2000)

#define	DQ_L501_FIFOSZ (2048)

#define	DQ_L508_FIFOSZ (1024)

#define	DQ_L508_MAJORSZ (1024)

#define	L50x_FIFOSZ(MODEL) ((MODEL == 0x501)?(DQ_L501_FIFOSZ):(DQ_L508_FIFOSZ))

#define	DQ_L501_REPEAT_SUPPORTED (0xf)

#define	DQ_SL501_MSG_NORM (0)

#define	DQ_SL501_MSG_BREAK (1)

#define	DQ_SL501_MSG_ERR_FRM (2)

#define	DQ_SL501_MSG_ERR_PAR (3)

#define	DQ_SL501_MSG_ERR_TO (4)

#define	DQ_CL_OFS (8L)

#define	DQ_SL501_MODE_SH (0 + DQ_CL_OFS)

#define	DQ_SL501_PARITY_SH (2 + DQ_CL_OFS)

#define	DQ_SL501_STOP_SH (5 + DQ_CL_OFS)

#define	DQ_SL501_WIDTH_SH (7 + DQ_CL_OFS)

#define	DQ_SL501_OPER_SH (9 + DQ_CL_OFS)

#define	DQ_SL501_RTS_SH (10 + DQ_CL_OFS)

#define	DQ_SL501_DTS_SH (11 + DQ_CL_OFS)

#define	DQ_SL501_BAUD_SH (12 + DQ_CL_OFS)

#define	DQ_SL501_ERROR_SH (16 + DQ_CL_OFS)

#define	DQ_SL501_BREAK_SH (17 + DQ_CL_OFS)

#define	DQ_SL501_FSTE_SH (18 + DQ_CL_OFS)

#define	DQ_SL501_RXTE_SH (19 + DQ_CL_OFS)

#define	DQ_SL501_TXTE_SH (20 + DQ_CL_OFS)

#define	DQ_SL501_BAUD_PLL_SH (21 + DQ_CL_OFS)

#define	DQ_SL501_MODE_232 (0L)

#define	DQ_SL501_MODE_485F (1L)

#define	DQ_SL501_MODE_485H (2L)

#define	DQ_SL501_PARITY_NONE (0L)

#define	DQ_SL501_PARITY_EVEN (1L)

#define	DQ_SL501_PARITY_ODD (2L)

#define	DQ_SL501_PARITY_SPACE (3L)

#define	DQ_SL501_PARITY_MARK (4L)

#define	DQ_SL501_STOP_1 (0L)

#define	DQ_SL501_STOP_1_5 (1L)

#define	DQ_SL501_STOP_2 (2L)

#define	DQ_SL501_WIDTH_8 (0L)

#define	DQ_SL501_WIDTH_7 (1L)

#define	DQ_SL501_WIDTH_6 (2L)

#define	DQ_SL501_WIDTH_5 (3L)

#define	DQ_SL501_OPER_NORM (0L)

#define	DQ_SL501_OPER_LOOP (1L)

#define	DQ_SL501_RTS (1L)

#define	DQ_SL501_DTS (1L)

#define	DQ_SL501_BAUD_57600 (0L)

#define	DQ_SL501_BAUD_DEFAULT (DQ_SL501_BAUD_57600)

#define	DQ_SL501_BAUD_300 (1L)

#define	DQ_SL501_BAUD_600 (2L)

#define	DQ_SL501_BAUD_1200 (3L)

#define	DQ_SL501_BAUD_2400 (4L)

#define	DQ_SL501_BAUD_4800 (5L)

#define	DQ_SL501_BAUD_9600 (6L)

#define	DQ_SL501_BAUD_19200 (7L)

#define	DQ_SL501_BAUD_38400 (8L)

#define	DQ_SL501_BAUD_56000 (9L)

#define	DQ_SL501_BAUD_115200 (10L)

#define	DQ_SL501_BAUD_128000 (11L)

#define	DQ_SL501_BAUD_250000 (12L)

#define	DQ_SL501_BAUD_256000 (13L)

#define	DQ_SL501_BAUD_1000000 (14L)

#define	DQ_SL501_BAUD_CUST (15L)

#define	DQ_SL501_ERROR (1L)

#define	DQ_SL501_BREAK (1L)

#define	DQ_SL501_TERM_FS (1L)

#define	DQ_SL501_TERM_RX (1L)

#define	DQ_SL501_TERM_TX (1L)

#define	DQ_SL501_VMAP_STAT (1L<<9)

#define	DQL_IOCTL501_READ_CHNL (0x07L)

#define	DQL_IOCTL501_WRITE_CHNL (0x08L)

#define	DQL_IOCTL501_SETCHNL_CFG (0x09L)

#define	DQL_IOCTL501_START (0x0AL)

#define	DQL_IOCTL501_STOP (0x0BL)

#define	DQL_IOCTL501_BREAK (0x0CL)

#define	DQL_IOCTL501_CHANGE (0x0DL)

#define	DQL_IOCTL501_STATUS (0x0FL)

#define	DQL_IOCTL501_READ_CFIFO (0x1001L)

#define	DQL_IOCTL501_SETBAUD (0x01L)

#define	DQL_IOCTL501_SETTXWM (0x02L)

#define	DQL_IOCTL501_SETRXWM (0x03L)

#define	DQL_IOCTL501_SETTIMEOUT (0x04L)

#define	DQL_IOCTL501_SET_TS (0x05L)

#define	DQL_IOCTL501_SET_TL (0x06L)

#define	DQL_IOCTL501_SETRXWM_DIRECT (0x07L)

#define	DQL_IOCTL501_SETBASECLOCK (0x0CL)

#define	DQL_IOCTL501_SETCHARDLY (0x0DL)

#define	DQL_IOCTL501_SETFRAMEDLY (0x0EL)

#define	DQL_IOCTL501_CHANGE_FINCLEAR (0x1)

#define	DQL_IOCTL501_CHANGE_FOUTCLEAR (0x2)

#define	DQL_IOCTL501_CHANGE_FINFOUT (0x3)

#define	DQL_IOCTL501_CHANGE_SETCHCFG (0x4)

#define	DQL_IOCTL501_CHANGE_PARITY (0x8)

#define	DQL_IOCTL501_CHANGE_PAUSE (0x9)

#define	DQL_IOCTL501_CHANGE_RESUME (0xA)

#define	DQ_SL501_DELAYMODE_DISABLED (0)

#define	DQ_SL501_DELAYMODE_INTERNAL (1)

#define	DQ_SL501_DELAYMODE_TMR01 (2)

#define	DQ_SL501_DELAYMODE_SYNC02 (3)

#define	DQ_SL501_FRAMEDELAY_DISABLED (0)

#define	DQ_SL501_FRAMEDELAY_FIXEDLEN (1)

#define	DQ_SL501_FRAMEDELAY_VMAP_LEN (2)

#define	DQ_SL501_FRAMEDELAY_ZERO_CHAR (3)

#define	DQ_SL501_FRAMEDELAY_REPEAT (0x10)

#define	DQ_SL501_PARITY9_DISABLE (DQ_SL501_FRAMEDELAY_DISABLED)

#define	DQ_SL501_PARITY9_ENABLED (4)

#define	DQ_SL501_PARITY9 (1L<<8)

#define	DQ_SL501_MIXED_PARITY (1L<<9)

#define	DQMSG_501_SZ (DQ_MAX_MSG_SIZE - sizeof(DQMSG_501) - 2)

#define	DQCFG_501(OPER, MODE, BAUD, WIDTH, STOP, PARITY) (OPER << DQ_SL501_OPER_SH \| MODE << DQ_SL501_MODE_SH \| BAUD << DQ_SL501_BAUD_SH \| WIDTH << DQ_SL501_WIDTH_SH \| STOP << DQ_SL501_STOP_SH \| PARITY << DQ_SL501_PARITY_SH)

#define	DqAdv501ConfigEvents_PARAMSZ (7)

#define	EV501_FIFO_DATA (1L<<0)

#define	EV501_ACC_DATA (1L<<1)

#define	DQ_L501_MODESCAN (DQ_FIFO_MODESCAN)

#define	DQ_L501_MODEFIFO (DQ_FIFO_MODEFIFO)

#define	DQ_L501_MODECONT (DQ_FIFO_MODECONT)

#define	DQ_L501_ID_STANDARD (0x0L<<18)

#define	DQ_L501_ID_EXTENDED (0x1L<<18)

#define	DQ_L501_FIFO_GET_DATA (DQ_FIFO_GET_DATA)

#define	DQ_L501_FIFO_SET_DATA (DQ_FIFO_SET_DATA)

#define	DQ_C3PLL_MIN_FREQ_501 (16000000)

#define	DQ_C3PLL_MAX_FREQ_501 (32000000)

#define	DQ_C3PLL_CFG_24MHZ_VCO_POST (0)

#define	DQ_C3PLL_CFG_24MHZ_R (19)

#define	DQ_C3PLL_CFG_24MHZ_C (0)

#define	DQ_C3PLL_CFG_24MHZ_I (1)

#define	DQ_L501_NAMELEN (32)

#define	DQ_L508_NAMELEN (24)

#define	DQ_L503_CHAN (4)

#define	DQ_L503_INFOSZ (DQ_MAX_INFO_SIZE)

#define	DQ_L503_BASE (BUS_FREQUENCY)

#define	DQ_L503_MAXCLFRQ (2000)

#define	DQ_L503_MAXCVFRQ (2000)

#define	DQ_L503_RX_FIFOSZ (1024)

#define	DQ_L503_TX_FIFOSZ (512)

#define	DQ_L503_FIFO_RQ (10000)

#define	DQ_L503_TO_RQ (10)

#define	DQ_L503_RX_FIFO_ONEMSG (4)

#define	DQ_CAN503_RATE_10K (0 << 8)

#define	DQ_CAN503_RATE_20K (1 << 8)

#define	DQ_CAN503_RATE_50K (2 << 8)

#define	DQ_CAN503_RATE_100K (3 << 8)

#define	DQ_CAN503_RATE_125K (4 << 8)

#define	DQ_CAN503_RATE_250K (5 << 8)

#define	DQ_CAN503_RATE_500K (6 << 8)

#define	DQ_CAN503_RATE_800K (7 << 8)

#define	DQ_CAN503_RATE_1M (8 << 8)

#define	DQ_CAN503_RATE_10K_Baud (10000)

#define	DQ_CAN503_RATE_20K_Baud (20000)

#define	DQ_CAN503_RATE_50K_Baud (50000)

#define	DQ_CAN503_RATE_100K_Baud (100000)

#define	DQ_CAN503_RATE_125K_Baud (125000)

#define	DQ_CAN503_RATE_250K_Baud (250000)

#define	DQ_CAN503_RATE_500K_Baud (500000)

#define	DQ_CAN503_RATE_800K_Baud (800000)

#define	DQ_CAN503_RATE_1M_Baud (1000000)

#define	DQ_L503_MAX_PACKET_BITS (120)

#define	DQ_CAN503_MODE_BASIC (0 << 12)

#define	DQ_CAN503_MODE_XTEND (1 << 12)

#define	DQ_CAN503_OPER_NORMAL (0 << 13)

#define	DQ_CAN503_OPER_LISTEN (1 << 13)

#define	DQ_CAN503_ERR_NONE (0)

#define	DQ_CAN503_ERR_WARN (1)

#define	DQ_CAN503_ERR_AE (2)

#define	DQ_CAN503_ERR_BE (3)

#define	DQ_CAN503_ERR_OR (4)

#define	DQ_CAN503_ERR_TO (5)

#define	DQ_CAN503_ERR_RESET (6)

#define	DQ_CAN503_ERR_PASS (7)

#define	DQ_CAN503_VMAP_TIMESTAMP (1L<<8)

#define	DQ_CAN503_VMAP_STAT (1L<<9)

#define	DQL_IOCTL503_SET_MASK (0x1)

#define	DQL_IOCTL503_SET_RATE (0x2)

#define	DQL_IOCTL503_SET_OPER_MODE (0x3)

#define	DQL_IOCTL503_SETTXWM (0x4)

#define	DQL_IOCTL503_SETRXWM (0x5)

#define	DQL_IOCTL503_RESET_CHNL (0x4)

#define	DQL_IOCTL503_READ_CHNL (0x5)

#define	DQL_IOCTL503_WRITE_CHNL (0x6)

#define	DQL_IOCTL503_SETCHNL_CFG (0x7)

#define	DQL_IOCTL503_START (0x8)

#define	DQL_IOCTL503_STOP (0x9)

#define	DQL_IOCTL503_STATUS (0x0FL)

#define	DQ_L503_SEC_FIFO_SUPPORTED (0xf)

#define	DQ_CAN503_EC_BIT (0x00)

#define	DQ_CAN503_EC_FORM (0x40)

#define	DQ_CAN503_EC_STUFF (0x80)

#define	DQ_CAN503_EC_OTHER (0xC0)

#define	DQ_CAN503_DIR_RX (0x20)

#define	DQ_CAN503_DIR_TX (0x0)

#define	DQ_CAN503_BE_SOF (0x3)

#define	DQ_CAN503_BE_ID_28_21 (0x2)

#define	DQ_CAN503_BE_ID_20_18 (0x6)

#define	DQ_CAN503_BE_SRTR (0x4)

#define	DQ_CAN503_BE_IDE (0x5)

#define	DQ_CAN503_BE_ID_17_13 (0x7)

#define	DQ_CAN503_BE_ID_12_5 (0xf)

#define	DQ_CAN503_BE_ID_4_0 (0xe)

#define	DQ_CAN503_BE_RTR (0xc)

#define	DQ_CAN503_BE_DLC (0xb)

#define	DQ_CAN503_BE_DF (0xa)

#define	DQ_CAN503_BE_CRC_SEQ (0x8)

#define	DQ_CAN503_BE_CRC_DEL (0x18)

#define	DQ_CAN503_BE_ACK_SLT (0x19)

#define	DQ_CAN503_BE_ACK_DEL (0x1a)

#define	DQ_CAN503_BE_EOF (0x1a)

#define	DQ_CAN503_BE_IM (0x12)

#define	DQ_CAN503_BE_AEF (0x11)

#define	DQ_CAN503_BE_PEF (0x16)

#define	DQ_CAN503_BE_TDB (0x13)

#define	DQ_CAN503_BE_ERR_DEL (0x17)

#define	DQ_CAN503_BE_OL (0x1c)

#define	DQ_CAN503_BC_TX0 (0x0A)

#define	DQ_CAN503_PC_TX0 (0x10)

#define	ICR_SECFIFO_RD32 (4)

#define	ICR_SECFIFO_RD (16)

#define	ICR_SECFIFO_WR32 (4)

#define	ICR_SECFIFO_WR (16)

#define	DQ_L503_MODESCAN (DQ_FIFO_MODESCAN)

#define	DQ_L503_MODEFIFO (DQ_FIFO_MODEFIFO)

#define	DQ_L503_MODECONT (DQ_FIFO_MODECONT)

#define	DQ_L503_FIFO_GET_DATA (DQ_FIFO_GET_DATA)

#define	DQ_L503_FIFO_SET_DATA (DQ_FIFO_SET_DATA)

#define	CAN_EFF(D) (((D)&0x80)>>7)

#define	CAN_LEN(D) ( (((D)&0x0f)>8) ? 8 : ((D)&0x0f) )

#define	DQ503_MINSZ_SECRX(DT, CHANNEL) ( ((pDEVOBJ_503)DT->devobj)->chnls[CHANNEL].mode == DQ503_BASIC ? 13 : 14)

#define	DQ_L503_NAMELEN (32)

#define	DQ_L504_CHAN (4)

#define	DQ_L504_INFOSZ (DQ_MAX_INFO_SIZE)

#define	DQ_L504_BASE_66 (66000000)

#define	DQ_L504_MAXCLFRQ (2000)

#define	DQ_L504_MAXCVFRQ (2000)

#define	DQ_L504_FIFOSZ (2048)

#define	DQL_LCR504_LED (1L<<1)

#define	DQ_L504_MODESCAN (DQ_FIFO_MODESCAN)

#define	DQ_L504_MODEFIFO (DQ_FIFO_MODEFIFO)

#define	DQ_L504_MODECONT (DQ_FIFO_MODECONT)

#define	DQ_L504_ID_STANDARD (0x0L<<18)

#define	DQ_L504_ID_EXTENDED (0x1L<<18)

#define	DQ_L504_FIFO_GET_DATA (DQ_FIFO_GET_DATA)

#define	DQ_L504_FIFO_SET_DATA (DQ_FIFO_SET_DATA)

#define	DQ_L504_NAMELEN (32)

#define	DQ_L550_CHAN (1)

#define	DQ_L550_INFOSZ DQ_MAX_INFO_SIZE

#define	DQ_L550_BASE (66000000)

#define	DQIOCTL_SET550CFG (0x08)

#define	DQ_CAR550_WIRELESS_EN_DIS (0)

#define	DQ_L550_NAMELEN (32)

#define	DQ_L553_CHAN 2

#define	DQ_L553_CHAN_TX 2

#define	DQ_L553_CHAN_RX 2

#define	DQ_L553_INFOSZ DQ_MAX_INFO_SIZE

#define	DQ_L553_BASE 66000000

#define	DQ_L553_BC_BASE 1000000.0

#define	DQ_L553_MAXCLFRQ 2000

#define	DQ_L553_MAXCVFRQ 2000

#define	DQ_L553_TERMADDR 32

#define	DQ_L553_SUBADDR 32

#define	DQ_L553_MAX_MSG 64

#define	DQ_L553_MAX_WORDS 32

#define	DQ_L553_MAXBM_WORDS (DQ_L553_MAX_WORDS+4)

#define	DQ_L553_MAXRT_WORDS (DQ_L553_MAX_WORDS+7)

#define	DQ_L553_BROADADDR 0x1f

#define	DQ_L553_MODEADDR 0

#define	DQ_L553_INTCLKUS 100

#define	DQ_L553_MAXDLYCNT 65535

#define	DQL_LCR553_LED 2

#define	DQL_L553_MJ_SIZE 256

#define	DQL_L553_MN_SIZE 128

#define	DQ_L553_CH_MASK 0x0f

#define	DQ_L553_CH_CMDMASK 0xf0

#define	DQ_L553_TXFIFOSIZE 256

#define	DQ_L553_RXFIFOSIZE 1024

#define	DQ_L553_LBLFILTSIZE 256

#define	DQ_L553_SCHEDSIZE 256

#define	DQ_L553_SCHEDDATASZ 256

#define	DQ_L553_MD_FIFOSZ 19

#define	DQ_L553_A708_FIFO 2048

#define	DQ_L553_A708_TSTAMP_SZ 2

#define	DQ_L553_RTLISTSZ 360

#define	DQ_L553_A708_FRMSZ 100

#define	DQL_IOCTL553_SETMODE (0x01L)

#define	DQL_IOCTL553_SETTXWM (0x02L)

#define	DQL_IOCTL553_SETRXWM (0x03L)

#define	DQL_IOCTL553_SETTIMEOUT (0x04L)

#define	DQL_IOCTL553_READ_FIFO (0x05L)

#define	DQL_IOCTL553_WRITE_FIFO (0x06L)

#define	DQL_IOCTL553_TRIGGER (0x07L)

#define	DQL_IOCTL553_CONTROL (0x08L)

#define	DQL_IOCTL553_START (0x0AL)

#define	DQL_IOCTL553_BIT (0x0BL)

#define	DQL_IOCTL553_RESERVED (0x0CL)

#define	DQL_IOCTL553_FILTER (0x0DL)

#define	DQL_IOCTL553_SETCLK (0x0EL)

#define	DQL_IOCTL553_STATUS (0x0FL)

#define	DQL_IOCTL553_BM_CFG (0x1002L)

#define	DQL_IOCTL553_RT_CFG (0x1003L)

#define	DQL_IOCTL553_BC_CFG (0x1004L)

#define	DQL_IOCTL553_READ_RT (0x1005L)

#define	DQL_IOCTL553_WRITE_RT (0x1006L)

#define	DQL_IOCTL553_READ_RAM (0x1007L)

#define	DQL_IOCTL553_WRITE_RAM (0x1008L)

#define	DQL_IOCTL553_WRITE_MD (0x1009L)

#define	DQL_IOCTL553_READ_MD (0x100AL)

#define	DQL_IOCTL553_WRITE_BCCB (0x100BL)

#define	DQL_IOCTL553_READ_BCCB (0x100CL)

#define	DQL_IOCTL553_STATUS_BC (0x100DL)

#define	DQL_IOCTL553_CONTROL_BC (0x100EL)

#define	DQL_IOCTL553_RT_VALID (0x100FL)

#define	DQEVENT553_READ_RT (0x1005L)

#define	DQEVENT553_WRITE_RT (0x1006L)

#define	DQEVENT553_WRITE_MD (0x1009L)

#define	DQEVENT553_READ_MD (0x100AL)

#define	DQEVENT553_WRITE_BCCB (0x100BL)

#define	DQEVENT553_READ_BCCB (0x100CL)

#define	DQEVENT553_STATUS_BC (0x100DL)

#define	DQEVENT553_CONTROL_BC (0x100EL)

#define	DQL_IOCTL553_SETPARAM_READREG 1

#define	DQL_IOCTL553_SETPARAM_WRITEREG 2

#define	DQL_IOCTL553_SETPARAM_READABS 3

#define	DQL_IOCTL553_SETPARAM_WRITEABS 4

#define	DQL_IOCTL553_MAJORD 1

#define	DQL_IOCTL553_MINORD 2

#define	DQL_IOCTL553_MNBLOCK0 1

#define	DQL_IOCTL553_MNBLOCK1 2

#define	DQL_IOCTL553_MJ_SWAP 1

#define	DQL_IOCTL553_MN_SWAP 2

#define	DQL_IOCTL553_DEBUG_START 3

#define	DQL_IOCTL553_DEBUG_STOP 4

#define	DQL_IOCTL553_DEBUG_STEP_MJ 5

#define	DQL_IOCTL553_DEBUG_STEP_MN 6

#define	DQL_IOCTL553_DEBUG_GOTO 7

#define	DQL_IOCTL553_MJMN_CLEAR 8

#define	DQ_L553_MODE_BM (1L<<0)

#define	DQ_L553_MODE_RT (1L<<1)

#define	DQ_L553_MODE_BC (1L<<2)

#define	DQ_L553_MODE_A708 (1L<<3)

#define	DQ_L553_RT_LSTN_A (1L<<0)

#define	DQ_L553_RT_LSTN_B (1L<<1)

#define	DQ_L553_RT_TX_A (1L<<2)

#define	DQ_L553_RT_TX_B (1L<<3)

#define	DQ_L553_RT_RX_TSCMD (1L<<28)

#define	DQ_L553_RT_RX_CMD (1L<<29)

#define	DQ_L553_RT_DEFER_EN (1L<<30)

#define	DQ_L553_RT_LIST_ADD (1L<<31)

#define	DQ_L553_RT_INH_RX (1L<<12)

#define	DQ_L553_RT_INH_TX (1L<<13)

#define	DQ_L553_RT_INH_MODE (1L<<14)

#define	DQ_L553_RT_LB_EN (1L<<15)

#define	DQ_L553_RT_INH_BCSTREP (1L<<16)

#define	DQ_L553_BM_LSTN_A (1L<<0)

#define	DQ_L553_BM_LSTN_B (1L<<1)

#define	DQ_L553_BM_TX_A (1L<<2)

#define	DQ_L553_BM_TX_B (1L<<3)

#define	DQ_L553_A708_TX_BE (1L<<4)

#define	DQ_L553_A708_RX_BE (1L<<5)

#define	DQ_L553_STORE_TS (1L<<17)

#define	DQ_L553_STORE_FLAGS (1L<<18)

#define	DQ_L553_BM_LIST_ADD (1L<<31)

#define	DQ_L553_BM_SADDR(N) (((N)&0x1f)<<0)

#define	DQ_L553_BM_SADDR_SEL (1L<<5)

#define	DQ_L553_BM_RT(N) (((N)&0x1f)<<6)

#define	DQ_L553_BM_RT_SEL (1L<<11)

#define	DQ_L553_DISCONNECT (0L<<0)

#define	DQ_L553_TRANSFORMER (2L<<0)

#define	DQ_L553_COUPLE_DIRECTLY (3L<<0)

#define	DQ_L553_FORCE_A (1L<<4)

#define	DQ_L553_RT_SADDR(N) (((N)&0x1f)<<0)

#define	DQ_L553_RT_SADDR_SEL (1L<<5)

#define	DQ_L553_RT_RT(N) (((N)&0x1f)<<6)

#define	DQ_L553_RT_RT_SEL (1L<<11)

#define	DQ_L553_RT_SET_STATUS (1L<<12)

#define	DQ_L553_RT_SET_BLK1 (1L<<13)

#define	DQ_L553_RT_TX_SIZE(N) (((N)&0x1f)<<16)

#define	DQ_L553_RT_TX_CMDSTS (1L<<21)

#define	DQ_L553_RT_TX_TSCMD (1L<<22)

#define	DQ_L553_RT_TX_STS_NUM 0

#define	DQ_L553_RT_TX_VECTOR_NUM 1

#define	DQ_L553_RT_TX(RT, SA, SIZE) (DQ_L553_RT_RT(RT)\|DQ_L553_RT_RT_SEL\|DQ_L553_RT_SADDR(SA)\|DQ_L553_RT_SADDR_SEL\|DQ_L553_RT_TX_SIZE(SIZE))

#define	DQ_L553_RT_TX_BLK(RT, SA, SIZE, BLK) (DQ_L553_RT_RT(RT)\|DQ_L553_RT_RT_SEL\|DQ_L553_RT_SADDR(SA)\|DQ_L553_RT_SADDR_SEL\|DQ_L553_RT_TX_SIZE(SIZE)\|((BLK)?DQ_L553_RT_SET_BLK1:0))

#define	DQ_L553_RT_TX_STS(RT) (DQ_L553_RT_RT(RT)\|DQ_L553_RT_RT_SEL\|DQ_L553_RT_SADDR(DQ_L553_RT_TX_STS_NUM)\|DQ_L553_RT_SET_STATUS\|DQ_L553_RT_TX_SIZE(2))

#define	DQ_L553_RT_TX_VECTOR(RT) (DQ_L553_RT_RT(RT)\|DQ_L553_RT_RT_SEL\|DQ_L553_RT_SADDR(DQ_L553_RT_TX_VECTOR_NUM)\|DQ_L553_RT_SET_STATUS\|DQ_L553_RT_TX_SIZE(2))

#define	DQ_L553_RT_RX_DATA_RDY_NUM 0

#define	DQ_L553_RT_RX_DATA_SENT_NUM 1

#define	DQ_L553_RT_RX_PORT_STS_NUM 2

#define	DQ_L553_RT_RX_SYNC_NUM 3

#define	DQ_L553_RT_RX_MODE_NUM 4

#define	DQ_L553_RT_RX(RT, SA, SIZE) (DQ_L553_RT_RT(RT)\|DQ_L553_RT_RT_SEL\|DQ_L553_RT_SADDR(SA)\|DQ_L553_RT_SADDR_SEL\|DQ_L553_RT_TX_SIZE(SIZE))

#define	DQ_L553_RT_RX_BLK(RT, SA, SIZE, BLK) (DQ_L553_RT_RT(RT)\|DQ_L553_RT_RT_SEL\|DQ_L553_RT_SADDR(SA)\|DQ_L553_RT_SADDR_SEL\|DQ_L553_RT_TX_SIZE(SIZE)\|((BLK)?DQ_L553_RT_SET_BLK1:0))

#define	DQ_L553_RT_RX_DATA_RDY(RT, BLK) (DQ_L553_RT_RT(RT)\|DQ_L553_RT_RT_SEL\|DQ_L553_RT_SADDR(DQ_L553_RT_RX_DATA_RDY_NUM)\|DQ_L553_RT_SET_STATUS\|DQ_L553_RT_TX_SIZE(2)\|((BLK)?DQ_L553_RT_SET_BLK1:0))

#define	DQ_L553_RT_RX_DATA_SENT(RT, BLK) (DQ_L553_RT_RT(RT)\|DQ_L553_RT_RT_SEL\|DQ_L553_RT_SADDR(DQ_L553_RT_RX_DATA_SENT_NUM)\|DQ_L553_RT_SET_STATUS\|DQ_L553_RT_TX_SIZE(2)\|((BLK)?DQ_L553_RT_SET_BLK1:0))

#define	DQ_L553_RT_RX_PORT_STS(RT) (DQ_L553_RT_RT(RT)\|DQ_L553_RT_RT_SEL\|DQ_L553_RT_SADDR(DQ_L553_RT_RX_PORT_STS_NUM)\|DQ_L553_RT_SET_STATUS\|DQ_L553_RT_TX_SIZE(2))

#define	DQ_L553_RT_RX_SYNC(RT) (DQ_L553_RT_RT(RT)\|DQ_L553_RT_RT_SEL\|DQ_L553_RT_SADDR(DQ_L553_RT_RX_SYNC_NUM)\|DQ_L553_RT_SET_STATUS\|DQ_L553_RT_TX_SIZE(2))

#define	DQ_L553_RT_RX_MODE(RT) (DQ_L553_RT_RT(RT)\|DQ_L553_RT_RT_SEL\|DQ_L553_RT_SADDR(DQ_L553_RT_RX_MODE_NUM)\|DQ_L553_RT_SET_STATUS\|DQ_L553_RT_TX_SIZE(2))

#define	DQ_L553_RT_RT_SHR 6

#define	SL553_RT_CFG0_M0DIST (1L<<11)

#define	SL553_RT_CFG0_M1DIST (1L<<10)

#define	SL553_RT_CFG0_M0DIS (1L<<9)

#define	SL553_RT_CFG0_M1DIS (1L<<8)

#define	SL553_RT_CFG0_M1553A (1L<<7)

#define	SL553_RT_CFG0_RSTD (1L<<6)

#define	SL553_RT_CFG0_TF (1L<<5)

#define	SL553_RT_CFG0_SF (1L<<4)

#define	SL553_RT_CFG0_BSY (1L<<3)

#define	SL553_RT_CFG0_BSRE (1L<<2)

#define	SL553_RT_CFG0_SR (1L<<1)

#define	SL553_RT_DEFERRED (1L<<1)

#define	SL553_RT_DIS_MD_RST (1L<<2)

#define	DQ_L553_RT_STS0 (1L<<12)

#define	DQ_L553_RT_STS1 (2L<<12)

#define	DQ_L553_RT_STS2 (3L<<12)

#define	DQ_L553_RT_CHSTAT (4L<<12)

#define	DQ_L553_RT_BERRORS (5L<<12)

#define	DQ_L553_RT_DATA_RDY (6L<<12)

#define	DQ_L553_RT_DATA_SENT (7L<<12)

#define	DQ_L553_RT_STATMASK (7L<<12)

#define	DQ_L553_SET_TX_BLOCK (1L<<0)

#define	DQ_L553_SET_RX_BLOCK (1L<<1)

#define	DQ_L553_SET_RT_ENABLE (1L<<2)

#define	DQ_L553_SET_VALID_ENTRY (1L<<3)

#define	DQ_L553_SET_RT_RTIMING (1L<<4)

#define	DQ_L553_RTVAL_WRITE 0

#define	DQ_L553_RTVAL_OR_WRITE (1L<<16)

#define	DQ_L553_RTVAL_AND_WRITE (2L<<16)

#define	DQ_L553_RTVAL_CLEARALL (1L<<0)

#define	DQ_L553_READMEM_CYCLES 200

#define	DQ_L553_READMEM_ONE_SA 25

#define	DQ_L553_READMEM_nS 200

#define	DQ_L553_READFIFO 100

#define	DQ_L553_RTS_RT_STS (1L<<15)

#define	DQ_L553_RTS_RT_CTL (1L<<15)

#define	DQ_L553_RTS_CHAN_NUM (1L<<12)

#define	DQ_L553_RTS_RT_BLK1 (1L<<13)

#define	DQ_L553_RTS_XCODE (1L<<14)

#define	DQ_L553_RTS_STATUS (1L<<11)

#define	DQ_L553_RTS_CHAN_NUM_SHR 12

#define	DQ_L553_RTS_BLK1_SHR 13

#define	DQ_L553_RTS_SA_SHR 0

#define	DQ_L553_RTS_RT_SHR 6

#define	DQ_L553_RTS_STATUS_SHR 11

#define	DQ_L553_RTS_RT_STS_SHR 15

#define	DQ_L553_RTS_RT_CTL_SHR 15

#define	DQ_L553_SA_MASK 0x1f

#define	DQ_L553_RT_MASK 0x1f

#define	DQ_L553_DSIZE_MASK 0x1f

#define	DQ_L553_RTS_RQ_MASK 0x3f

#define	DQ_L553_RTS_SADDR(N) (((N)&0x1f)<<DQ_L553_RTS_SA_SHR)

#define	DQ_L553_RTS_RT(N) (((N)&0x1f)<<DQ_L553_RTS_RT_SHR)

#define	DQ_L553_RTS_CH(CH) (((CH)&1)<<DQ_L553_RTS_CHAN_NUM_SHR)

#define	DQ_L553_RTS_BLK(C) (((C)&1)<<DQ_L553_RTS_BLK1_SHR)

#define	DQ_L553_STATUS_STSF(CH, RT, STS) (DQ_L553_RTS_RT_STS\|DQ_L553_RTS_STATUS\|DQ_L553_RTS_RT(RT)\|DQ_L553_RTS_CH(CH)\|STS)

#define	DQ_L553_RTS_STS0 (1L<<0)

#define	DQ_L553_RTS_STS1 (1L<<1)

#define	DQ_L553_RTS_STS2 (1L<<2)

#define	DQ_L553_RTS_CHSTAT (1L<<3)

#define	DQ_L553_RTS_BERRORS (1L<<4)

#define	DQ_L553_STATUS_DATA(CH, RT, BLK, RQ) (DQ_L553_RTS_RT_STS\|DQ_L553_RTS_RT(RT)\|DQ_L553_RTS_BLK(BLK)\|(((CH)&1)<<DQ_L553_RTS_CHAN_NUM_SHR)\|RQ)

#define	DQ_L553_RTS_DATAREADY (1L<<0)

#define	DQ_L553_RTS_DATASENT (1L<<1)

#define	DQ_L553_RTS_BMDATA (1L<<2)

#define	DQ_L553_RTS_MODECMD (1L<<3)

#define	DQ_L553_CONTROL_CFG(CH, RT, RQ) ((((CH)&1)<<DQ_L553_RTS_CHAN_NUM_SHR)\|DQ_L553_RTS_RT_CTL\|DQ_L553_RTS_RT(RT)\|RQ)

#define	DQ_L553_RT(RT) (DQ_L553_BM_RT((RT))\|DQ_L553_BM_RT_SEL)

#define	DQ_L553_RT_SA(RT, SA) (DQ_L553_BM_RT((RT))\|DQ_L553_BM_RT_SEL\|DQ_L553_BM_SADDR((SA))\|DQ_L553_BM_SADDR_SEL)

#define	DQ_L553_CH_RT_SA(CH, RT, SA) ((((CH)&1)<<DQ_L553_RTS_CHAN_NUM_SHR)\|(DQ_L553_BM_RT((RT))\|DQ_L553_BM_RT_SEL)\|(DQ_L553_BM_SADDR((SA))\|DQ_L553_BM_SADDR_SEL))

#define	DQ_L553_RTS_CFG0 (1L<<0)

#define	DQ_L553_RTS_CFG1 (1L<<1)

#define	DQ_L553_RTS_TX_BLK (1L<<2)

#define	DQ_L553_RTS_RTEN (1L<<3)

#define	DQ_L553_RTS_RX_BLK (1L<<4)

#define	DQ_SL553_RTS_CFG0_RSTD (1L<<6)

#define	DQ_SL553_RTS_CFG0_TF (1L<<5)

#define	DQ_SL553_RTS_CFG0_SF (1L<<4)

#define	DQ_SL553_RTS_CFG0_BSY (1L<<3)

#define	DQ_SL553_RTS_CFG0_BSRD (1L<<2)

#define	DQ_SL553_RTS_CFG0_SR (1L<<1)

#define	DQ_SL553_RTS_CFG0_DBCE (1L<<0)

#define	DQ_SL553_RTS_CFG1(HI, LO) (((HI)<<16)\|((LOW)&0xffff))

#define	DQ_L553_DATA(CH, RT, SA, BLK) (DQ_L553_RTS_RT(RT)\|DQ_L553_RTS_SADDR(SA)\|DQ_L553_RTS_BLK(BLK)\|(((CH)&1)<<DQ_L553_RTS_CHAN_NUM_SHR))

#define	DQ_L553_MODESCAN (DQ_FIFO_MODESCAN)

#define	DQ_L553_MODEFIFO (DQ_FIFO_MODEFIFO)

#define	DQ_L553_MODECONT (DQ_FIFO_MODECONT)

#define	DQ_L553_READFIFO_ALL (0x100)

#define	DQ_L553_BMSTATUS_OVER (0x80)

#define	DQ_L553_FIFO_GET_DATA DQ_FIFO_GET_DATA

#define	DQ_L553_FIFO_SET_DATA DQ_FIFO_SET_DATA

#define	SL553_VALID_W(RMIN, RMAX, TMIN, TMAX, FLAGS) ((((RMIN)&0x1f)<<0)\|(((RMAX)&0x1f)<<5)\|(((TMIN)&0x1f)<<10)\|(((TMAX)&0x1f)<<15)\|((FLAGS)&0xfff00000))

#define	SL553_MODE_ENABLE 1

#define	MEMORY_553_VALIDATION 0

#define	MEMORY_553_DATA_0 1

#define	MEMORY_553_DATA_1 2

#define	MEMORY_553_DATA_READY 3

#define	MEMORY_553_DATA_SENT 4

#define	MEMORY_553_DATA_XCNG 5

#define	MEMORY_553_MAJOR 6

#define	MEMORY_553_MINOR 7

#define	SL553_TXFW_PAR (1L<<31)

#define	SL553_TXFW_WT (1L<<30)

#define	SL553_TXFW_DLY (1L<<29)

#define	SL553_TXFW_BUSA (1L<<28)

#define	SL553_TXFW_BUSB (0L<<28)

#define	SL553_TXFW_WORD(DLY, DATA) ((((DLY)&0xfff)<<16) \| ((DATA)&0xf000ffff))

#define	SL553_TXFW_ERR_WORD(CODE, DLY, DATA) (SL553_TXFW_WORD(DLY, DATA)\|UEI1553_ERR_CODE(CODE))

#define	SL553_TXFW_uSDLY(uS) (SL553_TXFW_DLY\|((uS)&0xfffffff))

#define	SL553_TX_COMMAND(RT, TR, SA, WC) (SL553_TXFW_WT\|(((RT)&31)<<11)\|(((TR)&1)<<10)\|(((SA)&31)<<5)\|(((WC)&31)<<0))

#define	SL553_CMD_GET_RT(C) (((C)>>11)&31)

#define	SL553_CMD_GET_SA(C) (((C)>>5)&31)

#define	SL553_CMD_GET_TR(C) (((C)>>10)&1)

#define	SL553_CMD_GET_WC(C) ((C)&31)

#define	UEI1553_PE (1<<31)

#define	UEI1553_TYPE (1<<30)

#define	UEI1553_DLYUS (1<<29)

#define	UEI1553_GAP12 (1<<28)

#define	UEI1553_GAP0 (1<<16)

#define	UEI1553_D15 (1<<15)

#define	UEI1553_D0 (1<<0)

#define	UEI1553_DLY28 (1<<28)

#define	UEI1553_DLY0 (1<<0)

#define	UEI1553_GAP_708D 0xD

#define	UEI1553_GAP_708CS 0xE

#define	UEI1553_GAP_708DS 0xF

#define	UEI1553_GAP_GET708(N) (((N)&0xf)>>26)

#define	UEI1553_GAP_GET(N) (((N)&0x1fff)>>16)

#define	UEI1553_ERR_CODE(N) (((N)&0xf)<<25)

#define	SL553_TXFW_708_WORD(CODE, DLY, DATA) (SL553_TXFW_WORD(DLY, DATA)\|UEI1553_ERR_CODE(CODE))

#define	UEI1553_ERR_NE 0x0

#define	UEI1553_ERR_SPE 0x1

#define	UEI1553_ERR_SNE 0x2

#define	UEI1553_ERR_DPE 0x3

#define	UEI1553_ERR_DNE 0x4

#define	UEI1553_ERR_TMB 0x5

#define	UEI1553_ERR_TFB 0x6

#define	UEI1553_ERR_SED 0x7

#define	UEI1553_ERR_DED 0x8

#define	UEI1553_ERR_708_DATA 0xf

#define	UEI1553_ERR_708_CSYNC 0xe

#define	UEI1553_ERR_708_DSYNC 0xd

#define	SL553_TRANSMIT 1

#define	SL553_RECEIVE 0

#define	SL553_TX_DATA(D) ((D)&0xffff)

#define	SL553_TX_STATUS(RT, ME, I, SR, BC, BSY, SS, DBA, TF) (SL553_TXFW_WT\|(((RT)&31)<<11)\|(((ME)&1)<<10)\|(((I)&1)<<9)\|(((SR)&1)<<8)\|(((BC)&1)<<4)\|(((BSY)&1)<<3)\|(((SS)&1)<<2)\|(((DBA)&1)<<1)\|(((TF)&1)<<0))

#define	DQ_SL553_ABS_MEM_ADDR(MODE, BLK, CH, RT, SA) ((((MODE)&1)<<18)\|(((BLK)&1)<<17)\|(((CH)&1)<<16)\|(((RT)&0x1f)<<11)\|(((SA)&0x1f)<<6))

#define	SL553_MJF_DESC_BCCB_A(N) ((N&0xf)<<10)

#define	SL553_MJF_DESC_LINK (1L<<9)

#define	SL553_MJF_DESC_EN (1L<<8)

#define	SL553_MJF_DESC_OT (1L<<7)

#define	SL553_MJF_DESC_IRQ (1L<<6)

#define	SL553_MJF_DESC_EN_SWAP (1L<<5)

#define	SL553_MJF_DESC_ED (1L<<4)

#define	SL553_MJF_DESC_MRF(N) ((N)&0xf)

#define	SL553_MJF_BCCB_SEGM(N) (((N)&0x7f)<<10)

#define	SL553_MNF_DESC_BCCB_A(N) ((N&0xff)<<10)

#define	SL553_MNF_DESC_EN (1L<<8)

#define	SL553_MNF_DESC_OT (1L<<7)

#define	SL553_MNF_DESC_CB (1L<<6)

#define	SL553_MNF_DESC_RR (1L<<5)

#define	SL553_MNF_DESC_ED (1L<<4)

#define	SL553_MNF_DESC_ERR (1L<<3)

#define	SL553_MNF_DESC_ERRC2 (1L<<2)

#define	SL553_MNF_DESC_ERRC0 (1L<<0)

#define	SL553_MNF_BLOCK1 (1L<<1)

#define	SL553_MNF_BLOCK0 (1L<<0)

#define	SL553_MNF_BCCB_OFFS(N) (((N)&0xf)<<10)

#define	DqAdv553ConfigEvents_PARAMSZ 7

#define	SL553_MEMVAL_LB_EN (1L<<30)

#define	SL553_MEMVAL_ERRI (1L<<29)

#define	SL553_MEMVAL_MD_TX_DW (1L<<28)

#define	SL553_MEMVAL_MD_RX_DW (1L<<27)

#define	SL553_MEMVAL_MD_IRQ_EN (1L<<26)

#define	SL553_MEMVAL_MD_TX_EN (1L<<25)

#define	SL553_MEMVAL_MD_RX_EN (1L<<24)

#define	SL553_MEMVAL_TX_IRQ_EN (1L<<23)

#define	SL553_MEMVAL_RX_IRQ_EN (1L<<22)

#define	SL553_MEMVAL_TX_EN (1L<<21)

#define	SL553_MEMVAL_RX_EN (1L<<20)

#define	SL553_MEMVAL_TX_WCMAX_MSB (1L<<19)

#define	SL553_MEMVAL_TX_WCMAX_LSB (1L<<15)

#define	SL553_MEMVAL_TX_WCMIN_MSB (1L<<14)

#define	SL553_MEMVAL_TX_WCMIN_LSB (1L<<10)

#define	SL553_MEMVAL_RX_WCMAX_MSB (1L<<9)

#define	SL553_MEMVAL_RX_WCMAX_LSB (1L<<5)

#define	SL553_MEMVAL_RX_WCMIN_MSB (1L<<4)

#define	SL553_MEMVAL_RX_WCMIN_LSB (1L<<0)

#define	CMD1553_MD_DBC 0x0

#define	CMD1553_MD_SYNC 0x1

#define	CMD1553_MD_TST 0x2

#define	CMD1553_MD_IST 0x3

#define	CMD1553_MD_TXD 0x4

#define	CMD1553_MD_OTXD 0x5

#define	CMD1553_MD_ITFB 0x6

#define	CMD1553_MD_OITFB 0x7

#define	CMD1553_MD_RRT 0x8

#define	CMD1553_MD_TVW 0x10

#define	CMD1553_MD_SYNCD 0x11

#define	CMD1553_MD_TLCW 0x12

#define	CMD1553_MD_TBIT 0x13

#define	CMD1553_MD_STXD 0x14

#define	CMD1553_MD_OSTXD 0x15

#define	CMD1553_RT_TX 0x20

#define	CMD1553_RT_RX 0x21

#define	CMD1553_RT_RT 0x22

#define	CMD1553_BROADCAST 0x80

#define	BC1553_BCB_FLAGS0_IRQ (1L<<15)

#define	BC1553_BCB_FLAGS0_BEN (1L<<14)

#define	BC1553_BCB_FLAGS0_AEN (1L<<13)

#define	BC1553_BCB_FLAGS0_EXW (1L<<12)

#define	BC1553_BCB_FLAGS0_RSV11 (1L<<11)

#define	BC1553_BCB_FLAGS0_RSV10 (1L<<10)

#define	BC1553_BCB_FLAGS0_RSV9 (1L<<9)

#define	BC1553_BCB_FLAGS0_SBUS (1L<<8)

#define	BC1553_BCB_FLAGS0_DTC (1L<<7)

#define	BC1553_BCB_FLAGS0_MDC (1L<<6)

#define	BC1553_BCB_FLAGS0_STS2 (1L<<5)

#define	BC1553_BCB_FLAGS0_STS1 (1L<<4)

#define	BC1553_BCB_FLAGS0_TT(N) ((N)&0xf)

#define	BC1553_BCB_TT_BCRT_1E 1

#define	BC1553_BCB_TT_RTBC_2B 2

#define	BC1553_BCB_TT_RTRT_3A 3

#define	BC1553_BCB_TT_MD_1A 4

#define	BC1553_BCB_TT_MDTX_2A 5

#define	BC1553_BCB_TT_MDRX_1C 6

#define	BC1553_BCB_TT_BBCRT_1F 7

#define	BC1553_BCB_TT_BRTRT_3B 8

#define	BC1553_BCB_TT_BMD_1B 9

#define	BC1553_BCB_TT_BMDRX_1D 10

#define	BC1553_BCB_FLAGS1_RSV15 (1L<<15)

#define	BC1553_BCB_FLAGS1_IRT (1L<<14)

#define	BC1553_BCB_FLAGS1_RUS (1L<<13)

#define	BC1553_BCB_FLAGS1_RUD (1L<<12)

#define	BC1553_BCB_FLAGS1_RWB (1L<<11)

#define	BC1553_BCB_FLAGS1_RIS (1L<<10)

#define	BC1553_BCB_FLAGS1_RBB (1L<<9)

#define	BC1553_BCB_FLAGS1_RTE (1L<<8)

#define	BC1553_BCB_FLAGS1_RWC (1L<<7)

#define	BC1553_BCB_FLAGS1_RE (1L<<6)

#define	BC1553_BCB_FLAGS1_RNR (1L<<5)

#define	BC1553_BCB_FLAGS1_ERE (1L<<4)

#define	BC1553_BCB_FLAGS1_ESR (1L<<3)

#define	BC1553_BCB_FLAGS1_ERRC(N) ((N)&7)

#define	BC1553_BCB_FLAGS2_ENABLE (1L<<15)

#define	BC1553_BCB_FLAGS2_DELAY(N) ((N)&0x7fff)

#define	BC1553_BCB_ERRSTS0_CB (1L<<15)

#define	BC1553_BCB_ERRSTS0_RSV14 (1L<<14)

#define	BC1553_BCB_ERRSTS0_PD (1L<<13)

#define	BC1553_BCB_ERRSTS0_S1B (1L<<12)

#define	BC1553_BCB_ERRSTS0_S2B (1L<<11)

#define	BC1553_BCB_ERRSTS0_BNR (1L<<10)

#define	BC1553_BCB_ERRSTS0_RCR (1L<<9)

#define	BC1553_BCB_ERRSTS0_WBR (1L<<8)

#define	BC1553_BCB_ERRSTS0_IRT (1L<<7)

#define	BC1553_BCB_ERRSTS0_LR (1L<<6)

#define	BC1553_BCB_ERRSTS0_ER (1L<<5)

#define	BC1553_BCB_ERRSTS0_S2F (1L<<4)

#define	BC1553_BCB_ERRSTS0_S1F (1L<<3)

#define	BC1553_BCB_ERRSTS0_DCF (1L<<2)

#define	BC1553_BCB_ERRSTS0_TFW (1L<<1)

#define	BC1553_BCB_ERRSTS0_TMW (1L<<0)

#define	BC1553_BCB_ERRSTS1_0000 0x00

#define	BC1553_BCB_ERRSTS1_0001 0x01

#define	BC1553_BCB_ERRSTS1_0002 0x02

#define	BC1553_BCB_ERRSTS1_0003 0x03

#define	BC1553_BCB_ERRSTS1_0004 0x04

#define	BC1553_BCB_ERRSTS1_0005 0x05

#define	BC1553_BCB_ERRSTS1_0006 0x06

#define	BC1553_BCB_ERRSTS1_0007 0x07

#define	BC1553_BCB_ERRSTS1_0008 0x08

#define	BC1553_BCB_ERRSTS1_0009 0x09

#define	BC1553_BCB_ERRSTS1_000A 0x0A

#define	BC1553_BCB_ERRSTS1_000B 0x0B

#define	BC1553_BCB_ERRSTS1_000C 0x0C

#define	BC1553_BCB_ERRSTS1_000D 0x0D

#define	BC1553_BCB_ERRSTS1_000E 0x0E

#define	BC1553_BCB_ERRSTS1_000F 0x0F

#define	BC1553_BCB_ERRSTS1_0010 0x10

#define	BC1553_BCB_ERRSTS1_0011 0x11

#define	BC1553_BCB_ERRSTS1_0012 0x12

#define	BC1553_BCB_ERRSTS1_0013 0x13

#define	BC1553_BCB_ERRSTS1_0014 0x14

#define	BC1553_BCB_ERRSTS1_0015 0x15

#define	BC1553_BCB_ERRSTS1_0016 0x16

#define	BC1553_BCB_ERRSTS1_0017 0x17

#define	BC1553_BCB_ERRSTS1_0018 0x18

#define	BC1553_BCB_ERRSTS1_0019 0x19

#define	BC1553_BCB_ERRSTS1_001A 0x1A

#define	BC1553_BCB_ERRSTS1_001B 0x1B

#define	BC1553_BCB_ERRSTS1_001C 0x1C

#define	BC1553_BCB_ERRSTS1_001D 0x1D

#define	BC1553_BCB_ERRSTS1_001E 0x1E

#define	BC1553_BCB_ERRSTS1_001F 0x1F

#define	BC1553_BCB_ERRSTS1_0020 0x20

#define	BC1553_BCB_ERRSTS1_0021 0x21

#define	BC1553_BCB_ERRSTS1_0022 0x22

#define	BC1553_BCB_ERRSTS1_0023 0x23

#define	BC1553_BCB_ERRSTS1_0024 0x24

#define	BC1553_BCB_ERRSTS1_0025 0x25

#define	BC1553_BCB_ERRSTS1_0026 0x26

#define	BC1553_BCB_ERRSTS1_0027 0x27

#define	BC1553_BCB_ERRSTS1_0028 0x28

#define	BC1553_BCB_ERRSTS1_0029 0x29

#define	BC1553_BCB_ERRSTS1_002A 0x2A

#define	BC1553_BCB_ERRSTS1_002B 0x2B

#define	BC1553_BCB_ERRSTS1_002C 0x2C

#define	BC1553_BCB_ERRSTS1_002D 0x2D

#define	BC1553_BCB_ERRSTS1_002E 0x2E

#define	BC1553_BCB_ERRSTS1_002F 0x2F

#define	BC1553_BCB_ERRSTS1_0030 0x30

#define	BC1553_BCB_ERRSTS1_0031 0x31

#define	BC1553_BCB_ERRSTS1_0032 0x32

#define	BC1553_BCB_ERRSTS1_0033 0x33

#define	BC1553_BCB_ERRSTS1_0034 0x34

#define	BC1553_BCB_ERRSTS1_0035 0x35

#define	BC1553_BCB_ERRSTS1_0036 0x36

#define	BC1553_BCB_ERRSTS1_0037 0x37

#define	BC1553_BCB_ERRSTS1_0100 0x100

#define	BC1553_BCB_ERRSTS1_0200 0x200

#define	BC1553_BCB_ERRSTS1_0300 0x300

#define	BC1553_BCB_ERRSTS1_0400 0x400

#define	BC1553_BCB_ERRSTS1_0500 0x500

#define	BC1553_BCB_ERRSTS1_0600 0x600

#define	BC1553_BCB_ERRSTS1_0700 0x700

#define	BC1553_BCB_ERRSTS1_0800 0x800

#define	BC1553_BCB_ERRSTS1_0900 0x900

#define	BC1553_BCB_ERRSTS1_0A00 0xA00

#define	BC1553_BCB_ERRSTS1_0B00 0xB00

#define	BC1553_BCB_ERRSTS1_0C00 0xC00

#define	BC1553_BCB_ERRSTS1_0D00 0xD00

#define	BC1553_BCB_ERRSTS1_8000 0x8000

#define	SL553_PORT_BCSTS_BSY (1L<<31)

#define	SL553_PORT_BCSTS_RSV30 (1L<<30)

#define	SL553_PORT_BCSTS_RSV29 (1L<<29)

#define	SL553_PORT_BCSTS_RSV28 (1L<<28)

#define	SL553_PORT_BCSTS_MRF3 (1L<<27)

#define	SL553_PORT_BCSTS_MRF0 (1L<<24)

#define	SL553_PORT_BCSTS_DSC7 (1L<<23)

#define	SL553_PORT_BCSTS_DSC0 (1L<<16)

#define	SL553_PORT_BCSTS_BIR (1L<<12)

#define	SL553_PORT_BCSTS_BTO (1L<<11)

#define	SL553_PORT_BCSTS_BAD (1L<<10)

#define	SL553_PORT_BCSTS_BWB (1L<<9)

#define	SL553_PORT_BCSTS_BCO (1L<<8)

#define	SL553_PORT_BCSTS_HBT (1L<<7)

#define	SL553_PORT_BCSTS_MTD (1L<<6)

#define	SL553_PORT_BCSTS_RTR (1L<<5)

#define	SL553_PORT_BCSTS_MF (1L<<4)

#define	SL553_PORT_BCSTS_MRBF (1L<<3)

#define	SL553_PORT_BCSTS_MBRF (1L<<2)

#define	SL553_PORT_BCSTS_RBF (1L<<1)

#define	SL553_PORT_BCSTS_BRF (1L<<0)

#define	SL553_PORT_BCSTS_MRF(S) (((S)&0xf000000)>>24)

#define	SL553_PORT_BCSTS_DSC(S) (((S)&0xff0000)>>16)

#define	SL553_PORT_BCSWAP_MNF(MASK) ((MASK)&0xffff)

#define	SL553_PORT_BCGT_CMD(N) (((N)&0xf)<<28)

#define	SL553_PORT_BCGT_CMD_BCB_NORET (0L<<28)

#define	SL553_PORT_BCGT_CMD_MNF_NORET (1L<<28)

#define	SL553_PORT_BCGT_CMD_BCB_BCB (2L<<28)

#define	SL553_PORT_BCGT_CMD_MNF_BCB (3L<<28)

#define	SL553_PORT_BCGT_CMD_BCB_MNF (4L<<28)

#define	SL553_PORT_BCGT_CMD_MNF_MNF (5L<<28)

#define	SL553_PORT_BCGT_MNFD(N) (((N)&0xff)<<8)

#define	SL553_PORT_BCGT_MJFD(N) (((N)&0xff)<<0)

#define	SL553_PORT_BCPOS_GP (1L<<31)

#define	SL553_PORT_BCPOS_GET_GMNFD(N) (((N)>>24)&0xff)

#define	SL553_PORT_BCPOS_GET_GMJFD(N) (((N)>>16)&0xff)

#define	SL553_PORT_BCPOS_CUR_BLOCK(N) (((N)>>15)&0x1)

#define	SL553_PORT_BCPOS_CUR_MNFD(N) (((N)>>8)&0x7f)

#define	SL553_PORT_BCPOS_CUR_MJFD(N) (((N)>>0)&0xff)

#define	DQ_SL553_BC_DATA (1L<<12)

#define	DQ_SL553_BC_STATUS (2L<<12)

#define	DQ_SL553_BC_BC_STATUS (3L<<12)

#define	DQ_SL553_BC_BUSMON (4L<<12)

#define	DQ_SL553_BC_MN_DESC (5L<<12)

#define	DQ_SL553_BC_MJ_DESC (6L<<12)

#define	DQ_SL553_BC_TYPE (0x7<<12)

#define	DQ_SL553_BC_VMAP_DATA (1L)

#define	DQ_SL553_BC_VMAP_STATUS (2L)

#define	DQ_SL553_BC_VMAP_CONTROL (2L)

#define	DQ_SL553_BC_VMAP_BUSMON (4L)

#define	DQ_SL553_BC_VMAP_MN_DESC (5L)

#define	DQ_SL553_BC_VMAP_MJ_DESC (6L)

#define	DQ_SL553_BC_VMAP(CH, TYPE, MN, BLK, IDX) ((((TYPE)&0x7)<<13)\|(((CH)&1)<<12)\|(((MN)&0xf)<<8)\|(((BLK)&0x1)<<7)\|((IDX)&0x7f))

#define	DQ_SL553_BC_GET_MN(N) (((N)>>8)&0xf)

#define	DQ_SL553_BC_GET_IDX(N) (((N))&0xff)

#define	DQ_SL553_BC_GET_TYPE(N) (((N)>>13)&0x7)

#define	DQ_SL553_BC_GET_CHAN(N) (((N)>>12)&0x1)

#define	DQ_SL553_BC_GET_MNBLK(N) (((N)>>7)&0x1)

#define	SL553_CMDWORD_RT(C) (((C)&0xf800)>>11)

#define	SL553_CMDWORD_TR(C) (((C)&0x0400)>>10)

#define	SL553_CMDWORD_SA(C) (((C)&0x03e0)>>5)

#define	SL553_CMDWORD_WC(C) (((C)&0x01f)>>0)

#define	DQ_SL553_BC_STATUS_RQ(STS_TYPE, INDEX) ((DQ_SL553_BC_STATUS)\|(((STS_TYPE)&0xf)<<8)\|((INDEX)&0xff))

#define	DQ_SL553_BC_STATUS_BC 1

#define	DQ_SL553_BC_STATUS_MJ 2

#define	DQ_SL553_BC_STATUS_ISRC 3

#define	DQ_SL553_BC_STATUS_ERR 4

#define	DQ_SL553_BC_STATUS_PORT 5

#define	DQ_SL553_BC_STATUS_BCPOS 6

#define	_CAPS_553_

#define	DQ_L553_NAMELEN 32

#define	SL553_MEMVAL_TXEN (1L<<21)

#define	SL553_MEMVAL_RXEN (1L<<20)

#define	DQ_SL553_MEMVAL_RT (SL553_MEMVAL_TXEN\|SL553_MEMVAL_RXEN)

#define	LUT553_ENTRIES 16

#define	DQ_AR566_CHAN 6

#define	DQ_AR512_CHAN 12

#define	DQ_AR566_CHAN_TX 6

#define	DQ_AR566_CHAN_RX 12

#define	DQ_AR566_INFOSZ DQ_MAX_INFO_SIZE

#define	DQ_AR566_BASE 66000000

#define	DQ_AR566_MAXCLFRQ 2000

#define	DQ_AR566_MAXCVFRQ 2000

#define	DQ_AR566_INTCLKUS 100

#define	DQ_AR566_MAXDLYCNT 65535

#define	DQL_LCR566_LED 2

#define	DQ_AR566_CH_MASK 0x0f

#define	DQ_AR566_CH_CMDMASK 0xf0

#define	DQ_AR566_CH_RXFIFOAVL 0x20

#define	DQ_AR566_CH_TXFIFOAVL 0x30

#define	DQ_AR566_CH_SCHED 0x40

#define	DQ_AR566_CH_SCHDATA 0x50

#define	DQ_AR566_CH_FILTER 0x60

#define	DQ_AR566_CH_LASTDATA 0x70

#define	AR566_TXFIFOSIZE 256

#define	AR566_RXFIFOSIZE 256

#define	AR566_LBLFILTSIZE 256

#define	AR566_SCHEDSIZE 256

#define	AR566_SCHEDDATASZ 256

#define	DQ_AR_ENABLE_DIO0 (1L<<0)

#define	DQ_AR_ENABLE_DIO1 (1L<<1)

#define	DQ_AR_ENABLE_DIO2 (1L<<2)

#define	DQ_AR_SETFILTER_PUT (1L<<0)

#define	DQ_AR_SETFILTER_GET (1L<<1)

#define	DQ_AR_SETFILTER_FILL_TABLE (1L<<4)

#define	DQ_AR_SETSCHED_PUT (1L<<0)

#define	DQ_AR_SETSCHED_GET (1L<<1)

#define	DQ_AR_SETSCHED_DATA_ONLY (1L<<2)

#define	DQ_AR_SETSCHED_FILL_TABLE (1L<<4)

#define	DQ_AR_RXCTR_NDO (1L<<8)

#define	DQ_AR_RXCTR_TRIG (1L<<9)

#define	DQ_AR_RATEHIGH (1L<<0)

#define	DQ_AR_RATELOW (0)

#define	DQ_AR_PARITYODD (1L<<1)

#define	DQ_AR_PARITYEVEN (1L<<2)

#define	DQ_AR_PARITYOFF (0)

#define	DQ_AR_SDI_ENABLED (1L<<3)

#define	DQ_AR_SDI_DISABLED (0)

#define	DQ_AR_XBIT_ENABLED (1L<<4)

#define	DQ_AR_XBIT_DISABLED (0)

#define	DQ_AR_FEW_ENABLED (1L<<5)

#define	DQ_AR_FEW_DISABLED (0)

#define	DQ_AR_SHORTGAP_ENABLED (1L<<6)

#define	DQ_AR_SHORTGAP_DISABLED (0)

#define	DQ_AR_TIMESTAMP_ENABLED (1L<<7)

#define	DQ_AR_TIMESTAMP_DISABLED (0)

#define	DQ_AR_SLOWSLEW_ENABLED (1L<<8)

#define	DQ_AR_SLOWSLEW_DISABLED (0)

#define	DQ_AR_SDIMASK0 (1L<<9)

#define	DQ_AR_SDIMASK1 (1L<<10)

#define	DQ_AR_SDIMASKOFFSET (9)

#define	DQ_AR_LB_CHECK_PARITY (1L<<12)

#define	DQ_AR_ADD_TIMESTAMP (1L<<13)

#define	DQ_FRCNT_COUNT_ALL (0L<<14)

#define	DQ_FRCNT_COUNT_GOOD (1L<<14)

#define	DQ_FRCNT_COUNT_FIFO (2L<<14)

#define	DQ_FRCNT_COUNT_TRIGGER (3L<<14)

#define	DQ_FRCNT_COUNT_PAR_ERR (4L<<14)

#define	DQ_FRCNT_COUNT_OFFSET (14)

#define	DQ_AR_ALLOW_ZERO_LBL (1L<<15)

#define	DQ_AR_ALLOW_FIFO_HIGH (1L<<16)

#define	DQ_AR_IGNORE_BAD_DATA (1L<<19)

#define	DQ_AR_SCHED_PSDISABLED (0)

#define	DQ_AR_SCHED_PS100us (1L<<20)

#define	DQ_AR_SCHED_PSTB0 (2L<<20)

#define	DQ_AR_SCHED_PSTB1 (3L<<20)

#define	DQ_AR_FIFO_PSTB0 (1L<<20)

#define	DQ_AR_FIFO_PSTB1 (3L<<20)

#define	DQ_AR_MASTER (1L<<17)

#define	DQ_AR_RECYCLE (1L<<16)

#define	DQ_AR_TxPRIORITY_HIGH (1L<<0)

#define	DQ_AR_TxPRIORITY_LOW (1L<<1)

#define	DQ_AR_Tx_BLOCKING (1L<<2)

#define	DQ_AR_Rx_LATEST (1L<<0)

#define	DQ_AR_Rx_FIFO (1L<<1)

#define	DQ_AR_Rx_BLOCKING (1L<<2)

#define	DQ_AR_STATUS_CLEAR_ERROR (1L<<0)

#define	DQ_AR_STATUS_CLEAR_COUNT (1L<<1)

#define	DQ_AR_STATUS_GET_TOTAL (1L<<2)

#define	DQ_AR_STATUS_GET_FRM_CTR (1L<<3)

#define	DQ_AR_STATUS_GET_FRM_ERR (1L<<4)

#define	DQ_AR_STATUS_GET_FRM_MIS (1L<<5)

#define	DQ_AR_STATUS_GET_FIFO_CNT (1L<<6)

#define	DQ_AR_ENABLE_Tx (1L<<8)

#define	DQ_AR_ENABLE_Rx (1L<<9)

#define	DQ_AR_ENABLE_SCHEDULER (1L<<10)

#define	DQ_AR_ENABLE_LOOPBACK (1L<<11)

#define	DQ_AR_ENABLE_FILTER (1L<<12)

#define	DQ_AR_ENABLE_RxFIFO (1L<<13)

#define	DQ_AR_ENABLE_TxFIFO (1L<<14)

#define	DQ_AR_LOGIC_LOOPBACK (1L<<15)

#define	DQ_AR_SCHEDULER_RATE 0

#define	DQ_AR_FIFO_RATE 1

#define	DQL_IOCTL566_CHANGE_FINCLEAR (0x1)

#define	DQL_IOCTL566_CHANGE_FOUTCLEAR (0x2)

#define	DQL_IOCTL555_CHANGE_FINFOUT (0x3)

#define	DQL_IOCTL566_CHANGE_PAUSE (0x9)

#define	DQL_IOCTL566_CHANGE_RESUME (0xA)

#define	DQL_IOCTL566_SETCFG (0x01L)

#define	DQL_IOCTL566_SETTXWM (0x02L)

#define	DQL_IOCTL566_SETRXWM (0x03L)

#define	DQL_IOCTL566_SETTIMEOUT (0x04L)

#define	DQL_IOCTL566_READ_FIFO (0x05L)

#define	DQL_IOCTL566_WRITE_FIFO (0x06L)

#define	DQL_IOCTL566_READ_CHNL (0x07L)

#define	DQL_IOCTL566_WRITE_CHNL (0x08L)

#define	DQL_IOCTL566_SETCHNL_MODE (0x09L)

#define	DQL_IOCTL566_START (0x0AL)

#define	DQL_IOCTL566_STOP (0x0BL)

#define	DQL_IOCTL566_SCHED (0x0CL)

#define	DQL_IOCTL566_FILTER (0x0DL)

#define	DQL_IOCTL566_SETCLK (0x0EL)

#define	DQL_IOCTL566_STATUS (0x0FL)

#define	DQL_IOCTL566_CHANGE (0x21L)

#define	DQL_IOCTL566_SETCHNL_CFG (0x1001L)

#define	AR566_ILE11 (1L<<29)

#define	AR566_ILE10 (1L<<28)

#define	AR566_ILE9 (1L<<27)

#define	AR566_ILE8 (1L<<26)

#define	AR566_ILE7 (1L<<25)

#define	AR566_ILE6 (1L<<24)

#define	AR566_ILE5 (1L<<23)

#define	AR566_ILE4 (1L<<22)

#define	AR566_ILE3 (1L<<21)

#define	AR566_ILE2 (1L<<20)

#define	AR566_ILE1 (1L<<19)

#define	AR566_ILE0 (1L<<18)

#define	AR566_IPE11 (1L<<11)

#define	AR566_IPE10 (1L<<10)

#define	AR566_IPE9 (1L<<9)

#define	AR566_IPE8 (1L<<8)

#define	AR566_IPE7 (1L<<7)

#define	AR566_IPE6 (1L<<6)

#define	AR566_IPE5 (1L<<5)

#define	AR566_IPE4 (1L<<4)

#define	AR566_IPE3 (1L<<3)

#define	AR566_IPE2 (1L<<2)

#define	AR566_IPE1 (1L<<1)

#define	AR566_IPE0 (1L<<0)

#define	DQ_AR_ALL_ERROR_FLASG (0x1FFFFFFF)

#define	AR566_TXSCC_ERR0 (1L<<31)

#define	AR566_TXSCC_ECO (1L<<24)

#define	AR566_TXSCC_ME (1L<<23)

#define	AR566_TXSCC_EO (1L<<22)

#define	AR566_TXSCC_PS1 (1L<<21)

#define	AR566_TXSCC_PS0 (1L<<20)

#define	AR566_TXSCC_PS_DISABLED (0)

#define	AR566_TXSCC_PS_100US (1)

#define	AR566_TXSCC_PS_PS0 (2)

#define	AR566_TXSCC_PS_PS1 (3)

#define	AR566_TXSCC_RSV1 (1L<<19)

#define	AR566_TXSCC_RSV0 (1L<<18)

#define	AR566_TXSCC_MA (1L<<17)

#define	AR566_TXSCC_RC (1L<<16)

#define	AR566_TXSCC_TD15 (1L<<15)

#define	AR566_TXSCC_TD0 (1L<<0)

#define	AR566_RXLAF_TR (1L<<9)

#define	AR566_RXLAF_ND (1L<<8)

#define	AR566_RXLAF_D7 (1L<<7)

#define	AR566_RXLAF_D0 (1L<<0)

#define	AR566_RXFDR_CEC_S (16)

#define	AR566_RXFDR_CMC_S (0)

#define	AR566_RXFDR_CEC (1L<<11)

#define	AR566_RXFDR_CMC (1L<<10)

#define	AR566_RXFDR_SRC1 (1L<<9)

#define	AR566_RXFDR_SRC0 (1L<<8)

#define	AR566_RXFDR_SC_S (0)

#define	AR566_RXFDR_SRC_SCH (0)

#define	AR566_RXFDR_SRC_FF (1)

#define	AR566_RXFDR_SRC_HPR (2)

#define	AR566_RXFDR_SRC_LPR (3)

#define	DQ_AR566_MODESCAN (DQ_FIFO_MODESCAN)

#define	DQ_AR566_MODEFIFO (DQ_FIFO_MODEFIFO)

#define	DQ_AR566_MODECONT (DQ_FIFO_MODECONT)

#define	DQ_AR566_ID_STANDARD (0x0L << 18)

#define	DQ_AR566_ID_EXTENDED (0x1L << 18)

#define	DQ_AR566_FIFO_GET_DATA DQ_FIFO_GET_DATA

#define	DQ_AR566_FIFO_SET_DATA DQ_FIFO_SET_DATA

#define	DQ_AR566_NAMELEN 32

#define	DQ_PL_601_CHAN (8)

#define	DQ_PL_601_CHANSVC (8)

#define	DQ_PL_601_INFOSZ (DQ_MAX_INFO_SIZE)

#define	DQ_PL_601_BASE (BUS_FREQUENCY)

#define	DQ_PL_601_BASE_DOUBLE (BUS_FREQUENCY<<1)

#define	DQ_PL_601_MAXCLFRQ (50000)

#define	DQ_PL_601_MAXCVFRQ (50000)

#define	DQ_PL601_CHNLTYPE_MASK (0xf0)

#define	DQ_PL601_CHNLNUM_MASK (0x0f)

#define	DQ_PL601_CHNLTYPE_STATUS (0x10)

#define	DQ_PL601_CHNLTYPE_CRH (0x20)

#define	DQ_PL601_CHNLTYPE_CRL (0x30)

#define	DQ_PL601_CHNLTYPE_CR0 (0x40)

#define	DQ_PL601_CHNLTYPE_CR1 (0x50)

#define	DQ_PL601_SMAUTO (0L)

#define	DQ_PL601_SMHARD (1L)

#define	DQ_PL601_SMSOFT (2L)

#define	DQ_PL601_SW8 (1L)

#define	DQ_PL601_SW16 (2L)

#define	DQ_PL601_SW32 (4L)

#define	DQL_IOCTL601_SETCHNL_CFG (1L)

#define	DQL_IOCTL601_SET_REG (2L)

#define	DQL_IOCTL601_GET_REG (3L)

#define	DQL_IOCTL601_CTR_EN (4L)

#define	DQL_IOCTL601_CTR_DIS (5L)

#define	DQL_IOCTL601_ENALL (6L)

#define	DQL_IOCTL601_DISALL (7L)

#define	DQL_IOCTL601_READCHNL (8L)

#define	DQL_IOCTL601_WRITECHNL (9L)

#define	DQL_IOCTL601_CTR_CLR (10L)

#define	DQL_IOCTL601_SET_WM (11L)

#define	DQL_IOCTL601_ADDITIONAL (12L)

#define	DQL_IOCTL601_START (0x0AL)

#define	DQL_IOCTL601_STOP (0x0BL)

#define	DQ_L601_FIFOSZ (256)

#define	DQEVENT601_READ_CTR (0x1005L)

#define	DQEVENT601_WRITE_CTR (0x1006L)

#define	DQEVENT601_STATUS_CTR (0x1007L)

#define	DQEVENT601_CONTROL_CTR (0x1008L)

#define	DqAdv601ConfigEvents_PARAMSZ 7

#define	DQ_ICR_CTU7 (1L<<7)

#define	DQ_ICR_CTU6 (1L<<6)

#define	DQ_ICR_CTU5 (1L<<5)

#define	DQ_ICR_CTU4 (1L<<4)

#define	DQ_ICR_CTU3 (1L<<3)

#define	DQ_ICR_CTU2 (1L<<2)

#define	DQ_ICR_CTU1 (1L<<1)

#define	DQ_ICR_CTU0 (1L<<0)

#define	DQ_CLI_CTU0S 0x2000

#define	DQ_CLI_CTU0E 0x207C

#define	DQ_CLI_CTU1S 0x2080

#define	DQ_CLI_CTU1E 0x20FC

#define	DQ_CLI_CTU2S 0x2100

#define	DQ_CLI_CTU2E 0x217C

#define	DQ_CLI_CTU3S 0x2180

#define	DQ_CLI_CTU3E 0x21FC

#define	DQ_CLI_CTU4S 0x2200

#define	DQ_CLI_CTU4E 0x227C

#define	DQ_CLI_CTU5S 0x2280

#define	DQ_CLI_CTU5E 0x22FC

#define	DQ_CLI_CTU6S 0x2300

#define	DQ_CLI_CTU6E 0x237C

#define	DQ_CLI_CTU7S 0x2380

#define	DQ_CLI_CTU7E 0x23FC

#define	DQ_CTU_STR 0x00

#define	DQ_CTU_CTR 0x00

#define	DQ_CTU_CCR 0x04

#define	DQ_CTU_PS 0x08

#define	DQ_CTU_CR 0x0C

#define	DQ_CTU_LR 0x0C

#define	DQ_CTU_IDBC 0x10

#define	DQ_CTU_IDBG 0x14

#define	DQ_CTU_PC 0x18

#define	DQ_CTU_CRH 0x1C

#define	DQ_CTU_CR0 0x1C

#define	DQ_CTU_CRL 0x20

#define	DQ_CTU_CR1 0x20

#define	DQ_CTU_TBR 0x24

#define	DQ_CTU_FCNTI 0x28

#define	DQ_CTU_IFWR 0x2C

#define	DQ_CTU_FDTI 0x30

#define	DQ_CTU_FCNTO 0x34

#define	DQ_CTU_OFWR 0x38

#define	DQ_CTU_FDTO 0x3C

#define	DQ_CTU_ISR 0x40

#define	DQ_CTU_IER 0x40

#define	DQ_CTU_ICR 0x44

#define	DQ_CTU_FDDO 0x48

#define	DQ_CTU_TEST0 0x4C

#define	DQ_CTU_TEST1 0x50

#define	DQ_CTU_REGADDR(CLE) (0x2000\|CLE)

#define	DQ_STR_EN 31

#define	DQ_STR_BUSY 30

#define	DQ_STR_CR0L 29

#define	DQ_STR_CR0GE 28

#define	DQ_STR_CR1 27

#define	DQ_STR_IN0 26

#define	DQ_STR_GT0 25

#define	DQ_STR_IN1 24

#define	DQ_STR_GT1 23

#define	DQ_STR_IHL 22

#define	DQ_STR_ILH 21

#define	DQ_STR_GHL 20

#define	DQ_STR_GLH 19

#define	DQ_STR_OU 18

#define	DQ_STR_IRQ 17

#define	DQ_STR_CRH 16

#define	DQ_STR_CRL 15

#define	DQ_STR_IFE 14

#define	DQ_STR_IFH 13

#define	DQ_STR_IFF 12

#define	DQ_STR_OFE 11

#define	DQ_STR_OFH 10

#define	DQ_STR_OFF 9

#define	DQ_STR_GT 8

#define	DQ_CTR_EN 31

#define	DQ_CTR_IFE 30

#define	DQ_CTR_IFS 29

#define	DQ_CTR_IIE 28

#define	DQ_CTR_GIE 27

#define	DQ_CTR_OIE 26

#define	DQ_CTR_OU 25

#define	DQ_CTR_OFE 24

#define	DQ_CTR_CLFI 23

#define	DQ_CTR_CLFO 22

#define	DQ_CTR_CLR 21

#define	DQ_CTR_GPIO 20

#define	DQ_CTR_GTSE 19

#define	DQ_CTR_GTPE 18

#define	DQ_CCR_RE 31

#define	DQ_CCR_EC2 30

#define	DQ_CCR_EC1 29

#define	DQ_CCR_EC0 28

#define	DQ_CCR_CRM3 27

#define	DQ_CCR_CRM2 26

#define	DQ_CCR_CRM1 25

#define	DQ_CCR_CRM0 24

#define	DQ_CCR_PSG 23

#define	DQ_CCR_TRS 22

#define	DQ_CCR_ENC 21

#define	DQ_CCR_TBS 18

#define	DQ_CCR_PSS 15

#define	DQ_CCR_MM2X 14

#define	DQ_TBR_EN 31

#define	DQ_IR_CPT 31

#define	DQ_IR_CR0L 30

#define	DQ_IR_CR0GE 29

#define	DQ_IR_CR1 28

#define	DQ_IR_LHI 27

#define	DQ_IR_LHG 26

#define	DQ_IR_HLI 25

#define	DQ_IR_HLG 24

#define	DQ_IR_CRH 23

#define	DQ_IR_CRL 22

#define	DQ_IR_IFE 21

#define	DQ_IR_IFH 20

#define	DQ_IR_IFF 19

#define	DQ_IR_OFE 18

#define	DQ_IR_OFH 17

#define	DQ_IR_OFF 16

#define	DQ_IR601_CPT (1L<<31)

#define	DQ_IR601_CR0L (1L<<30)

#define	DQ_IR601_CR0GE (1L<<29)

#define	DQ_IR601_CR1 (1L<<28)

#define	DQ_IR601_LHI (1L<<27)

#define	DQ_IR601_LHG (1L<<26)

#define	DQ_IR601_HLI (1L<<25)

#define	DQ_IR601_HLG (1L<<24)

#define	DQ_IR601_CRH (1L<<23)

#define	DQ_IR601_CRL (1L<<22)

#define	DQ_IR601_IFE (1L<<21)

#define	DQ_IR601_IFH (1L<<20)

#define	DQ_IR601_IFF (1L<<19)

#define	DQ_IR601_OFE (1L<<18)

#define	DQ_IR601_OFH (1L<<17)

#define	DQ_IR601_OFF (1L<<16)

#define	DQ_EM_CR0 (0)

#define	DQ_EM_CR1 (1)

#define	DQ_EM_FFF (2)

#define	DQ_EM_PC (3)

#define	DQ_EM_TBR (4)

#define	DQ_EM_GT (5)

#define	DQL_ADDMODE_DOUBLE_PRECISION (1L<<14)

#define	EV601_LOW_TO_HI (1)

#define	EV601_HI_TO_LOW (2)

#define	DQ_CM_CT (0x0)

#define	DQ_CM_TPPM (0x1)

#define	DQ_CM_TCT (0x4)

#define	DQ_CM_TTPPM (0x5)

#define	DQ_CM_RTCT (0x7)

#define	DQ_CM_ECT (0x8)

#define	DQ_CM_HP (0x9)

#define	DQ_CM_NP (0xA)

#define	DQ_CM_QE (0xB)

#define	DQ_CM_TECT (0xC)

#define	DQ_CM_THP (0xD)

#define	DQ_CM_TNP (0xE)

#define	DQ_PL_601_MODESCAN (0L << 16)

#define	DQ_PL_601_MODEFIFO (2L << 16)

#define	DQ_PL_601_MODECONT (3L << 16)

#define	DQ_PL_601_TSCOPY (1L << 18)

#define	DQ_PL_601_FIFO_GET_DATA (DQ_FIFO_GET_DATA)

#define	DQ_PL_601_NAMELEN 16

#define	DQ_PL_604_CHAN 4

#define	DQ_PL_604_CHANSVC 4

#define	DQ_PL_604_INFOSZ DQ_MAX_INFO_SIZE

#define	DQ_PL_604_BASE BUS_FREQUENCY

#define	DQ_PL_604_PLL 16500000

#define	DQ_PL_604_MAXCLFRQ 50000

#define	DQ_PL_604_MAXCVFRQ 50000

#define	DQ_PL604_CHNLMASK (0xf0)

#define	DQ_PL604_MSGNORM (0)

#define	DQL_IOCTL604_SETCHNL_CFG (1L)

#define	DQL_IOCTL604_SET_REG (2L)

#define	DQL_IOCTL604_GET_REG (3L)

#define	DQL_IOCTL604_CTR_EN (4L)

#define	DQL_IOCTL604_CTR_DIS (5L)

#define	DQL_IOCTL604_ENALL (6L)

#define	DQL_IOCTL604_DISALL (7L)

#define	DQL_IOCTL604_READCHNL (8L)

#define	DQL_IOCTL604_CTR_CLR (9L)

#define	DQL_IOCTL604_SET_WM (10L)

#define	DQL_IOCTL604_GET_DIN (11L)

#define	DQL_IOCTL604_GET_DOUT (12L)

#define	DQL_IOCTL604_SET_DOUT (13L)

#define	DQ_L604_FIFOSZ 1024

#define	DQ_ICR_QDU3 3

#define	DQ_ICR_QDU2 2

#define	DQ_ICR_QDU1 1

#define	DQ_ICR_QDU0 0

#define	DQ_ICR_QDU_MASK (0xf)

#define	QD604_QDU0S 0x2100

#define	QD604_QDU0E 0x21FC

#define	QD604_QDU1S 0x2200

#define	QD604_QDU1E 0x22FC

#define	QD604_QDU2S 0x2300

#define	QD604_QDU2E 0x23FC

#define	QD604_QDU3S 0x2400

#define	QD604_QDU3E 0x24FC

#define	QD604_DIN_604 0x2000

#define	QD604_DOUT_604 0x2004

#define	QD604_QDU_STR 0x00

#define	QD604_QDU_CTR 0x04

#define	QD604_QDU_CCR 0x08

#define	QD604_QDU_CR 0x0C

#define	QD604_QDU_LR 0x10

#define	QD604_QDU_IDBA 0x14

#define	QD604_QDU_IDBB 0x18

#define	QD604_QDU_IDBZ 0x1C

#define	QD604_QDU_IDBT 0x20

#define	QD604_QDU_CR0 0x24

#define	QD604_QDU_CR1 0x28

#define	QD604_QDU_TBR 0x2C

#define	QD604_QDU_QED 0x30

#define	QD604_QDU_OW 0x34

#define	QD604_QDU_INC 0x38

#define	QD604_QDU_FCNTI 0x3C

#define	QD604_QDU_IFWR 0x40

#define	QD604_QDU_FDTI 0x44

#define	QD604_QDU_IER 0x48

#define	QD604_QDU_ISR 0x4C

#define	QD604_QDU_ICR 0x4C

#define	QD604_DIN_604_INT3 15

#define	QD604_DIN_604_INZ3 14

#define	QD604_DIN_604_INB3 13

#define	QD604_DIN_604_INA3 12

#define	QD604_DIN_604_INT2 11

#define	QD604_DIN_604_INZ2 10

#define	QD604_DIN_604_INB2 9

#define	QD604_DIN_604_INA2 8

#define	QD604_DIN_604_INT1 7

#define	QD604_DIN_604_INZ1 6

#define	QD604_DIN_604_INB1 5

#define	QD604_DIN_604_INA1 4

#define	QD604_DIN_604_INT0 3

#define	QD604_DIN_604_INZ0 2

#define	QD604_DIN_604_INB0 1

#define	QD604_DIN_604_INA0 0

#define	QD604_DOUT_604_CLK3 7

#define	QD604_DOUT_604_TRIG3 6

#define	QD604_DOUT_604_CLK2 5

#define	QD604_DOUT_604_TRIG2 4

#define	QD604_DOUT_604_CLK1 3

#define	QD604_DOUT_604_TRIG1 2

#define	QD604_DOUT_604_CLK0 1

#define	QD604_DOUT_604_TRIG0 0

#define	QD604_QDU_STR_EN 31

#define	QD604_QDU_STR_TOOFAST 30

#define	QD604_QDU_STR_CR0L 29

#define	QD604_QDU_STR_BUSY 30

#define	QD604_QDU_STR_CROL 29

#define	QD604_QDU_STR_CROG 28

#define	QD604_QDU_STR_CR1 27

#define	QD604_QDU_STR_AHL 26

#define	QD604_QDU_STR_ALH 25

#define	QD604_QDU_STR_BHL 24

#define	QD604_QDU_STR_BLH 23

#define	QD604_QDU_STR_ZHL 22

#define	QD604_QDU_STR_ZLH 21

#define	QD604_QDU_STR_THL 20

#define	QD604_QDU_STR_TLH 19

#define	QD604_QDU_STR_RQ 18

#define	QD604_QDU_STR_IFE 17

#define	QD604_QDU_STR_IFH 16

#define	QD604_QDU_STR_IFF 15

#define	QD604_QDU_STR_TE 14

#define	QD604_QDU_STR_QE 13

#define	QD604_QDU_STR_GTS 12

#define	QD604_QDU_STR_DIR 11

#define	QD604_QDU_CTR_EN 31

#define	QD604_QDU_CTR_AIE 30

#define	QD604_QDU_CTR_BIE 29

#define	QD604_QDU_CTR_ZIE 28

#define	QD604_QDU_CTR_TIE 27

#define	QD604_QDU_CTR_DO0IE 26

#define	QD604_QDU_CTR_DO1IE 25

#define	QD604_QDU_CTR_CLR 24

#define	QD604_QDU_CTR_TOE 23

#define	QD604_QDU_CTR_TOM2 22

#define	QD604_QDU_CTR_TOM1 21

#define	QD604_QDU_CTR_TOM0 20

#define	QD604_QDU_CTR_COE 19

#define	QD604_QDU_CTR_COM2 18

#define	QD604_QDU_CTR_COM1 17

#define	QD604_QDU_CTR_COM0 16

#define	QD604_QDU_CTR_GTSE 15

#define	QD604_QDU_CTR_GTPE 14

#define	QD604_QDU_CTR_IFE 13

#define	QD604_QDU_CTR_TSM1 12

#define	QD604_QDU_CTR_TSM0 11

#define	QD604_QDU_CCR_EC3 31

#define	QD604_QDU_CCR_EC2 30

#define	QD604_QDU_CCR_EC1 29

#define	QD604_QDU_CCR_EC0 28

#define	QD604_QDU_CCR_CM3 27

#define	QD604_QDU_CCR_CM2 26

#define	QD604_QDU_CCR_CM1 25

#define	QD604_QDU_CCR_CM0 24

#define	QD604_QDU_CCR_TRS 23

#define	QD604_QDU_CCR_ENC 22

#define	QD604_QDU_CCR_TBS2 21

#define	QD604_QDU_CCR_TBS1 20

#define	QD604_QDU_CCR_TBS0 19

#define	QD604_QDU_CCR_CRM2 18

#define	QD604_QDU_CCR_CRM1 17

#define	QD604_QDU_CCR_CRM0 16

#define	QD604_QDU_CCR_ES 15

#define	QD604_QDU_CCR_EB2 14

#define	QD604_QDU_CCR_EB1 13

#define	QD604_QDU_CCR_EB0 12

#define	QD604_QDU_CCR_QEM1 11

#define	QD604_QDU_CCR_QEM0 10

#define	QD604_QDU_CCR_QED 9

#define	QD604_QDU_CCR_QESWAP 8

#define	QD604_QDU_TBR_EN 31

#define	QD604_QDU_IR_CPT 31

#define	QD604_QDU_IR_CR0L 30

#define	QD604_QDU_IR_CR01 29

#define	QD604_QDU_IR_CR1 28

#define	QD604_QDU_IR_LHA 27

#define	QD604_QDU_IR_HLA 26

#define	QD604_QDU_IR_LHB 25

#define	QD604_QDU_IR_HLB 24

#define	QD604_QDU_IR_LHZ 23

#define	QD604_QDU_IR_HLZ 22

#define	QD604_QDU_IR_IFE 21

#define	QD604_QDU_IR_IFH 20

#define	QD604_QDU_IR_IFF 19

#define	QD604_QDU_IR_TE 18

#define	QD604_QDU_IR_QE 17

#define	QD604_QDU_IR_DIR 16

#define	QDU_TOM_CR0L 0

#define	QDU_TOM_CR0E 1

#define	QDU_TOM_GTS 2

#define	QDU_TOM_STD 3

#define	QDU_TOM_DIR 4

#define	QDU_TOM_EM 5

#define	QDU_COM_CR1G 0

#define	QDU_COM_CR1E 1

#define	QDU_COM_1X 2

#define	QDU_COM_2X 3

#define	QDU_COM_4X 4

#define	QDU_COM_IE 5

#define	QDU_COM_N 6

#define	QDU_TSM_NOTS 0

#define	QDU_TSM_TSADD 1

#define	QDU_TSM_TSONLY 2

#define	QDU_EM_CR0 0

#define	QDU_EM_CR1 1

#define	QDU_EM_CR01 2

#define	QDU_EM_IE 3

#define	QDU_EM_TBR 4

#define	QDU_EM_INC 5

#define	QDU_EM_INF 6

#define	QDU_CM_CDU 0

#define	QDU_CM_CDN 1

#define	QDU_CM_DC 2

#define	QDU_CM_QE 3

#define	QDU_CM_TCDU 4

#define	QDU_CM_TCDN 5

#define	QDU_CM_TDC 6

#define	QDU_CM_TQE 7

#define	QDU_CM_RTCDU 8

#define	QDU_CM_RTCDN 9

#define	QDU_CM_RTDC 0xA

#define	QDU_CM_RTQE 0xB

#define	QDU_TBS_66M 0

#define	QDU_TBS_TRIG 1

#define	QDU_TBS_SYNC0 4

#define	QDU_TBS_SYNC1 5

#define	QDU_TBS_SYNC2 6

#define	QDU_TBS_SYNC3 7

#define	QDU_CRM_LR 0

#define	QDU_CRM_CR01 1

#define	QDU_CRM_CR10 2

#define	QDU_CRM_NR 3

#define	QDU_CRM_OTR 4

#define	QDU_TRS_SW 0

#define	QDU_TRS_HW 1

#define	QDU_ES_Z 0

#define	QDU_ES_T 1

#define	QDU_EB_NO 0

#define	QDU_EB_RE 1

#define	QDU_EB_RE_LL 2

#define	QDU_EB_RE_LH 3

#define	QDU_EB_RE_HL 4

#define	QDU_EB_RE_HH 5

#define	QDU_QEM_1X 0

#define	QDU_QEM_2X 1

#define	QDU_QEM_4X 2

#define	DQ_PL_604_NAMELEN 16

#define	DQ_CT_651_CHAN (4)

#define	DQ_CT_651_CHAN_MASK (0x3)

#define	DQ_CT_651_INFOSZ (DQ_MAX_INFO_SIZE)

#define	DQ_CT_651_BASE_66 (66000000)

#define	DQ_CT_651_BASE_100 (100000000)

#define	DQ_CT_651_BASE_160 (160000000)

#define	DQ_LCR651_RXT (1L<<4)

#define	DQ_LCR651_CLK_160MHZ (1L<<2)

#define	DQ_LCR651_CLK_100MHZ (0L<<2)

#define	DQ_LCR651_LED (1L<<1)

#define	DQ_LCR651_DCEN (1L<<0)

#define	DQL_IOCTL651_SET_LCR (1L)

#define	DQL_IOCTL651_SET_FWCFG (3L)

#define	DQL_IOCTL651_SET_DW (4L)

#define	DQL_IOCTL651_SET_FWDC (5L)

#define	DQL_IOCTL651_SET_FWDIV (6L)

#define	DQL_IOCTL651_SET_FWCLK_MIN (7L)

#define	DQL_IOCTL651_SET_FWCLK_MAX (8L)

#define	DQL_IOCTL651_GET_LCR (1L)

#define	DQL_IOCTL651_GET_STS (2L)

#define	DQL_IOCTL651_GET_FWCFG (3L)

#define	DQL_IOCTL651_GET_FWDC (5L)

#define	DQL_IOCTL651_GET_FWDIV (6L)

#define	DQL_IOCTL651_GET_FWCLK_MIN (7L)

#define	DQL_IOCTL651_GET_FWCLK_MAX (8L)

#define	DQL_IOCTL651_GET_FWCRH (9L)

#define	DQL_IOCTL651_GET_FWCRP (10L)

#define	DQL_IOCTL651_GET_FWCNT (11L)

#define	DQ_LCR651_STS_ICF (1L<<2)

#define	DQ_LCR651_DB (1L<<1)

#define	DQ_LCR651_STS_ICIV (1L<<0)

#define	DQ_CT651_DW_C_LD_LDAC (6L<<19)

#define	DQ_CT651_DW_C_RESET (5L<<19)

#define	DQ_CT651_DW_C_PWR_DN (4L<<19)

#define	DQ_CT651_DW_C_WR_UPD_CH (3L<<19)

#define	DQ_CT651_DW_C_WRUPD_ALL (2L<<19)

#define	DQ_CT651_DW_C_UPD_CH (1L<<19)

#define	DQ_CT651_DW_A_ALLAOUTS (7L<<16)

#define	DQ_CT651_DW_A_AOUTD (3L<<16)

#define	DQ_CT651_DW_A_AOUTC (2L<<16)

#define	DQ_CT651_DW_A_AOUTB (1L<<16)

#define	DQ_CT651_DW_A_AOUTA (0L<<16)

#define	DQ_CT651_DW_D_MSB (1L<<15)

#define	DQ_CT651_DW_D_LSB (1L<<0)

#define	DQ_CT651_DW_D_MIDSCALE (0x8000)

#define	DQ_CT651_DW_D_HYST_DEF (0x800)

#define	DQ_CT651_FWCFG_EIH (1L<<19)

#define	DQ_CT651_FWCFG_ACRFW (1L<<18)

#define	DQ_CT651_FWCFG_ACFWDC (1L<<17)

#define	DQ_CT651_FWCFG_ACFWDIV (1L<<16)

#define	DQ_CT651_FWCFG_CH3_M3 (1L<<15)

#define	DQ_CT651_FWCFG_CH3_M0 (1L<<12)

#define	DQ_CT651_FWCFG_CH2_M3 (1L<<11)

#define	DQ_CT651_FWCFG_CH2_M0 (1L<<8)

#define	DQ_CT651_FWCFG_CH1_M3 (1L<<7)

#define	DQ_CT651_FWCFG_CH1_M0 (1L<<4)

#define	DQ_CT651_FWCFG_CH0_M3 (1L<<3)

#define	DQ_CT651_FWCFG_CH0_M0 (1L<<0)

#define	DQ_CT651_FWCFG_CH0 (0)

#define	DQ_CT651_FWCFG_CH1 (4)

#define	DQ_CT651_FWCFG_CH2 (8)

#define	DQ_CT651_FWCFG_CH3 (12)

#define	DQ_CT651_CH_M_DIS_BUF (0)

#define	DQ_CT651_CH_M_FOLLOW (1)

#define	DQ_CT651_CH_M_FLYWHEEL (2)

#define	DQ_CT651_CH_M_AUTO_FOL (3)

#define	DQ_CT651_CH_M_OUT_0 (4)

#define	DQ_CT651_CH_M_OUT_1 (5)

#define	DQ_CT651_CH_M_FOL_DUTY (6)

#define	DQ_CT651_CH_M_AUTO_DUTY (7)

#define	DQ_CT651_CH_M_SYNC_0 (8)

#define	DQ_CT651_CH_M_SYNC_1 (9)

#define	DQ_CT651_CH_M_SYNC_2 (0xa)

#define	DQ_CT651_CH_M_SYNC_3 (0xb)

#define	DQ_CT651_CH_MODE_MASK (0xf)

#define	DQ_CT651_FWDC_D31 (1L<<31)

#define	DQ_CT651_FWDC_D0 (1L<<0)

#define	DQ_CT651_FWDIV_D31 (1L<<31)

#define	DQ_CT651_FWDIV_D0 (1L<<0)

#define	DQ_CT651_FWCLK_MIN_D31 (1L<<31)

#define	DQ_CT651_FWCLK_MIN_D0 (1L<<0)

#define	DQ_CT651_FWCLK_MAX_D31 (1L<<31)

#define	DQ_CT651_FWCLK_MAX_D0 (1L<<0)

#define	DQ_CT651_FWCRH_STOP (1L<<31)

#define	DQ_CT651_FWCRH_D30 (1L<<30)

#define	DQ_CT651_FWCRH_D0 (1L<<0)

#define	DQ_CT651_FWCRP_STOP (1L<<31)

#define	DQ_CT651_FWCRP_D31 (1L<<30)

#define	DQ_CT651_FWCRP_D0 (1L<<0)

#define	DQ_CT651_FWCNT_D31 (1L<<31)

#define	DQ_CT651_FWCNT_D0 (1L<<0)

#define	DQ_L651_NAMELEN (32)

#define	L8000_INFOSZ DQ_MAX_INFO_SIZE

#define	L8000_MODEL 0x8000

#define	L8000_OPTION 0x1

#define	L8000_SERNUM 0x8021234

#define	_CAPS_8000_

#define	L8000_TIMER 0

#define	L8000_CPUTMR_MASTER 1

#define	L8000_CPUTMR_SLAVE 2

#define	L8000_CPUTMR_START 3

#define	L8000_CPUTMR_STOP 4

#define	L8000_CPUTMR_DISABLE 5

#define	DQMAXTRL (DQ_MAXDEVN * DQ_MAXSS)

#define	DQMAXCHNLS (32)

#define	DQ_VDD_DMAPID_IN DQ_DMAP_LASTID_IN

#define	DQ_VDD_DMAPID_OUT DQ_DMAP_LASTID_OUT

#define	DQ_VDD_SS (2)

#define	MPC5200_GPT_100US_PS (6600)

#define	MPC5200_GPT_10US_PS (660)

#define	MPC5200_GPT_1US_PS (66)

#define	DQIOCTL_VDD_SETTRL (0x21)

#define	DQIOCTL_VDD_FINISHTRL (0x22)

#define	DQIOCTL_VDD_CONFIG (0x23)

#define	DQIOCTL_VDD_SETTMRSRC (0x24)

#define	DQ_PL_801_CHAN 4

#define	DQ_PL_801_CHANSVC 4

#define	DQ_PL_801_INFOSZ DQ_MAX_INFO_SIZE

#define	DQ_PL_801_BASE BUS_FREQUENCY

#define	DQ_PL_801_MAXCLFRQ 50000

#define	DQ_PL_801_MAXCVFRQ 50000

#define	DQ_PL801_CHNLMASK (0xf0)

#define	DQ_PL801_MSGNORM (0)

#define	DQ_PL801_SW8 (1L)

#define	DQ_PL801_SW16 (2L)

#define	DQ_PL801_SW32 (4L)

#define	DQ_CDS_STR 0x00

#define	DQ_CDS_CTR 0x00

#define	DQ_CDS_IFWR 0x0C

#define	DQ_CDS_OFWR 0x10

#define	DQ_CDS_FDTI 0x14

#define	DQ_CDS_FDTO 0x18

#define	DQ_CDS_FCNTI 0x1C

#define	DQ_CDS_FCNTO 0x20

#define	DQ_COM_CNT 0x24

#define	DQ_COM_DATA 0x28

#define	DQ_COM_TS 0x2C

#define	DQ_CDU_START_MASK 0x001FFBFE

#define	DQ_CDU_STOP_MASK 0x00200400

#define	DQ_FGC_MSGSIZE 8

#define	DQ_CDU_MSGSIZE 1

#define	DQL_IOCTL801_START (0x0AL)

#define	DQL_IOCTL801_SETCHNL_CFG (1L)

#define	DQL_IOCTL801_SET_REG (2L)

#define	DQL_IOCTL801_GET_REG (3L)

#define	DQL_IOCTL801_SET_LCR (4L)

#define	DQL_IOCTL801_GET_LCR (5L)

#define	DQL_IOCTL801_SET_WM (11L)

#define	DQ_L801_FIFOSZ 256

#define	DQ_CLI_CDS0S 0x2000

#define	DQ_CR801_TXF 0x20000

#define	DQ_CR801_RXF 0x10000

#define	DQ_CR801_LB 0x00010

#define	DQ_CR801_TS 0x00008

#define	DQ_CR801_OED 0x00004

#define	DQ_CR801_OES 0x00002

#define	DQ_CR801_OEC 0x00001

#define	DQ_PL_801_MODESCAN (0L << 16)

#define	DQ_PL_801_MODEFIFO (2L << 16)

#define	DQ_PL_801_MODECONT (3L << 16)

#define	DQ_PL_801_TSCOPY (1L << 18)

#define	DQ_PL_801_FIFO_GET_DATA DQ_FIFO_GET_DATA

#define	DQ_PL_801_NAMELEN 16

#define	DQ_PL_802_CHAN 4

#define	DQ_PL_802_CHANSVC 4

#define	DQ_PL_802_INFOSZ DQ_MAX_INFO_SIZE

#define	DQ_PL_802_BASE BUS_FREQUENCY

#define	DQ_PL_802_MAXCLFRQ 50000

#define	DQ_PL_802_MAXCVFRQ 50000

#define	DQ_PL802_CHNLMASK (0xf0)

#define	DQ_PL802_MSGNORM (0)

#define	DQ_PL802_SW8 (1L)

#define	DQ_PL802_SW16 (2L)

#define	DQ_PL802_SW32 (4L)

#define	DQ_MAN_STR 0x00

#define	DQ_MAN_CTR 0x00

#define	DQ_MAN_IFWR 0x0C

#define	DQ_MAN_OFWR 0x10

#define	DQ_MAN_FDTI 0x14

#define	DQ_MAN_FDTO 0x18

#define	DQ_MAN_FCNTI 0x1C

#define	DQ_MAN_FCNTO 0x20

#define	DQ_MAN_MSGSIZE 256

#define	DQL_IOCTL802_START (0x0AL)

#define	DQL_IOCTL802_SETCHNL_CFG (1L)

#define	DQL_IOCTL802_SET_REG (2L)

#define	DQL_IOCTL802_GET_REG (3L)

#define	DQL_IOCTL802_SET_LCR (4L)

#define	DQL_IOCTL802_GET_LCR (5L)

#define	DQL_IOCTL802_SET_WM (11L)

#define	DQ_L802_FIFOSZ 256

#define	DQ_CLI_MANSS 0x2100

#define	DQ_CR802_TXF 0x20000

#define	DQ_CR802_RXF 0x10000

#define	DQ_CR802_LB 0x00010

#define	DQ_CR802_RAW 0x00008

#define	DQ_CR802_PRIMUS 0x00004

#define	DQ_PL_802_MODESCAN (0L << 16)

#define	DQ_PL_802_MODEFIFO (2L << 16)

#define	DQ_PL_802_MODECONT (3L << 16)

#define	DQ_PL_802_TSCOPY (1L << 18)

#define	DQ_PL_802_FIFO_GET_DATA DQ_FIFO_GET_DATA

#define	DQ_PL_802_NAMELEN 16

#define	DQ_L90x_CHAN 2

#define	DQ_L90x_INFOSZ DQ_MAX_INFO_SIZE

#define	DQ_L90x_BASE 66000000

#define	DQ_L90x_NAMELEN 32

#define	DQ_PC_91x_OCHAN (2)

#define	DQ_PC_91x_ICHAN (5)

#define	DQ_PC_91x_CL_MASK (0x7)

#define	DQ_PC_91x_INFOSZ (DQ_MAX_INFO_SIZE)

#define	DQ_PC_91x_BASE (66000000)

#define	DQ_PC91X_AI_SPAN (2.5)

#define	DQ_PC91X_OFFSET (DQ_PC91X_AI_SPAN/2.0)

#define	DQ_PC91X_STEP (DQ_PC91X_AI_SPAN/(double)0xffff)

#define	DQ_PC91X_V_SCALER (42.667)

#define	DQ_PC91X_I_SCALER_TH (165.0)

#define	DQ_PC91X_I_SCALER_INT (61.5)

#define	DQ_PC91X_I_SCALER_EXT (83.5)

#define	DQ_PC91X_T_SLOPE (2.45)

#define	DQ_PC91X_T_OFFSET (273.0)

#define	DQ_PC91X_DEF_OFFSET_CAL (0)

#define	DQ_PC91X_MAX_OFFSET_CAL_DEV (0x1000)

#define	DQ_PC91X_DEF_GAIN_CAL (0x8000)

#define	DQ_PC91X_MAX_GAIN_CAL_DEV (3277)

#define	DQ_PC91X_MIN_ADC_WAIT (160)

#define	DQ_PC91X_ADC_EOC (1L<<18)

#define	DQ_PC91X_ADC_SIG (1L<<16)

#define	DQ_PC91X_ADC_MSB (1L<<15)

#define	DQ_PC91X_CH_EXT_V (0)

#define	DQ_PC91X_CH_INPUT_I (1)

#define	DQ_PC91X_CH_INT_V (2)

#define	DQ_PC91X_CH_DCDC_INPUT_V (3)

#define	DQ_PC91X_CH_THERM (4)

#define	DQ_91X_STS_JMAIN_ON (1L<<2)

#define	DQ_91X_STS_JIO_ON (1L<<1)

#define	DQ_91X_STS_JIO (1L<<0)

#define	DQ_PC_91X_CFG_EJIO (1L<<31)

#define	DQ_91X_CFG_DCEN3 (1L<<30)

#define	DQ_91X_CFG_DCEN2 (1L<<29)

#define	DQ_91X_CFG_DCEN1 (1L<<28)

#define	DQ_PC_91X_CFG_AUTO (1L<<27)

#define	DQ_91X_POWER_OFF (0)

#define	DQ_911_P5_N5_12W (DQ_91X_CFG_DCEN2)

#define	DQ_911_P10_N10_24W (DQ_91X_CFG_DCEN1+DQ_91X_CFG_DCEN3)

#define	DQ_911_P15_N15_36W (DQ_91X_CFG_DCEN1+DQ_91X_CFG_DCEN2+DQ_91X_CFG_DCEN3)

#define	DQ_911_P15_N5_24W (DQ_91X_CFG_DCEN1+DQ_91X_CFG_DCEN2)

#define	DQ_911_P5_N15_24W (DQ_91X_CFG_DCEN2+DQ_91X_CFG_DCEN3)

#define	DQ_912_P12_20W (DQ_91X_CFG_DCEN1)

#define	DQ_912_P24_40W (DQ_91X_CFG_DCEN1+DQ_91X_CFG_DCEN3)

#define	DQ_913_P15_N15_12W (DQ_91X_CFG_DCEN2)

#define	DQ_913_P30_N30_24W (DQ_91X_CFG_DCEN1+DQ_91X_CFG_DCEN3)

#define	DQ_913_P45_N45_36W (DQ_91X_CFG_DCEN1+DQ_91X_CFG_DCEN2+DQ_91X_CFG_DCEN3)

#define	DQ_913_P45_N15_24W (DQ_91X_CFG_DCEN1+DQ_91X_CFG_DCEN2)

#define	DQ_913_P15_N45_24W (DQ_91X_CFG_DCEN2+DQ_91X_CFG_DCEN3)

#define	DQ_91X_INTERNAL_POWER (0)

#define	DQ_91X_EXT_JIO_POWER (DQ_PC_91X_CFG_EJIO)

#define	DQ_91X_EXT_JIO_AUTOSWITCH (DQ_PC_91X_CFG_EJIO+DQ_PC_91X_CFG_AUTO)

#define	DQ_L91x_NAMELEN (32)

#define	DQ_LAYER_CHAN 4

#define	DQ_LAYER_CALDACS 4

#define	DQ_LAYER_NAMELEN 20

Typedefs
typedef struct _SIGS	SGNLS

typedef struct _SIGS *	pSGNLS

typedef struct _SYNCPAL	SYNCPLL

typedef struct _SYNCPAL *	pSYNCPLL

typedef struct _SYNCRT	SYNCRT

typedef struct _SYNCRT *	pSYNCRT

typedef struct DQPKT	DQPKT

typedef struct DQPKT *	pDQPKT

typedef struct wDQPKT *	pwDQPKT

typedef struct dwDQPKT *	pdwDQPKT

typedef struct DQRDCFG *	pDQRDCFG

typedef struct DQWRVALM *	pDQWRVALM

typedef struct wDQRDVALM *	pwDQRDVALM

typedef struct wDQWRVALM *	pwDQWRVALM

typedef struct dwDQWRVALM *	pdwDQWRVALM

typedef struct DQSETCFG *	pDQSETCFG

typedef struct DQEVENT *	pDQEVENT

typedef struct DQAXMAP *	pDQAXMAP

typedef struct DQGETCFG *	pDQGETCFG

typedef struct DQGETCFG_RQ *	pDQGETCFG_RQ

typedef struct DQWRCHNL *	pDQWRCHNL

typedef struct DQCHNL *	pDQCHNL

typedef struct DQRDCHNL *	pDQRDCHNL

typedef struct DQSETCLK *	pDQSETCLK

typedef struct DQSETCL *	pDQSETCL

typedef struct DQSETTRL *	pDQSETTRL

typedef struct DQSETTRIG *	pDQSETTRIG

typedef struct DQWRRD *	pDQWRRD

typedef struct DQFIFO *	pDQFIFO

typedef struct DQWRRDFIFO *	pDQWRRDFIFO

typedef struct DQCRCINFO *	pDQCRCINFO

typedef struct DQSETCOMM *	pDQSETCOMM

typedef struct DQSETPRM *	pDQSETPRM

typedef struct DQSETPRM	DQGETPRM

typedef struct DQSETPRM *	pDQGETPRM

typedef struct DQSETCAL *	pDQSETCAL

typedef struct DQIOCTL *	pDQIOCTL

typedef struct DQBURST *	pDQBURST

typedef struct DQCLRMEM *	pDQCLRMEM

typedef struct DQRBF *	pDQRBF

typedef struct DQRBFDEV *	pDQRBFDEV

typedef struct NBUFSTR *	pNBUFSTR

typedef struct HW_TEST_DATA *	pHW_TEST_DATA

typedef struct DQEECMNDEVS *	pDQEECMNDEVS

typedef struct DQPRMFLAGS *	pDQPRMFLAGS

typedef struct SIMA_MSG_CTRL_STATUS *	pSIMA_MSG_CTRL_STATUS

typedef struct DQCNAMES_104 *	pDQCNAMES_104

typedef struct DQCALSET_104 *	pDQCALSET_104

typedef struct DQOPMODEPRM_104 *	pDQOPMODEPRM_104

typedef struct DQCNAMES_2000_ *	pDQCNAMES_2000_

typedef struct DQCALSET_2000_ *	pDQCALSET_2000_

typedef struct DQOPMODEPRM_2000_ *	pDQOPMODEPRM_2000_

typedef struct DQINITPRM_2000_ *	pDQINITPRM_2000_

typedef struct DQSDOWNPRM_2000_ *	pDQSDOWNPRM_2000_

typedef struct DEVEEPROM_2000_ *	pDEVEEPROM_2000_

typedef struct DQCNAMES_201_ *	pDQCNAMES_201_

typedef struct DQCALSET_201_ *	pDQCALSET_201_

typedef struct DQOPMODEPRM_201_ *	pDQOPMODEPRM_201_

typedef struct DEVEEPROM_201_ *	pDEVEEPROM_201_

typedef struct DQCNAMES_205_ *	pDQCNAMES_205_

typedef struct DQCALSET_205_ *	pDQCALSET_205_

typedef struct DQOPMODEPRM_205_ *	pDQOPMODEPRM_205_

typedef struct DEVEEPROM_205_ *	pDEVEEPROM_205_

typedef struct DQCNAMES_208_ *	pDQCNAMES_208_

typedef struct DQCNAMES_207_ *	pDQCNAMES_207_

typedef struct DQCALSET_208_ *	pDQCALSET_208_

typedef struct DQOPMODEPRM_208_ *	pDQOPMODEPRM_208_

typedef struct DEVEEPROM_208_ *	pDEVEEPROM_208_

typedef struct DQCFGCH_211 *	pDQCFGCH_211

typedef struct DQCFGLAYER_211 *	pDQCFGLAYER_211

typedef struct DQCNAMES_211_ *	pDQCNAMES_211_

typedef struct CAL_DAC_SET_211 *	pCAL_DAC_SET_211

typedef struct DQCALSET_211_ *	pDQCALSET_211_

typedef struct CAL_DAC_SET_EXT_211 *	pCAL_DAC_SET_EXT_211

typedef struct DQCALSET_EXT_AFON_211_ *	pDQCALSET_EXT_AFON_211_

typedef struct DQCALSET_EXT_AFOFF_211_ *	pDQCALSET_EXT_AFOFF_211_

typedef struct DQOPMODEPRM_211_ *	pDQOPMODEPRM_211_

typedef struct DEVEEPROM_211_ *	pDEVEEPROM_211_

typedef struct DQCNAMES_217_ *	pDQCNAMES_217_

typedef struct CAL_DAC_SET_217 *	pCAL_DAC_SET_217

typedef struct DQCALSET_217_ *	pDQCALSET_217_

typedef struct DQCALSET_217_X *	pDQCALSET_217_X

typedef struct DQOPMODEPRM_217_ *	pDQOPMODEPRM_217_

typedef struct DEVEEPROM_217_ *	pDEVEEPROM_217_

typedef struct DQCNAMES_224_ *	pDQCNAMES_224_

typedef struct DQCALSET_224_ *	pDQCALSET_224_

typedef struct DQOPMODEPRM_224_ *	pDQOPMODEPRM_224_

typedef struct DEVEEPROM_224_ *	pDEVEEPROM_224_

typedef struct DQAI225CALDATA *	pDQAI225CALDATA

typedef struct DQCNAMES_225_ *	pDQCNAMES_225_

typedef struct DQCALSET_225_ *	pDQCALSET_225_

typedef struct DQOPMODEPRM_225_ *	pDQOPMODEPRM_225_

typedef struct DEVEEPROM_225_ *	pDEVEEPROM_225_

typedef struct DQ254SetExt *	pDQ254SetExt

typedef struct DQCNAMES_254_ *	pDQCNAMES_254_

typedef struct DQCALCHAN_254_ *	pDQCALCHAN_254_

typedef struct DQCALSET_254_ *	pDQCALSET_254_

typedef struct DQOPMODEPRM_254_ *	pDQOPMODEPRM_254_

typedef struct DEVEEPROM_254_ *	pDEVEEPROM_254_

typedef struct WFPRM_254 *	pWFPRM_254

typedef struct WFMEASURE_254 *	pWFMEASURE_254

typedef struct DQ255SetExt *	pDQ255SetExt

typedef struct DQCNAMES_255_ *	pDQCNAMES_255_

typedef struct DQCALCHAN_255_ *	pDQCALCHAN_255_

typedef struct DQCALSET_255_ *	pDQCALSET_255_

typedef struct DQOPMODEPRM_255_ *	pDQOPMODEPRM_255_

typedef struct DEVEEPROM_255_ *	pDEVEEPROM_255_

typedef struct WFPRM_255 *	pWFPRM_255

typedef struct WFMEASURE_255 *	pWFMEASURE_255

typedef struct DQCNAMES_301_ *	pDQCNAMES_301_

typedef struct DQCALSET_301_ *	pDQCALSET_301_

typedef struct DQOPMODEPRM_301_ *	pDQOPMODEPRM_301_

typedef struct DQINITPRM_301_ *	pDQINITPRM_301_

typedef struct DQSDOWNPRM_301_ *	pDQSDOWNPRM_301_

typedef struct DEVEEPROM_301_ *	pDEVEEPROM_301_

typedef struct DQCNAMES_332_ *	pDQCNAMES_332_

typedef struct DQCALSET_332_ *	pDQCALSET_332_

typedef struct DQCALSET_333_ *	pDQCALSET_333_

typedef struct DQOPMODEPRM_332_ *	pDQOPMODEPRM_332_

typedef struct DQINITPRM_332_ *	pDQINITPRM_332_

typedef struct DQSDOWNPRM_332_ *	pDQSDOWNPRM_332_

typedef struct DEVEEPROM_332_ *	pDEVEEPROM_332_

typedef struct DQCNAMES_358_ *	pDQCNAMES_358_

typedef struct DQCALSET_358_ *	pDQCALSET_358_

typedef struct DQOPMODEPRM_358_ *	pDQOPMODEPRM_358_

typedef struct DQINITPRM_358_ *	pDQINITPRM_358_

typedef struct DQSDOWNPRM_358_ *	pDQSDOWNPRM_358_

typedef struct DEVEEPROM_358_ *	pDEVEEPROM_358_

typedef struct DQ_358CAL_HEAD *	pDQ_358CAL_HEAD

typedef struct DQEXCAL_358 *	pDQEXCAL_358

typedef struct DQEXCAL_358_8 *	pDQEXCAL_358_8

typedef struct EV401_ID *	pEV401_ID

typedef struct DQCNAMES_401_ *	pDQCNAMES_401_

typedef struct DQOPMODEPRM_401_ *	pDQOPMODEPRM_401_

typedef struct DQINITPRM_401_ *	pDQINITPRM_401_

typedef struct DQSDOWNPRM_401_ *	pDQSDOWNPRM_401_

typedef struct DEVEEPROM_401_ *	pDEVEEPROM_401_

typedef struct DQCNAMES_403_ *	pDQCNAMES_403_

typedef struct DQOPMODEPRM_403_ *	pDQOPMODEPRM_403_

typedef struct DQINITPRM_403_ *	pDQINITPRM_403_

typedef struct DQSDOWNPRM_403_ *	pDQSDOWNPRM_403_

typedef struct DEVEEPROM_403_ *	pDEVEEPROM_403_

typedef struct DQCNAMES_448_ *	pDQCNAMES_448_

typedef struct DQOPMODEPRM_448_ *	pDQOPMODEPRM_448_

typedef struct DQINITPRM_448_ *	pDQINITPRM_448_

typedef struct DQCALSET_448_ *	pDQCALSET_448_

typedef struct DEVEEPROM_448_ *	pDEVEEPROM_448_

typedef struct DQDIO448DATAOUT *	pDQDIO448DATAOUT

typedef struct DQCNAMES_416_ *	pDQCNAMES_416_

typedef struct DQCNAMES_432_ *	pDQCNAMES_432_

typedef struct DQCALSET_416_ *	pDQCALSET_416_

typedef struct DQCALSET_432_ *	pDQCALSET_432_

typedef struct DQOPMODEPRM_416_ *	pDQOPMODEPRM_416_

typedef struct DQOPMODEPRM_432_ *	pDQOPMODEPRM_432_

typedef struct DQINITPRM_416_ *	pDQINITPRM_416_

typedef struct DQSDOWNPRM_416_ *	pDQSDOWNPRM_416_

typedef struct DQINITPRM_432_ *	pDQINITPRM_432_

typedef struct DQSDOWNPRM_432_ *	pDQSDOWNPRM_432_

typedef struct DEVEEPROM_416_ *	pDEVEEPROM_416_

typedef struct DEVEEPROM_432_ *	pDEVEEPROM_432_

typedef struct DQDIO416DATAIN *	pDQDIO416DATAIN

typedef struct DQDIO416DATAOUT *	pDQDIO416DATAOUT

typedef struct DQDIO432DATAIN *	pDQDIO432DATAIN

typedef struct DQDIO432PWM *	pDQDIO432PWM

typedef struct DQDIO432CVTD *	pDQDIO432CVTD

typedef struct DQDIO432DATAOUT *	pDQDIO432DATAOUT

typedef struct DQCNAMES_462_ *	pDQCNAMES_462_

typedef struct DQCALSET_462_ *	pDQCALSET_462_

typedef struct DQOPMODEPRM_462_ *	pDQOPMODEPRM_462_

typedef struct DQINITPRM_462_ *	pDQINITPRM_462_

typedef struct DQSDOWNPRM_462_ *	pDQSDOWNPRM_462_

typedef struct DEVEEPROM_462_ *	pDEVEEPROM_462_

typedef struct DQDIO462DATAIN *	pDQDIO462DATAIN

typedef struct DQDIO462DATAOUT *	pDQDIO462DATAOUT

typedef struct DQMSG_501 *	pDQMSG_501

typedef struct DQMSG_501_L *	pDQMSG_501_L

typedef struct EV501_ID *	pEV501_ID

typedef struct DQCNAMES_501_ *	pDQCNAMES_501_

typedef struct DQCNAMES_508_ *	pDQCNAMES_508_

typedef struct DQOPMODEPRM_501_ *	pDQOPMODEPRM_501_

typedef struct DQINITPRM_501_ *	pDQINITPRM_501_

typedef struct DQSDOWNPRM_501_ *	pDQSDOWNPRM_501_

typedef struct DEVEEPROM_501_ *	pDEVEEPROM_501_

typedef struct DQCNAMES_503_ *	pDQCNAMES_503_

typedef struct DQCHNLSET_503_ *	pDQCHNLSET_503_

typedef struct DQOPMODEPRM_503_ *	pDQOPMODEPRM_503_

typedef struct DQINITPRM_503_ *	pDQINITPRM_503_

typedef struct DQSDOWNPRM_503_ *	pDQSDOWNPRM_503_

typedef struct DEVEEPROM_503_ *	pDEVEEPROM_503_

typedef struct DQCNAMES_504_ *	pDQCNAMES_504_

typedef struct DQOPMODEPRM_504_ *	pDQOPMODEPRM_504_

typedef struct DQINITPRM_504_ *	pDQINITPRM_504_

typedef struct DQSDOWNPRM_504_ *	pDQSDOWNPRM_504_

typedef struct DEVEEPROM_504_ *	pDEVEEPROM_504_

typedef struct DQCNAMES_550_ *	pDQCNAMES_550_

typedef struct DQOPMODEPRM_550_ *	pDQOPMODEPRM_550_

typedef struct DQINITPRM_550_ *	pDQINITPRM_550_

typedef struct DQSDOWNPRM_550_ *	pDQSDOWNPRM_550_

typedef struct DQ553Control *	pDQ553Control

typedef struct BCCB_Control *	pBCCB_Control

typedef struct BCCB_Status *	pBCCB_Status

typedef struct BCCB_Block *	pBCCB_Block

typedef struct DQBM553Message *	pDQBM553Message

typedef struct DQBM553MessageStor *	pDQBM553MessageStor

typedef struct DQBM553RTSAEntry *	pDQBM553RTSAEntry

typedef struct DQBM553Filter *	pDQBM553Filter

typedef struct DQBM553Trigger *	pDQBM553Trigger

typedef struct EV553_ID *	pEV553_ID

typedef struct DQCNAMES_553_ *	pDQCNAMES_553_

typedef struct DQOPMODEPRM_553_ *	pDQOPMODEPRM_553_

typedef struct DQINITPRM_553_ *	pDQINITPRM_553_

typedef struct DQSDOWNPRM_553_ *	pDQSDOWNPRM_553_

typedef struct DEVEEPROM_553_ *	pDEVEEPROM_553_

typedef enum _tSL553CommandType	tSL553CommandType

typedef struct SL553CUST_LUT *	pSL553CUST_LUT

typedef struct DQMSG_566 *	pDQMSG_566

typedef struct DQMSG_566_L *	pDQMSG_566_L

typedef struct DQCNAMES_566_ *	pDQCNAMES_566_

typedef struct DQOPMODEPRM_566_ *	pDQOPMODEPRM_566_

typedef struct DQINITPRM_566_ *	pDQINITPRM_566_

typedef struct DQSDOWNPRM_566_ *	pDQSDOWNPRM_566_

typedef struct DEVEEPROM_566_ *	pDEVEEPROM_566_

typedef struct EV601_ID *	pEV601_ID

typedef struct DQCNAMES_601_ *	pDQCNAMES_601_

typedef struct DQCALSET_601_ *	pDQCALSET_601_

typedef struct DQOPMODEPRM_601_ *	pDQOPMODEPRM_601_

typedef struct DEVEEPROM_601_ *	pDEVEEPROM_601_

typedef struct DQCHNLSET_601_ *	pDQCHNLSET_601_

typedef struct DQWMSET_601_ *	pDQWMSET_601_

typedef struct DQMSG_601 *	pDQMSG_601

typedef struct DQMSG_601_L *	pDQMSG_601_L

typedef struct DQCNAMES_604_ *	pDQCNAMES_604_

typedef struct DQCALSET_604_ *	pDQCALSET_604_

typedef struct DQOPMODEPRM_604_ *	pDQOPMODEPRM_604_

typedef struct DEVEEPROM_604_ *	pDEVEEPROM_604_

typedef struct DQCHNLSET_604_ *	pDQCHNLSET_604_

typedef struct DQMSG_604 *	pDQMSG_604

typedef struct DQCNAMES_651_ *	pDQCNAMES_651_

typedef struct DQCALSET_651_ *	pDQCALSET_651_

typedef struct DQINITPRM_651_ *	pDQINITPRM_651_

typedef struct DQOPMODEPRM_651_ *	pDQOPMODEPRM_651_

typedef struct DQSDOWNPRM_651_ *	pDQSDOWNPRM_651_

typedef struct DQPRMFLAGS_651_ *	pDQPRMFLAGS_651_

typedef struct DQCNAMES_801_ *	pDQCNAMES_801_

typedef struct DQCALSET_801_ *	pDQCALSET_801_

typedef struct DQOPMODEPRM_801_ *	pDQOPMODEPRM_801_

typedef struct DEVEEPROM_801_ *	pDEVEEPROM_801_

typedef struct DQCHNLSET_801_ *	pDQCHNLSET_801_

typedef struct DQWMSET_801_ *	pDQWMSET_801_

typedef struct DQMSG_801 *	pDQMSG_801

typedef struct DQFGC *	pDQFGC

typedef struct DQCDU *	pDQCDU

typedef struct DQCNAMES_802_ *	pDQCNAMES_802_

typedef struct DQCALSET_802_ *	pDQCALSET_802_

typedef struct DQOPMODEPRM_802_ *	pDQOPMODEPRM_802_

typedef struct DEVEEPROM_802_ *	pDEVEEPROM_802_

typedef struct DQCHNLSET_802_ *	pDQCHNLSET_802_

typedef struct DQWMSET_802_ *	pDQWMSET_802_

typedef struct DQMSG_802 *	pDQMSG_802

typedef struct DQMAN *	pDQMAN

typedef struct DQCNAMES_90x_ *	pDQCNAMES_90x_

typedef struct DQOPMODEPRM_90x_ *	pDQOPMODEPRM_90x_

typedef struct DQINITPRM_90x_ *	pDQINITPRM_90x_

typedef struct DQSDOWNPRM_90x_ *	pDQSDOWNPRM_90x_

typedef struct DQCNAMES_91x_ *	pDQCNAMES_91x_

typedef struct DQCALSET_91x_ *	pDQCALSET_91x_

typedef struct DQINITPRM_91x_ *	pDQINITPRM_91x_

typedef struct DQOPMODEPRM_91x_ *	pDQOPMODEPRM_91x_

typedef struct DQSDOWNPRM_91x_ *	pDQSDOWNPRM_91x_

typedef struct DQPRMFLAGS_91x_ *	pDQPRMFLAGS_91x_

typedef struct DQCNAMES_LAYER_ *	pDQCNAMES_LAYER_

typedef struct DQCALSET_LAYER_ *	pDQCALSET_LAYER_

typedef struct DQOPMODEPRM_LAYER_ *	pDQOPMODEPRM_LAYER_

Enumerations
enum	event401_t { EV401_CLEAR = 0x1000, EV401_DI_CHANGE = 0x101, EV401_CLEAR = 0x1000, EV401_DI_CHANGE = 0x101, EV401_CLEAR = 0x1000, EV401_DI_CHANGE = 0x101 }

enum	event501_t { EV501_CLEAR = 0x1000, EV501_TO = 0x101, EV501_IN_FIFO, EV501_RX, EV501_OUT_FIFO, EV501_TX, EV501_BUS_ERROR, EV501_CLEAR = 0x1000, EV501_TO = 0x101, EV501_IN_FIFO, EV501_RX, EV501_OUT_FIFO, EV501_TX, EV501_BUS_ERROR, EV501_CLEAR = 0x1000, EV501_TO = 0x101, EV501_IN_FIFO, EV501_RX, EV501_OUT_FIFO, EV501_TX, EV501_BUS_ERROR }

enum	event553_t { EV553_CLEAR = 0x1000, EV553_NO_ACTIVITY = 0x101, EV553_IN_FIFO, EV553_OUT_FIFO, EV553_BUS_ERROR, EV553_FSM_ERROR, EV553_BUS_CHANGED, EV553_MD_SHUTDOWN, EV553_MD_SYNCHRONIZE, EV553_MD_RESET, EV553_MD_MISC, EV553_RX, EV553_TX, EV553_BCST_RX, EV553_BCST_TX, EV553_MD, EV553_BC_ERROR, EV553_BC_BUS, EV553_BC_IRQ, EV553_BC_OVERRUN, EV553_BC_CMD_ERR, EV553_BC_HEARTBEAT, EV553_RT_CUST_LUT, EV553_CLEAR = 0x1000, EV553_NO_ACTIVITY = 0x101, EV553_IN_FIFO, EV553_OUT_FIFO, EV553_BUS_ERROR, EV553_FSM_ERROR, EV553_BUS_CHANGED, EV553_MD_SHUTDOWN, EV553_MD_SYNCHRONIZE, EV553_MD_RESET, EV553_MD_MISC, EV553_RX, EV553_TX, EV553_BCST_RX, EV553_BCST_TX, EV553_MD, EV553_BC_ERROR, EV553_BC_BUS, EV553_BC_IRQ, EV553_BC_OVERRUN, EV553_BC_CMD_ERR, EV553_BC_HEARTBEAT, EV553_RT_CUST_LUT, EV553_CLEAR = 0x1000, EV553_NO_ACTIVITY = 0x101, EV553_IN_FIFO, EV553_OUT_FIFO, EV553_BUS_ERROR, EV553_FSM_ERROR, EV553_BUS_CHANGED, EV553_MD_SHUTDOWN, EV553_MD_SYNCHRONIZE, EV553_MD_RESET, EV553_MD_MISC, EV553_RX, EV553_TX, EV553_BCST_RX, EV553_BCST_TX, EV553_MD, EV553_BC_ERROR, EV553_BC_BUS, EV553_BC_IRQ, EV553_BC_OVERRUN, EV553_BC_CMD_ERR, EV553_BC_HEARTBEAT, EV553_RT_CUST_LUT }

enum	_tSL553CommandType { SL553CmdBCRT, SL553CmdRTBC, SL553CmdRTRT, SL553CmdModeTxNoData, SL553CmdModeTxWithData, SL553CmdModeRxWithData, SL553CmdBCRTBroadcast, SL553CmdRTRTBroadcast, SL553CmdModeTxNoDataBroadcast, SL553CmdModeRxWithDataBroadcast, SL553CmdBCRT, SL553CmdRTBC, SL553CmdRTRT, SL553CmdModeTxNoData, SL553CmdModeTxWithData, SL553CmdModeRxWithData, SL553CmdBCRTBroadcast, SL553CmdRTRTBroadcast, SL553CmdModeTxNoDataBroadcast, SL553CmdModeRxWithDataBroadcast, SL553CmdBCRT, SL553CmdRTBC, SL553CmdRTRT, SL553CmdModeTxNoData, SL553CmdModeTxWithData, SL553CmdModeRxWithData, SL553CmdBCRTBroadcast, SL553CmdRTRTBroadcast, SL553CmdModeTxNoDataBroadcast, SL553CmdModeRxWithDataBroadcast }

enum	event601_t { EV601_CLEAR = 0x100, EV601_COUNT_COMPLETE, EV601_CR0_LESSTHEN, EV601_CR0_EXCEEDED, EV601_CR1_EXCEEDED, EV601_DATA_AVAILABLE, EV601_INP_TRANSITION, EV601_GATE_TRANSITION, EV601_CLEAR = 0x100, EV601_COUNT_COMPLETE, EV601_CR0_LESSTHEN, EV601_CR0_EXCEEDED, EV601_CR1_EXCEEDED, EV601_DATA_AVAILABLE, EV601_INP_TRANSITION, EV601_GATE_TRANSITION, EV601_CLEAR = 0x100, EV601_COUNT_COMPLETE, EV601_CR0_LESSTHEN, EV601_CR0_EXCEEDED, EV601_CR1_EXCEEDED, EV601_DATA_AVAILABLE, EV601_INP_TRANSITION, EV601_GATE_TRANSITION }

Macro Definition Documentation

◆ _CAPS_553_

#define _CAPS_553_

Value:

"NumberSS=1\n" \
"SS0.Type=1553\n" \
"SS0.Chnls=2\n" \
"SS0.NameLen=32\n" \
"SS0.Dir=In\n" \
"SS0.Res=0\n" \
"SS0.Coding=1\n" \
"SS0.Align=0\n" \
"SS0.MinRate=1\n" \
"SS0.MaxRate=25000\n" \
"SS0.Muxed=0\n"

◆ _CAPS_8000_

#define _CAPS_8000_

Value:

"NumberSS=1\n" \
"SS0.Type=SL\n" \
"SS0.Chnls=1\n"

◆ AI205_DEFDCR

#define AI205_DEFDCR (0)

◆ AI205_DEFTAPS

#define AI205_DEFTAPS (128)

◆ AI205_FIR_DECRAT_ONLY

#define AI205_FIR_DECRAT_ONLY (2)

◆ AI205_FIR_DEFAULT

#define AI205_FIR_DEFAULT (1)

◆ AI205_FIR_DISABLED

#define AI205_FIR_DISABLED (0)

◆ AI205_FIR_PROGRAMMED

#define AI205_FIR_PROGRAMMED (6)

◆ AI205_SHOW_SUM

#define AI205_SHOW_SUM (0x80)

◆ AI205_STARTRATE

#define AI205_STARTRATE (DQ_AI205_BASE/100-1)

◆ AI208_MAXEXCITE

#define AI208_MAXEXCITE (10.0)

◆ AI208_MINEXCITE

#define AI208_MINEXCITE (1.5)

◆ AI211_CFGAMG_BW_0_1HZ

#define AI211_CFGAMG_BW_0_1HZ (1UL<<7)

◆ AI211_CFGAMG_BW_10HZ

#define AI211_CFGAMG_BW_10HZ (1UL<<9)

◆ AI211_CFGAMG_BW_1HZ

#define AI211_CFGAMG_BW_1HZ (1UL<<8)

◆ AI211_CFGAMG_BW_DC

#define AI211_CFGAMG_BW_DC (1UL<<6)

◆ AI211_CFGAMG_DEFAULT_STATE

#define AI211_CFGAMG_DEFAULT_STATE (0x020A)

◆ AI211_CFGAMG_FLOFF

#define AI211_CFGAMG_FLOFF (1UL<<4)

◆ AI211_CFGAMG_FMTR

#define AI211_CFGAMG_FMTR (1UL<<16)

◆ AI211_CFGAMG_GAIN

#define AI211_CFGAMG_GAIN ( G ) ((G&3UL)<<10)

◆ AI211_CFGAMG_GAIN_MASK

#define AI211_CFGAMG_GAIN_MASK (3UL<<10)

◆ AI211_CFGAMG_IDIS

#define AI211_CFGAMG_IDIS (1UL<<3)

◆ AI211_CFGAMG_L0COMP

#define AI211_CFGAMG_L0COMP (1UL<<13)

◆ AI211_CFGAMG_L0STATE

#define AI211_CFGAMG_L0STATE (1UL<<12)

◆ AI211_CFGAMG_L1COMP

#define AI211_CFGAMG_L1COMP (1UL<<15)

◆ AI211_CFGAMG_L1STATE

#define AI211_CFGAMG_L1STATE (1UL<<14)

◆ AI211_CFGAMG_M_ADCENFEN

#define AI211_CFGAMG_M_ADCENFEN (1UL<<1)

◆ AI211_CFGAMG_OFFSET

#define AI211_CFGAMG_OFFSET (1UL<<5)

◆ AI211_CFGAMG_S_ADCEN

#define AI211_CFGAMG_S_ADCEN (1UL<<2)

◆ AI211_CLID_FMTR0_ADCD0

#define AI211_CLID_FMTR0_ADCD0 (1UL<<0)

◆ AI211_CLID_FMTR0_CHN0

#define AI211_CLID_FMTR0_CHN0 (3UL<<28)

◆ AI211_CLID_FMTR0_INFOO

#define AI211_CLID_FMTR0_INFOO (1UL<<27)

◆ AI211_CLID_FMTR0_INFOU

#define AI211_CLID_FMTR0_INFOU (1UL<<26)

◆ AI211_CLID_FMTR0_SMSB0

#define AI211_CLID_FMTR0_SMSB0 (3UL<<24)

◆ AI211_FIR_COEFF_LOAD

#define AI211_FIR_COEFF_LOAD (0x4)

◆ AI211_FIR_DISABLE

#define AI211_FIR_DISABLE (0x0)

◆ AI211_FIR_ENABLE

#define AI211_FIR_ENABLE (0x1)

◆ AI211_FIR_SET_DECIMATION_RATE

#define AI211_FIR_SET_DECIMATION_RATE (0x2)

◆ AI211_FIR_SET_DEFAULT

#define AI211_FIR_SET_DEFAULT (0x8)

◆ AI211_FIRFIRST_DISABLE

#define AI211_FIRFIRST_DISABLE (0x10)

◆ AI211_FIRFIRST_ENABLE

#define AI211_FIRFIRST_ENABLE (0)

◆ AI211_MAXCVFRQ

#define AI211_MAXCVFRQ (125000)

◆ AI211_MINCVFRQ_AVG

#define AI211_MINCVFRQ_AVG (AI211_MAXCVFRQ/2)

◆ AI211_SEL_CHAN_0

#define AI211_SEL_CHAN_0 (0x01)

◆ AI211_SEL_CHAN_1

#define AI211_SEL_CHAN_1 (0x02)

◆ AI211_SEL_CHAN_2

#define AI211_SEL_CHAN_2 (0x04)

◆ AI211_SEL_CHAN_3

#define AI211_SEL_CHAN_3 (0x08)

◆ AI211_SEL_CHAN_ALL

#define AI211_SEL_CHAN_ALL (0x0f)

◆ AI217_DEFAULT_CJC_GAIN_CAL

#define AI217_DEFAULT_CJC_GAIN_CAL (0x0800000)

◆ AI217_DEFAULT_CJC_OFFS_CAL

#define AI217_DEFAULT_CJC_OFFS_CAL (0)

◆ AI217_DEFAULT_GAIN_CAL

#define AI217_DEFAULT_GAIN_CAL (0x0b8ba00)

◆ AI217_DEFAULT_OFFS_CAL

#define AI217_DEFAULT_OFFS_CAL (0)

◆ AI255_CHANONLY_MASK

#define AI255_CHANONLY_MASK 0x1

◆ AI255_GAIN_MASK

#define AI255_GAIN_MASK 0x3

◆ AO333_CAL_ADC_EE_ERR

#define AO333_CAL_ADC_EE_ERR (-93)

◆ AO333_CAL_ADC_GAIN_RANGE

#define AO333_CAL_ADC_GAIN_RANGE (-94)

◆ AO333_CAL_ADC_N9_5_LIMIT

#define AO333_CAL_ADC_N9_5_LIMIT (-95)

◆ AO333_CAL_ADC_OFFSET_RANGE

#define AO333_CAL_ADC_OFFSET_RANGE (-96)

◆ AO333_CAL_ADC_RA_HIGH

#define AO333_CAL_ADC_RA_HIGH (-99)

◆ AO333_CAL_ADC_RA_LOW

#define AO333_CAL_ADC_RA_LOW (-98)

◆ AO333_CAL_ADC_RD_FAIL

#define AO333_CAL_ADC_RD_FAIL (-97)

◆ AO333_CAL_ADC_SUCCESS

#define AO333_CAL_ADC_SUCCESS (1)

◆ AR566_ILE0

#define AR566_ILE0 (1L<<18)

◆ AR566_ILE1

#define AR566_ILE1 (1L<<19)

◆ AR566_ILE10

#define AR566_ILE10 (1L<<28)

◆ AR566_ILE11

#define AR566_ILE11 (1L<<29)

◆ AR566_ILE2

#define AR566_ILE2 (1L<<20)

◆ AR566_ILE3

#define AR566_ILE3 (1L<<21)

◆ AR566_ILE4

#define AR566_ILE4 (1L<<22)

◆ AR566_ILE5

#define AR566_ILE5 (1L<<23)

◆ AR566_ILE6

#define AR566_ILE6 (1L<<24)

◆ AR566_ILE7

#define AR566_ILE7 (1L<<25)

◆ AR566_ILE8

#define AR566_ILE8 (1L<<26)

◆ AR566_ILE9

#define AR566_ILE9 (1L<<27)

◆ AR566_IPE0

#define AR566_IPE0 (1L<<0)

◆ AR566_IPE1

#define AR566_IPE1 (1L<<1)

◆ AR566_IPE10

#define AR566_IPE10 (1L<<10)

◆ AR566_IPE11

#define AR566_IPE11 (1L<<11)

◆ AR566_IPE2

#define AR566_IPE2 (1L<<2)

◆ AR566_IPE3

#define AR566_IPE3 (1L<<3)

◆ AR566_IPE4

#define AR566_IPE4 (1L<<4)

◆ AR566_IPE5

#define AR566_IPE5 (1L<<5)

◆ AR566_IPE6

#define AR566_IPE6 (1L<<6)

◆ AR566_IPE7

#define AR566_IPE7 (1L<<7)

◆ AR566_IPE8

#define AR566_IPE8 (1L<<8)

◆ AR566_IPE9

#define AR566_IPE9 (1L<<9)

◆ AR566_LBLFILTSIZE

#define AR566_LBLFILTSIZE 256

◆ AR566_RXFDR_CEC

#define AR566_RXFDR_CEC (1L<<11)

◆ AR566_RXFDR_CEC_S

#define AR566_RXFDR_CEC_S (16)

◆ AR566_RXFDR_CMC

#define AR566_RXFDR_CMC (1L<<10)

◆ AR566_RXFDR_CMC_S

#define AR566_RXFDR_CMC_S (0)

◆ AR566_RXFDR_SC_S

#define AR566_RXFDR_SC_S (0)

◆ AR566_RXFDR_SRC0

#define AR566_RXFDR_SRC0 (1L<<8)

◆ AR566_RXFDR_SRC1

#define AR566_RXFDR_SRC1 (1L<<9)

◆ AR566_RXFDR_SRC_FF

#define AR566_RXFDR_SRC_FF (1)

◆ AR566_RXFDR_SRC_HPR

#define AR566_RXFDR_SRC_HPR (2)

◆ AR566_RXFDR_SRC_LPR

#define AR566_RXFDR_SRC_LPR (3)

◆ AR566_RXFDR_SRC_SCH

#define AR566_RXFDR_SRC_SCH (0)

◆ AR566_RXFIFOSIZE

#define AR566_RXFIFOSIZE 256

◆ AR566_RXLAF_D0

#define AR566_RXLAF_D0 (1L<<0)

◆ AR566_RXLAF_D7

#define AR566_RXLAF_D7 (1L<<7)

◆ AR566_RXLAF_ND

#define AR566_RXLAF_ND (1L<<8)

◆ AR566_RXLAF_TR

#define AR566_RXLAF_TR (1L<<9)

◆ AR566_SCHEDDATASZ

#define AR566_SCHEDDATASZ 256

◆ AR566_SCHEDSIZE

#define AR566_SCHEDSIZE 256

◆ AR566_TXFIFOSIZE

#define AR566_TXFIFOSIZE 256

◆ AR566_TXSCC_ECO

#define AR566_TXSCC_ECO (1L<<24)

◆ AR566_TXSCC_EO

#define AR566_TXSCC_EO (1L<<22)

◆ AR566_TXSCC_ERR0

#define AR566_TXSCC_ERR0 (1L<<31)

◆ AR566_TXSCC_MA

#define AR566_TXSCC_MA (1L<<17)

◆ AR566_TXSCC_ME

#define AR566_TXSCC_ME (1L<<23)

◆ AR566_TXSCC_PS0

#define AR566_TXSCC_PS0 (1L<<20)

◆ AR566_TXSCC_PS1

#define AR566_TXSCC_PS1 (1L<<21)

◆ AR566_TXSCC_PS_100US

#define AR566_TXSCC_PS_100US (1)

◆ AR566_TXSCC_PS_DISABLED

#define AR566_TXSCC_PS_DISABLED (0)

◆ AR566_TXSCC_PS_PS0

#define AR566_TXSCC_PS_PS0 (2)

◆ AR566_TXSCC_PS_PS1

#define AR566_TXSCC_PS_PS1 (3)

◆ AR566_TXSCC_RC

#define AR566_TXSCC_RC (1L<<16)

◆ AR566_TXSCC_RSV0

#define AR566_TXSCC_RSV0 (1L<<18)

◆ AR566_TXSCC_RSV1

#define AR566_TXSCC_RSV1 (1L<<19)

◆ AR566_TXSCC_TD0

#define AR566_TXSCC_TD0 (1L<<0)

◆ AR566_TXSCC_TD15

#define AR566_TXSCC_TD15 (1L<<15)

◆ BC1553_BCB_ERRSTS0_BNR

#define BC1553_BCB_ERRSTS0_BNR (1L<<10)

◆ BC1553_BCB_ERRSTS0_CB

#define BC1553_BCB_ERRSTS0_CB (1L<<15)

◆ BC1553_BCB_ERRSTS0_DCF

#define BC1553_BCB_ERRSTS0_DCF (1L<<2)

◆ BC1553_BCB_ERRSTS0_ER

#define BC1553_BCB_ERRSTS0_ER (1L<<5)

◆ BC1553_BCB_ERRSTS0_IRT

#define BC1553_BCB_ERRSTS0_IRT (1L<<7)

◆ BC1553_BCB_ERRSTS0_LR

#define BC1553_BCB_ERRSTS0_LR (1L<<6)

◆ BC1553_BCB_ERRSTS0_PD

#define BC1553_BCB_ERRSTS0_PD (1L<<13)

◆ BC1553_BCB_ERRSTS0_RCR

#define BC1553_BCB_ERRSTS0_RCR (1L<<9)

◆ BC1553_BCB_ERRSTS0_RSV14

#define BC1553_BCB_ERRSTS0_RSV14 (1L<<14)

◆ BC1553_BCB_ERRSTS0_S1B

#define BC1553_BCB_ERRSTS0_S1B (1L<<12)

◆ BC1553_BCB_ERRSTS0_S1F

#define BC1553_BCB_ERRSTS0_S1F (1L<<3)

◆ BC1553_BCB_ERRSTS0_S2B

#define BC1553_BCB_ERRSTS0_S2B (1L<<11)

◆ BC1553_BCB_ERRSTS0_S2F

#define BC1553_BCB_ERRSTS0_S2F (1L<<4)

◆ BC1553_BCB_ERRSTS0_TFW

#define BC1553_BCB_ERRSTS0_TFW (1L<<1)

◆ BC1553_BCB_ERRSTS0_TMW

#define BC1553_BCB_ERRSTS0_TMW (1L<<0)

◆ BC1553_BCB_ERRSTS0_WBR

#define BC1553_BCB_ERRSTS0_WBR (1L<<8)

◆ BC1553_BCB_ERRSTS1_0000

#define BC1553_BCB_ERRSTS1_0000 0x00

◆ BC1553_BCB_ERRSTS1_0001

#define BC1553_BCB_ERRSTS1_0001 0x01

◆ BC1553_BCB_ERRSTS1_0002

#define BC1553_BCB_ERRSTS1_0002 0x02

◆ BC1553_BCB_ERRSTS1_0003

#define BC1553_BCB_ERRSTS1_0003 0x03

◆ BC1553_BCB_ERRSTS1_0004

#define BC1553_BCB_ERRSTS1_0004 0x04

◆ BC1553_BCB_ERRSTS1_0005

#define BC1553_BCB_ERRSTS1_0005 0x05

◆ BC1553_BCB_ERRSTS1_0006

#define BC1553_BCB_ERRSTS1_0006 0x06

◆ BC1553_BCB_ERRSTS1_0007

#define BC1553_BCB_ERRSTS1_0007 0x07

◆ BC1553_BCB_ERRSTS1_0008

#define BC1553_BCB_ERRSTS1_0008 0x08

◆ BC1553_BCB_ERRSTS1_0009

#define BC1553_BCB_ERRSTS1_0009 0x09

◆ BC1553_BCB_ERRSTS1_000A

#define BC1553_BCB_ERRSTS1_000A 0x0A

◆ BC1553_BCB_ERRSTS1_000B

#define BC1553_BCB_ERRSTS1_000B 0x0B

◆ BC1553_BCB_ERRSTS1_000C

#define BC1553_BCB_ERRSTS1_000C 0x0C

◆ BC1553_BCB_ERRSTS1_000D

#define BC1553_BCB_ERRSTS1_000D 0x0D

◆ BC1553_BCB_ERRSTS1_000E

#define BC1553_BCB_ERRSTS1_000E 0x0E

◆ BC1553_BCB_ERRSTS1_000F

#define BC1553_BCB_ERRSTS1_000F 0x0F

◆ BC1553_BCB_ERRSTS1_0010

#define BC1553_BCB_ERRSTS1_0010 0x10

◆ BC1553_BCB_ERRSTS1_0011

#define BC1553_BCB_ERRSTS1_0011 0x11

◆ BC1553_BCB_ERRSTS1_0012

#define BC1553_BCB_ERRSTS1_0012 0x12

◆ BC1553_BCB_ERRSTS1_0013

#define BC1553_BCB_ERRSTS1_0013 0x13

◆ BC1553_BCB_ERRSTS1_0014

#define BC1553_BCB_ERRSTS1_0014 0x14

◆ BC1553_BCB_ERRSTS1_0015

#define BC1553_BCB_ERRSTS1_0015 0x15

◆ BC1553_BCB_ERRSTS1_0016

#define BC1553_BCB_ERRSTS1_0016 0x16

◆ BC1553_BCB_ERRSTS1_0017

#define BC1553_BCB_ERRSTS1_0017 0x17

◆ BC1553_BCB_ERRSTS1_0018

#define BC1553_BCB_ERRSTS1_0018 0x18

◆ BC1553_BCB_ERRSTS1_0019

#define BC1553_BCB_ERRSTS1_0019 0x19

◆ BC1553_BCB_ERRSTS1_001A

#define BC1553_BCB_ERRSTS1_001A 0x1A

◆ BC1553_BCB_ERRSTS1_001B

#define BC1553_BCB_ERRSTS1_001B 0x1B

◆ BC1553_BCB_ERRSTS1_001C

#define BC1553_BCB_ERRSTS1_001C 0x1C

◆ BC1553_BCB_ERRSTS1_001D

#define BC1553_BCB_ERRSTS1_001D 0x1D

◆ BC1553_BCB_ERRSTS1_001E

#define BC1553_BCB_ERRSTS1_001E 0x1E

◆ BC1553_BCB_ERRSTS1_001F

#define BC1553_BCB_ERRSTS1_001F 0x1F

◆ BC1553_BCB_ERRSTS1_0020

#define BC1553_BCB_ERRSTS1_0020 0x20

◆ BC1553_BCB_ERRSTS1_0021

#define BC1553_BCB_ERRSTS1_0021 0x21

◆ BC1553_BCB_ERRSTS1_0022

#define BC1553_BCB_ERRSTS1_0022 0x22

◆ BC1553_BCB_ERRSTS1_0023

#define BC1553_BCB_ERRSTS1_0023 0x23

◆ BC1553_BCB_ERRSTS1_0024

#define BC1553_BCB_ERRSTS1_0024 0x24

◆ BC1553_BCB_ERRSTS1_0025

#define BC1553_BCB_ERRSTS1_0025 0x25

◆ BC1553_BCB_ERRSTS1_0026

#define BC1553_BCB_ERRSTS1_0026 0x26

◆ BC1553_BCB_ERRSTS1_0027

#define BC1553_BCB_ERRSTS1_0027 0x27

◆ BC1553_BCB_ERRSTS1_0028

#define BC1553_BCB_ERRSTS1_0028 0x28

◆ BC1553_BCB_ERRSTS1_0029

#define BC1553_BCB_ERRSTS1_0029 0x29

◆ BC1553_BCB_ERRSTS1_002A

#define BC1553_BCB_ERRSTS1_002A 0x2A

◆ BC1553_BCB_ERRSTS1_002B

#define BC1553_BCB_ERRSTS1_002B 0x2B

◆ BC1553_BCB_ERRSTS1_002C

#define BC1553_BCB_ERRSTS1_002C 0x2C

◆ BC1553_BCB_ERRSTS1_002D

#define BC1553_BCB_ERRSTS1_002D 0x2D

◆ BC1553_BCB_ERRSTS1_002E

#define BC1553_BCB_ERRSTS1_002E 0x2E

◆ BC1553_BCB_ERRSTS1_002F

#define BC1553_BCB_ERRSTS1_002F 0x2F

◆ BC1553_BCB_ERRSTS1_0030

#define BC1553_BCB_ERRSTS1_0030 0x30

◆ BC1553_BCB_ERRSTS1_0031

#define BC1553_BCB_ERRSTS1_0031 0x31

◆ BC1553_BCB_ERRSTS1_0032

#define BC1553_BCB_ERRSTS1_0032 0x32

◆ BC1553_BCB_ERRSTS1_0033

#define BC1553_BCB_ERRSTS1_0033 0x33

◆ BC1553_BCB_ERRSTS1_0034

#define BC1553_BCB_ERRSTS1_0034 0x34

◆ BC1553_BCB_ERRSTS1_0035

#define BC1553_BCB_ERRSTS1_0035 0x35

◆ BC1553_BCB_ERRSTS1_0036

#define BC1553_BCB_ERRSTS1_0036 0x36

◆ BC1553_BCB_ERRSTS1_0037

#define BC1553_BCB_ERRSTS1_0037 0x37

◆ BC1553_BCB_ERRSTS1_0100

#define BC1553_BCB_ERRSTS1_0100 0x100

◆ BC1553_BCB_ERRSTS1_0200

#define BC1553_BCB_ERRSTS1_0200 0x200

◆ BC1553_BCB_ERRSTS1_0300

#define BC1553_BCB_ERRSTS1_0300 0x300

◆ BC1553_BCB_ERRSTS1_0400

#define BC1553_BCB_ERRSTS1_0400 0x400

◆ BC1553_BCB_ERRSTS1_0500

#define BC1553_BCB_ERRSTS1_0500 0x500

◆ BC1553_BCB_ERRSTS1_0600

#define BC1553_BCB_ERRSTS1_0600 0x600

◆ BC1553_BCB_ERRSTS1_0700

#define BC1553_BCB_ERRSTS1_0700 0x700

◆ BC1553_BCB_ERRSTS1_0800

#define BC1553_BCB_ERRSTS1_0800 0x800

◆ BC1553_BCB_ERRSTS1_0900

#define BC1553_BCB_ERRSTS1_0900 0x900

◆ BC1553_BCB_ERRSTS1_0A00

#define BC1553_BCB_ERRSTS1_0A00 0xA00

◆ BC1553_BCB_ERRSTS1_0B00

#define BC1553_BCB_ERRSTS1_0B00 0xB00

◆ BC1553_BCB_ERRSTS1_0C00

#define BC1553_BCB_ERRSTS1_0C00 0xC00

◆ BC1553_BCB_ERRSTS1_0D00

#define BC1553_BCB_ERRSTS1_0D00 0xD00

◆ BC1553_BCB_ERRSTS1_8000

#define BC1553_BCB_ERRSTS1_8000 0x8000

◆ BC1553_BCB_FLAGS0_AEN

#define BC1553_BCB_FLAGS0_AEN (1L<<13)

◆ BC1553_BCB_FLAGS0_BEN

#define BC1553_BCB_FLAGS0_BEN (1L<<14)

◆ BC1553_BCB_FLAGS0_DTC

#define BC1553_BCB_FLAGS0_DTC (1L<<7)

◆ BC1553_BCB_FLAGS0_EXW

#define BC1553_BCB_FLAGS0_EXW (1L<<12)

◆ BC1553_BCB_FLAGS0_IRQ

#define BC1553_BCB_FLAGS0_IRQ (1L<<15)

◆ BC1553_BCB_FLAGS0_MDC

#define BC1553_BCB_FLAGS0_MDC (1L<<6)

◆ BC1553_BCB_FLAGS0_RSV10

#define BC1553_BCB_FLAGS0_RSV10 (1L<<10)

◆ BC1553_BCB_FLAGS0_RSV11

#define BC1553_BCB_FLAGS0_RSV11 (1L<<11)

◆ BC1553_BCB_FLAGS0_RSV9

#define BC1553_BCB_FLAGS0_RSV9 (1L<<9)

◆ BC1553_BCB_FLAGS0_SBUS

#define BC1553_BCB_FLAGS0_SBUS (1L<<8)

◆ BC1553_BCB_FLAGS0_STS1

#define BC1553_BCB_FLAGS0_STS1 (1L<<4)

◆ BC1553_BCB_FLAGS0_STS2

#define BC1553_BCB_FLAGS0_STS2 (1L<<5)

◆ BC1553_BCB_FLAGS0_TT

#define BC1553_BCB_FLAGS0_TT ( N ) ((N)&0xf)

◆ BC1553_BCB_FLAGS1_ERE

#define BC1553_BCB_FLAGS1_ERE (1L<<4)

◆ BC1553_BCB_FLAGS1_ERRC

#define BC1553_BCB_FLAGS1_ERRC ( N ) ((N)&7)

◆ BC1553_BCB_FLAGS1_ESR

#define BC1553_BCB_FLAGS1_ESR (1L<<3)

◆ BC1553_BCB_FLAGS1_IRT

#define BC1553_BCB_FLAGS1_IRT (1L<<14)

◆ BC1553_BCB_FLAGS1_RBB

#define BC1553_BCB_FLAGS1_RBB (1L<<9)

◆ BC1553_BCB_FLAGS1_RE

#define BC1553_BCB_FLAGS1_RE (1L<<6)

◆ BC1553_BCB_FLAGS1_RIS

#define BC1553_BCB_FLAGS1_RIS (1L<<10)

◆ BC1553_BCB_FLAGS1_RNR

#define BC1553_BCB_FLAGS1_RNR (1L<<5)

◆ BC1553_BCB_FLAGS1_RSV15

#define BC1553_BCB_FLAGS1_RSV15 (1L<<15)

◆ BC1553_BCB_FLAGS1_RTE

#define BC1553_BCB_FLAGS1_RTE (1L<<8)

◆ BC1553_BCB_FLAGS1_RUD

#define BC1553_BCB_FLAGS1_RUD (1L<<12)

◆ BC1553_BCB_FLAGS1_RUS

#define BC1553_BCB_FLAGS1_RUS (1L<<13)

◆ BC1553_BCB_FLAGS1_RWB

#define BC1553_BCB_FLAGS1_RWB (1L<<11)

◆ BC1553_BCB_FLAGS1_RWC

#define BC1553_BCB_FLAGS1_RWC (1L<<7)

◆ BC1553_BCB_FLAGS2_DELAY

#define BC1553_BCB_FLAGS2_DELAY ( N ) ((N)&0x7fff)

◆ BC1553_BCB_FLAGS2_ENABLE

#define BC1553_BCB_FLAGS2_ENABLE (1L<<15)

◆ BC1553_BCB_TT_BBCRT_1F

#define BC1553_BCB_TT_BBCRT_1F 7

◆ BC1553_BCB_TT_BCRT_1E

#define BC1553_BCB_TT_BCRT_1E 1

◆ BC1553_BCB_TT_BMD_1B

#define BC1553_BCB_TT_BMD_1B 9

◆ BC1553_BCB_TT_BMDRX_1D

#define BC1553_BCB_TT_BMDRX_1D 10

◆ BC1553_BCB_TT_BRTRT_3B

#define BC1553_BCB_TT_BRTRT_3B 8

◆ BC1553_BCB_TT_MD_1A

#define BC1553_BCB_TT_MD_1A 4

◆ BC1553_BCB_TT_MDRX_1C

#define BC1553_BCB_TT_MDRX_1C 6

◆ BC1553_BCB_TT_MDTX_2A

#define BC1553_BCB_TT_MDTX_2A 5

◆ BC1553_BCB_TT_RTBC_2B

#define BC1553_BCB_TT_RTBC_2B 2

◆ BC1553_BCB_TT_RTRT_3A

#define BC1553_BCB_TT_RTRT_3A 3

◆ BUS_FREQUENCY

#define BUS_FREQUENCY (66000000)

◆ CAN_EFF

#define CAN_EFF ( D ) (((D)&0x80)>>7)

◆ CAN_LEN

#define CAN_LEN ( D ) ( (((D)&0x0f)>8) ? 8 : ((D)&0x0f) )

◆ CHLISTSZ

#define CHLISTSZ 128

◆ CLR_STS_FLAG

#define CLR_STS_FLAG	(	DEV,
		SS,
		FG,
		FLAG
	)	(((pDEVOBJ)(DEV))->status[(SS)&7][FG] &= (~FLAG))

◆ CMD1553_BROADCAST

#define CMD1553_BROADCAST 0x80

◆ CMD1553_MD_DBC

#define CMD1553_MD_DBC 0x0

◆ CMD1553_MD_IST

#define CMD1553_MD_IST 0x3

◆ CMD1553_MD_ITFB

#define CMD1553_MD_ITFB 0x6

◆ CMD1553_MD_OITFB

#define CMD1553_MD_OITFB 0x7

◆ CMD1553_MD_OSTXD

#define CMD1553_MD_OSTXD 0x15

◆ CMD1553_MD_OTXD

#define CMD1553_MD_OTXD 0x5

◆ CMD1553_MD_RRT

#define CMD1553_MD_RRT 0x8

◆ CMD1553_MD_STXD

#define CMD1553_MD_STXD 0x14

◆ CMD1553_MD_SYNC

#define CMD1553_MD_SYNC 0x1

◆ CMD1553_MD_SYNCD

#define CMD1553_MD_SYNCD 0x11

◆ CMD1553_MD_TBIT

#define CMD1553_MD_TBIT 0x13

◆ CMD1553_MD_TLCW

#define CMD1553_MD_TLCW 0x12

◆ CMD1553_MD_TST

#define CMD1553_MD_TST 0x2

◆ CMD1553_MD_TVW

#define CMD1553_MD_TVW 0x10

◆ CMD1553_MD_TXD

#define CMD1553_MD_TXD 0x4

◆ CMD1553_RT_RT

#define CMD1553_RT_RT 0x22

◆ CMD1553_RT_RX

#define CMD1553_RT_RX 0x21

◆ CMD1553_RT_TX

#define CMD1553_RT_TX 0x20

◆ CY22150_BASE

#define CY22150_BASE (66000000)

◆ CY22150_MAX_VCO

#define CY22150_MAX_VCO (365000000.0)

◆ CY22150_MAXP

#define CY22150_MAXP (800)

◆ CY22150_MAXQ

#define CY22150_MAXQ (129)

◆ CY22150_MIN_VCO

#define CY22150_MIN_VCO (100000000.0)

◆ CY22150_MINP

#define CY22150_MINP (8)

◆ CY22150_MINQ

#define CY22150_MINQ (5)

◆ DIO401_2_4_5_CMDRDWR

#define DIO401_2_4_5_CMDRDWR (DQL_CL_CMD1)

◆ DIO416_CMDRDWR

#define DIO416_CMDRDWR (DQL_CL_CMD1)

◆ DL_DL_CTRL_CANCEL

#define DL_DL_CTRL_CANCEL 1

◆ DL_DL_CTRL_RESET

#define DL_DL_CTRL_RESET 2

◆ DL_ERR_ALARM_CFG

#define DL_ERR_ALARM_CFG (0x80020000)

◆ DL_ERR_LAYER_CFG

#define DL_ERR_LAYER_CFG (0x80040000)

◆ DL_ERR_MASTER_CFG

#define DL_ERR_MASTER_CFG (0x80010000)

◆ DL_ERR_OP_ERROR

#define DL_ERR_OP_ERROR (0x80080000)

◆ DL_ERROR

#define DL_ERROR (0x80000000)

◆ DL_ERROR_MASK

#define DL_ERROR_MASK (0x80000000)

◆ DL_GET_CHN_LST

#define DL_GET_CHN_LST 1

◆ DL_GET_LAST_SCAN

#define DL_GET_LAST_SCAN 2

◆ DL_IDLE

#define DL_IDLE (0)

◆ DL_LYSTATE_ERROR

#define DL_LYSTATE_ERROR (0x80010000)

◆ DL_LYSTATE_FIFOOVF

#define DL_LYSTATE_FIFOOVF (0x80020000)

◆ DL_LYSTATE_IDLE

#define DL_LYSTATE_IDLE (0)

◆ DL_LYSTATE_RUNNING

#define DL_LYSTATE_RUNNING (2)

◆ DL_LYSTATE_STRIG

#define DL_LYSTATE_STRIG (1)

◆ DL_LYSTATR_BUFOVF

#define DL_LYSTATR_BUFOVF (0x80040000)

◆ DL_LYSTATR_CFGERR

#define DL_LYSTATR_CFGERR (0x80080000)

◆ DL_LYSTATR_WRONGMOD

#define DL_LYSTATR_WRONGMOD (0x80100000)

◆ DL_OK

#define DL_OK (1)

◆ DL_RUNNING

#define DL_RUNNING (2)

◆ DL_SD_CTRL_CANCEL

#define DL_SD_CTRL_CANCEL 3

◆ DL_SD_CTRL_FORMAT

#define DL_SD_CTRL_FORMAT 2

◆ DL_SD_CTRL_GETFREE

#define DL_SD_CTRL_GETFREE 1

◆ DL_SD_CTRL_ISDONE

#define DL_SD_CTRL_ISDONE 5

◆ DL_SD_CTRL_RESET

#define DL_SD_CTRL_RESET 4

◆ DL_SDSTAT_FULL

#define DL_SDSTAT_FULL (0x80040000)

◆ DL_SDSTAT_NO_CARD

#define DL_SDSTAT_NO_CARD (0x3)

◆ DL_SDSTAT_OK

#define DL_SDSTAT_OK (0x1)

◆ DL_SDSTAT_RD_ERR

#define DL_SDSTAT_RD_ERR (0x80020000)

◆ DL_SDSTAT_RDONLY

#define DL_SDSTAT_RDONLY (0x2)

◆ DL_SDSTAT_UNKNOWN

#define DL_SDSTAT_UNKNOWN (0x0)

◆ DL_SDSTAT_WR_ERR

#define DL_SDSTAT_WR_ERR (0x80010000)

◆ DL_STOPPED

#define DL_STOPPED (4)

◆ DL_WAIT_MASTER

#define DL_WAIT_MASTER (0)

◆ DNA_LB

#define DNA_LB (0x44)

◆ DNA_PWR_1G

#define DNA_PWR_1G (0x41)

◆ DNA_QTB

#define DNA_QTB (0x45)

◆ DNR_LB

#define DNR_LB (0x42)

◆ DNR_PWR

#define DNR_PWR (0x20)

◆ DNR_PWR_1G

#define DNR_PWR_1G (0x40)

◆ DNR_QTB

#define DNR_QTB (0x43)

◆ DNx_ADDR_BUS_TEST_MASK

#define DNx_ADDR_BUS_TEST_MASK (0x0000FFFC)

◆ DQ211_DRIVE_CURRENT

#define DQ211_DRIVE_CURRENT ( I ) (((I)/8.0)*255)

◆ DQ503_MINSZ_SECRX

#define DQ503_MINSZ_SECRX	(	DT,
		CHANNEL
	)	( ((pDEVOBJ_503)DT->devobj)->chnls[CHANNEL].mode == DQ503_BASIC ? 13 : 14)

◆ DQ_211_ALARM_GREEN

#define DQ_211_ALARM_GREEN (0x8)

◆ DQ_211_ALARM_OFF

#define DQ_211_ALARM_OFF (0)

◆ DQ_211_ALARM_ON

#define DQ_211_ALARM_ON (0x3)

◆ DQ_211_ALARM_ORANGE

#define DQ_211_ALARM_ORANGE (0x0c)

◆ DQ_211_ALARM_RED

#define DQ_211_ALARM_RED (0x4)

◆ DQ_211_ANALOG_FILTER_OFF

#define DQ_211_ANALOG_FILTER_OFF (0)

◆ DQ_211_ANALOG_FILTER_ON

#define DQ_211_ANALOG_FILTER_ON (1)

◆ DQ_211_BIAS_OFF

#define DQ_211_BIAS_OFF (0)

◆ DQ_211_BIAS_ON

#define DQ_211_BIAS_ON (1)

◆ DQ_211_CLK_24MHZ

#define DQ_211_CLK_24MHZ (0x10)

◆ DQ_211_CLK_66MHZ

#define DQ_211_CLK_66MHZ (0)

◆ DQ_211_CLK_DIV_MAX

#define DQ_211_CLK_DIV_MAX (0x3ff)

◆ DQ_211_CLK_SYNC0_BUS

#define DQ_211_CLK_SYNC0_BUS (0x8)

◆ DQ_211_CLK_SYNC1_BUS

#define DQ_211_CLK_SYNC1_BUS (0x9)

◆ DQ_211_CLK_SYNC2

#define DQ_211_CLK_SYNC2 (0x18)

◆ DQ_211_CLK_SYNC2_BUS

#define DQ_211_CLK_SYNC2_BUS (0xa)

◆ DQ_211_CLK_SYNC3_BUS

#define DQ_211_CLK_SYNC3_BUS (0xb)

◆ DQ_211_COMP_HI_DEFAULT

#define DQ_211_COMP_HI_DEFAULT (0xfff)

◆ DQ_211_COMP_HI_STD

#define DQ_211_COMP_HI_STD (0xfa0)

◆ DQ_211_COMP_LO_DEFAULT

#define DQ_211_COMP_LO_DEFAULT (0x0)

◆ DQ_211_COMP_LO_STD

#define DQ_211_COMP_LO_STD (0x0c0)

◆ DQ_211_FMTR_NORMAL

#define DQ_211_FMTR_NORMAL (0)

◆ DQ_211_FMTR_REDUCED

#define DQ_211_FMTR_REDUCED (1)

◆ DQ_211_HPF_10_HZ

#define DQ_211_HPF_10_HZ (1L<<3)

◆ DQ_211_HPF_1_HZ

#define DQ_211_HPF_1_HZ (1L<<2)

◆ DQ_211_HPF_DC

#define DQ_211_HPF_DC (1L<<0)

◆ DQ_211_HPF_POINT1_HZ

#define DQ_211_HPF_POINT1_HZ (1L<<1)

◆ DQ_211_MAIN_FLOW_OFF

#define DQ_211_MAIN_FLOW_OFF (0)

◆ DQ_211_MAIN_FLOW_ON

#define DQ_211_MAIN_FLOW_ON (1)

◆ DQ_211_MAX_BIAS

#define DQ_211_MAX_BIAS (0xff)

◆ DQ_211_OFFSET_TEST_OFF

#define DQ_211_OFFSET_TEST_OFF (0)

◆ DQ_211_OFFSET_TEST_ON

#define DQ_211_OFFSET_TEST_ON (1)

◆ DQ_211_SEC_ENB_LED

#define DQ_211_SEC_ENB_LED (0x1)

◆ DQ_211_SEC_ENB_OFF

#define DQ_211_SEC_ENB_OFF (0)

◆ DQ_211_SEC_N_OFF

#define DQ_211_SEC_N_OFF (0)

◆ DQ_211_SEC_N_STD

#define DQ_211_SEC_N_STD (100)

◆ DQ_308_RD_TEST_CHANS

#define DQ_308_RD_TEST_CHANS (12)

◆ DQ_308_RD_TEST_SF_350

#define DQ_308_RD_TEST_SF_350 ((10240.0)/(240.0))

◆ DQ_308_RD_TEST_SF_353

#define DQ_308_RD_TEST_SF_353 ((39240.0)/(240.0))

◆ DQ_308_RD_TEST_SF_V15

#define DQ_308_RD_TEST_SF_V15 ((19840.0)/(240.0))

◆ DQ_308_RD_TEST_SF_VEX

#define DQ_308_RD_TEST_SF_VEX ((51240.0)/(240.0))

◆ DQ_332_RD_TEST_CHANS

#define DQ_332_RD_TEST_CHANS (32)

◆ DQ_3XX_RD_TEST_OFFSET

#define DQ_3XX_RD_TEST_OFFSET (DQ_3XX_RD_TEST_SPAN/2.0)

◆ DQ_3XX_RD_TEST_SPAN

#define DQ_3XX_RD_TEST_SPAN (2.5)

◆ DQ_3XX_RD_TEST_STEP

#define DQ_3XX_RD_TEST_STEP (DQ_3XX_RD_TEST_SPAN/(double)0xffffff)

◆ DQ_911_P10_N10_24W

#define DQ_911_P10_N10_24W (DQ_91X_CFG_DCEN1+DQ_91X_CFG_DCEN3)

◆ DQ_911_P15_N15_36W

#define DQ_911_P15_N15_36W (DQ_91X_CFG_DCEN1+DQ_91X_CFG_DCEN2+DQ_91X_CFG_DCEN3)

◆ DQ_911_P15_N5_24W

#define DQ_911_P15_N5_24W (DQ_91X_CFG_DCEN1+DQ_91X_CFG_DCEN2)

◆ DQ_911_P5_N15_24W

#define DQ_911_P5_N15_24W (DQ_91X_CFG_DCEN2+DQ_91X_CFG_DCEN3)

◆ DQ_911_P5_N5_12W

#define DQ_911_P5_N5_12W (DQ_91X_CFG_DCEN2)

◆ DQ_912_P12_20W

#define DQ_912_P12_20W (DQ_91X_CFG_DCEN1)

◆ DQ_912_P24_40W

#define DQ_912_P24_40W (DQ_91X_CFG_DCEN1+DQ_91X_CFG_DCEN3)

◆ DQ_913_P15_N15_12W

#define DQ_913_P15_N15_12W (DQ_91X_CFG_DCEN2)

◆ DQ_913_P15_N45_24W

#define DQ_913_P15_N45_24W (DQ_91X_CFG_DCEN2+DQ_91X_CFG_DCEN3)

◆ DQ_913_P30_N30_24W

#define DQ_913_P30_N30_24W (DQ_91X_CFG_DCEN1+DQ_91X_CFG_DCEN3)

◆ DQ_913_P45_N15_24W

#define DQ_913_P45_N15_24W (DQ_91X_CFG_DCEN1+DQ_91X_CFG_DCEN2)

◆ DQ_913_P45_N45_36W

#define DQ_913_P45_N45_36W (DQ_91X_CFG_DCEN1+DQ_91X_CFG_DCEN2+DQ_91X_CFG_DCEN3)

◆ DQ_91X_CFG_DCEN1

#define DQ_91X_CFG_DCEN1 (1L<<28)

◆ DQ_91X_CFG_DCEN2

#define DQ_91X_CFG_DCEN2 (1L<<29)

◆ DQ_91X_CFG_DCEN3

#define DQ_91X_CFG_DCEN3 (1L<<30)

◆ DQ_91X_EXT_JIO_AUTOSWITCH

#define DQ_91X_EXT_JIO_AUTOSWITCH (DQ_PC_91X_CFG_EJIO+DQ_PC_91X_CFG_AUTO)

◆ DQ_91X_EXT_JIO_POWER

#define DQ_91X_EXT_JIO_POWER (DQ_PC_91X_CFG_EJIO)

◆ DQ_91X_INTERNAL_POWER

#define DQ_91X_INTERNAL_POWER (0)

◆ DQ_91X_POWER_OFF

#define DQ_91X_POWER_OFF (0)

◆ DQ_91X_STS_JIO

#define DQ_91X_STS_JIO (1L<<0)

◆ DQ_91X_STS_JIO_ON

#define DQ_91X_STS_JIO_ON (1L<<1)

◆ DQ_91X_STS_JMAIN_ON

#define DQ_91X_STS_JMAIN_ON (1L<<2)

◆ DQ_ACB_HEADERSZ

#define DQ_ACB_HEADERSZ (ETH_HDR_SIZE + IP_HDR_SIZE + UDP_HDR_SIZE + DQHSZ + DQFIFOHSZ + sizeof(uint32))

◆ DQ_ACCESS_DIO1_OUT

#define DQ_ACCESS_DIO1_OUT (1L<<1)

◆ DQ_ACCESS_DIO2_OUT

#define DQ_ACCESS_DIO2_OUT (1L<<0)

◆ DQ_ACCESS_DIO_CFG_DIO1_IN

#define DQ_ACCESS_DIO_CFG_DIO1_IN (2)

◆ DQ_ACCESS_DIO_CFG_DIO1_OUT

#define DQ_ACCESS_DIO_CFG_DIO1_OUT (1)

◆ DQ_ACCESS_DIO_CFG_READ_DI_ONLY

#define DQ_ACCESS_DIO_CFG_READ_DI_ONLY (0)

◆ DQ_ACCESS_DIO_DIO0_ENB

#define DQ_ACCESS_DIO_DIO0_ENB (0x1)

◆ DQ_ACCESS_DIO_DIO0_IN

#define DQ_ACCESS_DIO_DIO0_IN (0)

◆ DQ_ACCESS_DIO_DIO0_OUT

#define DQ_ACCESS_DIO_DIO0_OUT (0x10)

◆ DQ_ACCESS_DIO_DIO1_ENB

#define DQ_ACCESS_DIO_DIO1_ENB (0x2)

◆ DQ_ACCESS_DIO_DIO1_IN

#define DQ_ACCESS_DIO_DIO1_IN (0)

◆ DQ_ACCESS_DIO_DIO1_OUT

#define DQ_ACCESS_DIO_DIO1_OUT (0x20)

◆ DQ_ACCESS_DIO_DIO2_ENB

#define DQ_ACCESS_DIO_DIO2_ENB (0x4)

◆ DQ_ACCESS_DIO_DIO2_IN

#define DQ_ACCESS_DIO_DIO2_IN (0)

◆ DQ_ACCESS_DIO_DIO2_OUT

#define DQ_ACCESS_DIO_DIO2_OUT (0x40)

◆ DQ_ACCESS_DIO_DIO3_ENB

#define DQ_ACCESS_DIO_DIO3_ENB (0x8)

◆ DQ_ACCESS_DIO_DIO3_IN

#define DQ_ACCESS_DIO_DIO3_IN (0)

◆ DQ_ACCESS_DIO_DIO3_OUT

#define DQ_ACCESS_DIO_DIO3_OUT (0x80)

◆ DQ_ACCESS_DIO_STATUS_DIO0_IN

#define DQ_ACCESS_DIO_STATUS_DIO0_IN (1L<<2)

◆ DQ_ACCESS_DIO_STATUS_DIO1_IN

#define DQ_ACCESS_DIO_STATUS_DIO1_IN (1L<<3)

◆ DQ_ACCESS_DIO_STATUS_DIO1_OUT

#define DQ_ACCESS_DIO_STATUS_DIO1_OUT (1L<<1)

◆ DQ_ACCESS_DIO_STATUS_DIO2_OUT

#define DQ_ACCESS_DIO_STATUS_DIO2_OUT (1L<<0)

◆ DQ_AD7776_GETCH

#define DQ_AD7776_GETCH ( V ) ((V>>28)&3)

◆ DQ_AD7776_GETVAL

#define DQ_AD7776_GETVAL ( V ) (V)

◆ DQ_AD7776_GETVAL16

#define DQ_AD7776_GETVAL16 ( V ) (V&0x3ffff >> 2)

◆ DQ_AD7776_GETVALS

#define DQ_AD7776_GETVALS ( V ) (V&0x3ffff)

◆ DQ_AI201_BASE

#define DQ_AI201_BASE (BUS_FREQUENCY)

◆ DQ_AI201_CALDACS

#define DQ_AI201_CALDACS (4)

◆ DQ_AI201_CHAN

#define DQ_AI201_CHAN (24)

◆ DQ_AI201_CHANSVC

#define DQ_AI201_CHANSVC (32)

◆ DQ_AI201_CL_TIMES

#define DQ_AI201_CL_TIMES (2)

◆ DQ_AI201_FIFO_CH

#define DQ_AI201_FIFO_CH (128)

◆ DQ_AI201_FIFO_GET_DATA

#define DQ_AI201_FIFO_GET_DATA (DQ_FIFO_GET_DATA)

◆ DQ_AI201_GAIN_1

#define DQ_AI201_GAIN_1 (0)

◆ DQ_AI201_GAIN_10

#define DQ_AI201_GAIN_10 (1)

◆ DQ_AI201_GAIN_100

#define DQ_AI201_GAIN_100 (2)

◆ DQ_AI201_GAIN_1000

#define DQ_AI201_GAIN_1000 (3)

◆ DQ_AI201_GAIN_10_100

#define DQ_AI201_GAIN_10_100 (3)

◆ DQ_AI201_GAIN_1_100

#define DQ_AI201_GAIN_1_100 (0)

◆ DQ_AI201_GAIN_2_100

#define DQ_AI201_GAIN_2_100 (1)

◆ DQ_AI201_GAIN_5_100

#define DQ_AI201_GAIN_5_100 (2)

◆ DQ_AI201_GAINS

#define DQ_AI201_GAINS (4)

◆ DQ_AI201_GAINV_0

#define DQ_AI201_GAINV_0 (1)

◆ DQ_AI201_GAINV_1

#define DQ_AI201_GAINV_1 (10)

◆ DQ_AI201_GAINV_2

#define DQ_AI201_GAINV_2 (100)

◆ DQ_AI201_GAINV_3

#define DQ_AI201_GAINV_3 (1000)

◆ DQ_AI201_INFOSZ

#define DQ_AI201_INFOSZ (DQ_MAX_INFO_SIZE)

◆ DQ_AI201_MAXCLFRQ

#define DQ_AI201_MAXCLFRQ (120000)

◆ DQ_AI201_MAXCVFRQ

#define DQ_AI201_MAXCVFRQ (120000)

◆ DQ_AI201_MODECONT

#define DQ_AI201_MODECONT (DQ_FIFO_MODECONT)

◆ DQ_AI201_MODEFIFO

#define DQ_AI201_MODEFIFO (DQ_FIFO_MODEFIFO)

◆ DQ_AI201_MODESCAN

#define DQ_AI201_MODESCAN (DQ_FIFO_MODESCAN)

◆ DQ_AI201_NAMELEN

#define DQ_AI201_NAMELEN (20)

◆ DQ_AI201_OFFSET

#define DQ_AI201_OFFSET (15.0)

◆ DQ_AI201_OFFSET_10

#define DQ_AI201_OFFSET_10 (DQ_AI201_OFFSET/10)

◆ DQ_AI201_OFFSET_100

#define DQ_AI201_OFFSET_100 (DQ_AI201_OFFSET/100)

◆ DQ_AI201_OFFSET_1000

#define DQ_AI201_OFFSET_1000 (DQ_AI201_OFFSET/1000)

◆ DQ_AI201_OFFSET_2

#define DQ_AI201_OFFSET_2 (DQ_AI201_OFFSET/2)

◆ DQ_AI201_OFFSET_5

#define DQ_AI201_OFFSET_5 (DQ_AI201_OFFSET/5)

◆ DQ_AI201_SPAN

#define DQ_AI201_SPAN (30.0)

◆ DQ_AI201_STEP

#define DQ_AI201_STEP (DQ_AI201_SPAN/0xFFFF)

◆ DQ_AI201_STEP_10

#define DQ_AI201_STEP_10 (DQ_AI201_STEP/10)

◆ DQ_AI201_STEP_100

#define DQ_AI201_STEP_100 (DQ_AI201_STEP/100)

◆ DQ_AI201_STEP_1000

#define DQ_AI201_STEP_1000 (DQ_AI201_STEP/1000)

◆ DQ_AI201_STEP_2

#define DQ_AI201_STEP_2 (DQ_AI201_STEP/2)

◆ DQ_AI201_STEP_5

#define DQ_AI201_STEP_5 (DQ_AI201_STEP/5)

◆ DQ_AI201_VREFS

#define DQ_AI201_VREFS (2)

◆ DQ_AI205_BASE

#define DQ_AI205_BASE (BUS_FREQUENCY)

◆ DQ_AI205_CALDACS

#define DQ_AI205_CALDACS (8)

◆ DQ_AI205_CFILT00

#define DQ_AI205_CFILT00 (0x00)

◆ DQ_AI205_CFILT01

#define DQ_AI205_CFILT01 (0x01)

◆ DQ_AI205_CFILT02

#define DQ_AI205_CFILT02 (0x02)

◆ DQ_AI205_CFILT10

#define DQ_AI205_CFILT10 (0x10)

◆ DQ_AI205_CFILT11

#define DQ_AI205_CFILT11 (0x11)

◆ DQ_AI205_CFILT12

#define DQ_AI205_CFILT12 (0x12)

◆ DQ_AI205_CFILT20

#define DQ_AI205_CFILT20 (0x20)

◆ DQ_AI205_CFILT21

#define DQ_AI205_CFILT21 (0x21)

◆ DQ_AI205_CFILT22

#define DQ_AI205_CFILT22 (0x22)

◆ DQ_AI205_CFILT30

#define DQ_AI205_CFILT30 (0x30)

◆ DQ_AI205_CFILT31

#define DQ_AI205_CFILT31 (0x31)

◆ DQ_AI205_CFILT32

#define DQ_AI205_CFILT32 (0x32)

◆ DQ_AI205_CFILT_CHANFILT

#define DQ_AI205_CFILT_CHANFILT	(	C,
		F
	)	(((C&0x3)<<4)\|(F&0x3))

◆ DQ_AI205_CFILT_GETCHAN

#define DQ_AI205_CFILT_GETCHAN ( D ) ((D & 0xf0)>>4)

◆ DQ_AI205_CFILT_GETFILT

#define DQ_AI205_CFILT_GETFILT ( D ) (D & 0xf)

◆ DQ_AI205_CFILTMINENT

#define DQ_AI205_CFILTMINENT (3)

◆ DQ_AI205_CHAN

#define DQ_AI205_CHAN (4)

◆ DQ_AI205_CHANSVC

#define DQ_AI205_CHANSVC (4)

◆ DQ_AI205_CL_TIMES

#define DQ_AI205_CL_TIMES (2)

◆ DQ_AI205_COEFF_WIDTH

#define DQ_AI205_COEFF_WIDTH (16)

◆ DQ_AI205_DATAFIFO

#define DQ_AI205_DATAFIFO (1)

◆ DQ_AI205_DEFDECR

#define DQ_AI205_DEFDECR (5)

◆ DQ_AI205_FIFO_BUFSZ

#define DQ_AI205_FIFO_BUFSZ (256)

◆ DQ_AI205_FIFO_CH

#define DQ_AI205_FIFO_CH (128)

◆ DQ_AI205_FIFO_COEF

#define DQ_AI205_FIFO_COEF (DQ_FIFO_PUT_COEFF)

◆ DQ_AI205_FIFO_DATA

#define DQ_AI205_FIFO_DATA (DQ_FIFO_SET_DATA)

◆ DQ_AI205_FIFO_GET_DATA

#define DQ_AI205_FIFO_GET_DATA (DQ_FIFO_GET_DATA)

◆ DQ_AI205_FIFO_MODE

#define DQ_AI205_FIFO_MODE (DQ_FIFO_PUT_CUSTOM)

◆ DQ_AI205_FIR_TOTAL

#define DQ_AI205_FIR_TOTAL (1<<(DQ_AI205_COEFF_WIDTH-1))

◆ DQ_AI205_FIRNUM

#define DQ_AI205_FIRNUM (3)

◆ DQ_AI205_GAIN_1

#define DQ_AI205_GAIN_1 (0)

◆ DQ_AI205_GAIN_10

#define DQ_AI205_GAIN_10 (1)

◆ DQ_AI205_GAIN_100

#define DQ_AI205_GAIN_100 (2)

◆ DQ_AI205_GAIN_1000

#define DQ_AI205_GAIN_1000 (3)

◆ DQ_AI205_GAINV_0

#define DQ_AI205_GAINV_0 (1)

◆ DQ_AI205_GAINV_1

#define DQ_AI205_GAINV_1 (10)

◆ DQ_AI205_GAINV_2

#define DQ_AI205_GAINV_2 (100)

◆ DQ_AI205_GAINV_3

#define DQ_AI205_GAINV_3 (1000)

◆ DQ_AI205_INFOSZ

#define DQ_AI205_INFOSZ (DQ_MAX_INFO_SIZE)

◆ DQ_AI205_MAXDECR

#define DQ_AI205_MAXDECR (32)

◆ DQ_AI205_MAXTAPS

#define DQ_AI205_MAXTAPS (128)

◆ DQ_AI205_MODECONT

#define DQ_AI205_MODECONT (DQ_FIFO_MODECONT)

◆ DQ_AI205_MODEFIFO

#define DQ_AI205_MODEFIFO (DQ_FIFO_MODEFIFO)

◆ DQ_AI205_MODESCAN

#define DQ_AI205_MODESCAN (DQ_FIFO_MODESCAN)

◆ DQ_AI205_NAMELEN

#define DQ_AI205_NAMELEN (32)

◆ DQ_AI205_OFFSET

#define DQ_AI205_OFFSET (100.0)

◆ DQ_AI205_OFFSET_10

#define DQ_AI205_OFFSET_10 (DQ_AI205_OFFSET/10)

◆ DQ_AI205_OFFSET_100

#define DQ_AI205_OFFSET_100 (DQ_AI205_OFFSET/100)

◆ DQ_AI205_OFFSET_1000

#define DQ_AI205_OFFSET_1000 (DQ_AI205_OFFSET/1000)

◆ DQ_AI205_OFFSET_1000_801

#define DQ_AI205_OFFSET_1000_801 (DQ_AI205_OFFSET_801/1000)

◆ DQ_AI205_OFFSET_100_801

#define DQ_AI205_OFFSET_100_801 (DQ_AI205_OFFSET_801/100)

◆ DQ_AI205_OFFSET_10_801

#define DQ_AI205_OFFSET_10_801 (DQ_AI205_OFFSET_801/10)

◆ DQ_AI205_OFFSET_801

#define DQ_AI205_OFFSET_801 (4.096)

◆ DQ_AI205_SPAN

#define DQ_AI205_SPAN (200.0)

◆ DQ_AI205_SPAN_801

#define DQ_AI205_SPAN_801 (8.192)

◆ DQ_AI205_STEP

#define DQ_AI205_STEP (DQ_AI205_SPAN/0x3FFFF)

◆ DQ_AI205_STEP16

#define DQ_AI205_STEP16 (DQ_AI205_SPAN/0xFFFF)

◆ DQ_AI205_STEP16_801

#define DQ_AI205_STEP16_801 (DQ_AI205_SPAN_801/0xFFFF)

◆ DQ_AI205_STEP_10

#define DQ_AI205_STEP_10 (DQ_AI205_STEP/10)

◆ DQ_AI205_STEP_100

#define DQ_AI205_STEP_100 (DQ_AI205_STEP/100)

◆ DQ_AI205_STEP_1000

#define DQ_AI205_STEP_1000 (DQ_AI205_STEP/1000)

◆ DQ_AI205_STEP_1000_801

#define DQ_AI205_STEP_1000_801 (DQ_AI205_STEP_801/1000)

◆ DQ_AI205_STEP_100_801

#define DQ_AI205_STEP_100_801 (DQ_AI205_STEP_801/100)

◆ DQ_AI205_STEP_10_801

#define DQ_AI205_STEP_10_801 (DQ_AI205_STEP_801/10)

◆ DQ_AI205_STEP_801

#define DQ_AI205_STEP_801 (DQ_AI205_SPAN_801/0x3FFFF)

◆ DQ_AI205_TSCOPY

#define DQ_AI205_TSCOPY (1L << 18)

◆ DQ_AI207_CHAN

#define DQ_AI207_CHAN (16)

◆ DQ_AI207_CHAN_SE

#define DQ_AI207_CHAN_SE (32)

◆ DQ_AI207_NAMELEN

#define DQ_AI207_NAMELEN (14)

◆ DQ_AI208_ALL_EXCITED

#define DQ_AI208_ALL_EXCITED (1L<<19)

◆ DQ_AI208_BASE

#define DQ_AI208_BASE (BUS_FREQUENCY)

◆ DQ_AI208_CALDACS

#define DQ_AI208_CALDACS (4)

◆ DQ_AI208_CHAN

#define DQ_AI208_CHAN (8)

◆ DQ_AI208_FIFO_GET_DATA

#define DQ_AI208_FIFO_GET_DATA (DQ_FIFO_GET_DATA)

◆ DQ_AI208_GAIN_1

#define DQ_AI208_GAIN_1 (0)

◆ DQ_AI208_GAIN_10

#define DQ_AI208_GAIN_10 (4)

◆ DQ_AI208_GAIN_100

#define DQ_AI208_GAIN_100 (8)

◆ DQ_AI208_GAIN_2

#define DQ_AI208_GAIN_2 (1)

◆ DQ_AI208_GAIN_20

#define DQ_AI208_GAIN_20 (5)

◆ DQ_AI208_GAIN_200

#define DQ_AI208_GAIN_200 (9)

◆ DQ_AI208_GAIN_4

#define DQ_AI208_GAIN_4 (2)

◆ DQ_AI208_GAIN_40

#define DQ_AI208_GAIN_40 (6)

◆ DQ_AI208_GAIN_400

#define DQ_AI208_GAIN_400 (10)

◆ DQ_AI208_GAIN_8

#define DQ_AI208_GAIN_8 (3)

◆ DQ_AI208_GAIN_80

#define DQ_AI208_GAIN_80 (7)

◆ DQ_AI208_GAIN_800

#define DQ_AI208_GAIN_800 (11)

◆ DQ_AI208_GAINS

#define DQ_AI208_GAINS (12)

◆ DQ_AI208_GAINV

#define DQ_AI208_GAINV (1)

◆ DQ_AI208_GAINV_10

#define DQ_AI208_GAINV_10 (DQ_AI208_GAINV*10)

◆ DQ_AI208_GAINV_100

#define DQ_AI208_GAINV_100 (DQ_AI208_GAINV*100)

◆ DQ_AI208_GAINV_2

#define DQ_AI208_GAINV_2 (DQ_AI208_GAINV*2)

◆ DQ_AI208_GAINV_20

#define DQ_AI208_GAINV_20 (DQ_AI208_GAINV*20)

◆ DQ_AI208_GAINV_200

#define DQ_AI208_GAINV_200 (DQ_AI208_GAINV*200)

◆ DQ_AI208_GAINV_4

#define DQ_AI208_GAINV_4 (DQ_AI208_GAINV*4)

◆ DQ_AI208_GAINV_40

#define DQ_AI208_GAINV_40 (DQ_AI208_GAINV*40)

◆ DQ_AI208_GAINV_400

#define DQ_AI208_GAINV_400 (DQ_AI208_GAINV*400)

◆ DQ_AI208_GAINV_8

#define DQ_AI208_GAINV_8 (DQ_AI208_GAINV*8)

◆ DQ_AI208_GAINV_80

#define DQ_AI208_GAINV_80 (DQ_AI208_GAINV*80)

◆ DQ_AI208_GAINV_800

#define DQ_AI208_GAINV_800 (DQ_AI208_GAINV*800)

◆ DQ_AI208_INFOSZ

#define DQ_AI208_INFOSZ (DQ_MAX_INFO_SIZE)

◆ DQ_AI208_MAX_CH_LIST

#define DQ_AI208_MAX_CH_LIST (32)

◆ DQ_AI208_MAXCLFRQ

#define DQ_AI208_MAXCLFRQ (20000)

◆ DQ_AI208_MAXCVFRQ

#define DQ_AI208_MAXCVFRQ (20000)

◆ DQ_AI208_MODECONT

#define DQ_AI208_MODECONT (DQ_FIFO_MODECONT)

◆ DQ_AI208_MODEFIFO

#define DQ_AI208_MODEFIFO (DQ_FIFO_MODEFIFO)

◆ DQ_AI208_MODESCAN

#define DQ_AI208_MODESCAN (DQ_FIFO_MODESCAN)

◆ DQ_AI208_NAMELEN

#define DQ_AI208_NAMELEN (20)

◆ DQ_AI208_OFFSET

#define DQ_AI208_OFFSET (10.0)

◆ DQ_AI208_OFFSET_10

#define DQ_AI208_OFFSET_10 (DQ_AI208_OFFSET/10)

◆ DQ_AI208_OFFSET_100

#define DQ_AI208_OFFSET_100 (DQ_AI208_OFFSET/100)

◆ DQ_AI208_OFFSET_2

#define DQ_AI208_OFFSET_2 (DQ_AI208_OFFSET/2)

◆ DQ_AI208_OFFSET_20

#define DQ_AI208_OFFSET_20 (DQ_AI208_OFFSET/20)

◆ DQ_AI208_OFFSET_200

#define DQ_AI208_OFFSET_200 (DQ_AI208_OFFSET/200)

◆ DQ_AI208_OFFSET_4

#define DQ_AI208_OFFSET_4 (DQ_AI208_OFFSET/4)

◆ DQ_AI208_OFFSET_40

#define DQ_AI208_OFFSET_40 (DQ_AI208_OFFSET/40)

◆ DQ_AI208_OFFSET_400

#define DQ_AI208_OFFSET_400 (DQ_AI208_OFFSET/400)

◆ DQ_AI208_OFFSET_8

#define DQ_AI208_OFFSET_8 (DQ_AI208_OFFSET/8)

◆ DQ_AI208_OFFSET_80

#define DQ_AI208_OFFSET_80 (DQ_AI208_OFFSET/80)

◆ DQ_AI208_OFFSET_800

#define DQ_AI208_OFFSET_800 (DQ_AI208_OFFSET/800)

◆ DQ_AI208_RS

#define DQ_AI208_RS (4990)

◆ DQ_AI208_SHUNT_NOMINAL

#define DQ_AI208_SHUNT_NOMINAL (200000)

◆ DQ_AI208_SHUNT_STEPS

#define DQ_AI208_SHUNT_STEPS (256)

◆ DQ_AI208_SPAN

#define DQ_AI208_SPAN (20.0)

◆ DQ_AI208_STEP

#define DQ_AI208_STEP (DQ_AI208_SPAN/0xFFFF)

◆ DQ_AI208_STEP18

#define DQ_AI208_STEP18 (DQ_AI208_SPAN/0x3FFFF)

◆ DQ_AI208_STEP18_10

#define DQ_AI208_STEP18_10 (DQ_AI208_STEP18/10)

◆ DQ_AI208_STEP18_100

#define DQ_AI208_STEP18_100 (DQ_AI208_STEP18/100)

◆ DQ_AI208_STEP18_2

#define DQ_AI208_STEP18_2 (DQ_AI208_STEP18/2)

◆ DQ_AI208_STEP18_20

#define DQ_AI208_STEP18_20 (DQ_AI208_STEP18/20)

◆ DQ_AI208_STEP18_200

#define DQ_AI208_STEP18_200 (DQ_AI208_STEP18/200)

◆ DQ_AI208_STEP18_4

#define DQ_AI208_STEP18_4 (DQ_AI208_STEP18/4)

◆ DQ_AI208_STEP18_40

#define DQ_AI208_STEP18_40 (DQ_AI208_STEP18/40)

◆ DQ_AI208_STEP18_400

#define DQ_AI208_STEP18_400 (DQ_AI208_STEP18/400)

◆ DQ_AI208_STEP18_8

#define DQ_AI208_STEP18_8 (DQ_AI208_STEP18/8)

◆ DQ_AI208_STEP18_80

#define DQ_AI208_STEP18_80 (DQ_AI208_STEP18/80)

◆ DQ_AI208_STEP18_800

#define DQ_AI208_STEP18_800 (DQ_AI208_STEP18/800)

◆ DQ_AI208_STEP_10

#define DQ_AI208_STEP_10 (DQ_AI208_STEP/10)

◆ DQ_AI208_STEP_100

#define DQ_AI208_STEP_100 (DQ_AI208_STEP/100)

◆ DQ_AI208_STEP_2

#define DQ_AI208_STEP_2 (DQ_AI208_STEP/2)

◆ DQ_AI208_STEP_20

#define DQ_AI208_STEP_20 (DQ_AI208_STEP/20)

◆ DQ_AI208_STEP_200

#define DQ_AI208_STEP_200 (DQ_AI208_STEP/200)

◆ DQ_AI208_STEP_4

#define DQ_AI208_STEP_4 (DQ_AI208_STEP/4)

◆ DQ_AI208_STEP_40

#define DQ_AI208_STEP_40 (DQ_AI208_STEP/40)

◆ DQ_AI208_STEP_400

#define DQ_AI208_STEP_400 (DQ_AI208_STEP/400)

◆ DQ_AI208_STEP_8

#define DQ_AI208_STEP_8 (DQ_AI208_STEP/8)

◆ DQ_AI208_STEP_80

#define DQ_AI208_STEP_80 (DQ_AI208_STEP/80)

◆ DQ_AI208_STEP_800

#define DQ_AI208_STEP_800 (DQ_AI208_STEP/800)

◆ DQ_AI208_VREFS

#define DQ_AI208_VREFS (2)

◆ DQ_AI211_ADC_CLOCK_FACTOR

#define DQ_AI211_ADC_CLOCK_FACTOR (8)

◆ DQ_AI211_BASE

#define DQ_AI211_BASE BUS_FREQUENCY

◆ DQ_AI211_BASE_24MHZ

#define DQ_AI211_BASE_24MHZ (24000000)

◆ DQ_AI211_CAL_SET_0

#define DQ_AI211_CAL_SET_0 (0)

◆ DQ_AI211_CAL_SET_1

#define DQ_AI211_CAL_SET_1 (1)

◆ DQ_AI211_CAL_SET_2

#define DQ_AI211_CAL_SET_2 (2)

◆ DQ_AI211_CAL_SET_3

#define DQ_AI211_CAL_SET_3 (3)

◆ DQ_AI211_CAL_SET_4

#define DQ_AI211_CAL_SET_4 (4)

◆ DQ_AI211_CAL_SET_5

#define DQ_AI211_CAL_SET_5 (5)

◆ DQ_AI211_CAL_SET_6

#define DQ_AI211_CAL_SET_6 (6)

◆ DQ_AI211_CAL_SET_7

#define DQ_AI211_CAL_SET_7 (7)

◆ DQ_AI211_CAL_SETS

#define DQ_AI211_CAL_SETS (8)

◆ DQ_AI211_CAL_SETS1

#define DQ_AI211_CAL_SETS1 (4)

◆ DQ_AI211_CALDACS

#define DQ_AI211_CALDACS (8)

◆ DQ_AI211_CHAN

#define DQ_AI211_CHAN (4)

◆ DQ_AI211_COEFF_WIDTH

#define DQ_AI211_COEFF_WIDTH (20)

◆ DQ_AI211_DEFDECR

#define DQ_AI211_DEFDECR (0)

◆ DQ_AI211_DEFTAPS

#define DQ_AI211_DEFTAPS (254)

◆ DQ_AI211_FIR_TOTAL

#define DQ_AI211_FIR_TOTAL (1<<(DQ_AI211_COEFF_WIDTH-1))

◆ DQ_AI211_GAIN_1

#define DQ_AI211_GAIN_1 (0)

◆ DQ_AI211_GAIN_10

#define DQ_AI211_GAIN_10 (3)

◆ DQ_AI211_GAIN_2

#define DQ_AI211_GAIN_2 (1)

◆ DQ_AI211_GAIN_5

#define DQ_AI211_GAIN_5 (2)

◆ DQ_AI211_GAINS

#define DQ_AI211_GAINS (4)

◆ DQ_AI211_GETCH

#define DQ_AI211_GETCH ( V ) ((V>>28)&3)

◆ DQ_AI211_HEX_TO_V

#define DQ_AI211_HEX_TO_V ( HEX ) (HEX*DQ_AI211_STEP-DQ_AI211_SPAN_V/2)

◆ DQ_AI211_INFOSZ

#define DQ_AI211_INFOSZ DQ_MAX_INFO_SIZE

◆ DQ_AI211_MAXAVG

#define DQ_AI211_MAXAVG (15)

◆ DQ_AI211_MAXDEC

#define DQ_AI211_MAXDEC (16)

◆ DQ_AI211_MAXDECR

#define DQ_AI211_MAXDECR (65536)

◆ DQ_AI211_MAXTAPS

#define DQ_AI211_MAXTAPS (256)

◆ DQ_AI211_MODECONT

#define DQ_AI211_MODECONT (DQ_FIFO_MODECONT)

◆ DQ_AI211_MODEFIFO

#define DQ_AI211_MODEFIFO (DQ_FIFO_MODEFIFO)

◆ DQ_AI211_MODESCAN

#define DQ_AI211_MODESCAN (DQ_FIFO_MODESCAN)

◆ DQ_AI211_NAMELEN

#define DQ_AI211_NAMELEN (32)

◆ DQ_AI211_OFFSET

#define DQ_AI211_OFFSET (25.0)

◆ DQ_AI211_OFFSET_10

#define DQ_AI211_OFFSET_10 (DQ_AI211_OFFSET/10)

◆ DQ_AI211_OFFSET_2

#define DQ_AI211_OFFSET_2 (DQ_AI211_OFFSET/2)

◆ DQ_AI211_OFFSET_5

#define DQ_AI211_OFFSET_5 (DQ_AI211_OFFSET/5)

◆ DQ_AI211_SETS

#define DQ_AI211_SETS (4)

◆ DQ_AI211_SETS1

#define DQ_AI211_SETS1 (4)

◆ DQ_AI211_SPAN

#define DQ_AI211_SPAN (50.0)

◆ DQ_AI211_SPAN_H

#define DQ_AI211_SPAN_H (0xFFFFFF)

◆ DQ_AI211_SPAN_V

#define DQ_AI211_SPAN_V (50.0)

◆ DQ_AI211_STEP

#define DQ_AI211_STEP (DQ_AI211_SPAN_V/DQ_AI211_SPAN_H)

◆ DQ_AI211_STEP16

#define DQ_AI211_STEP16 (DQ_AI211_SPAN/0xFFFF)

◆ DQ_AI211_STEP_10

#define DQ_AI211_STEP_10 (DQ_AI211_STEP/10)

◆ DQ_AI211_STEP_2

#define DQ_AI211_STEP_2 (DQ_AI211_STEP/2)

◆ DQ_AI211_STEP_5

#define DQ_AI211_STEP_5 (DQ_AI211_STEP/5)

◆ DQ_AI217_ADC_CLOCK_FACTOR

#define DQ_AI217_ADC_CLOCK_FACTOR (8.0)

◆ DQ_AI217_BASE

#define DQ_AI217_BASE (BUS_FREQUENCY)

◆ DQ_AI217_CHAN

#define DQ_AI217_CHAN (16)

◆ DQ_AI217_CJC_AVG

#define DQ_AI217_CJC_AVG (0x20)

◆ DQ_AI217_CJC_CHAN

#define DQ_AI217_CJC_CHAN (1)

◆ DQ_AI217_CJC_OFFSET

#define DQ_AI217_CJC_OFFSET (16)

◆ DQ_AI217_COEFF_WIDTH

#define DQ_AI217_COEFF_WIDTH (24)

◆ DQ_AI217_DEFTAPS

#define DQ_AI217_DEFTAPS (128)

◆ DQ_AI217_FIR_BANKS

#define DQ_AI217_FIR_BANKS (4)

◆ DQ_AI217_FIR_COEFF_LOAD

#define DQ_AI217_FIR_COEFF_LOAD (0x4)

◆ DQ_AI217_FIR_DISABLE

#define DQ_AI217_FIR_DISABLE (0x0)

◆ DQ_AI217_FIR_ENABLE

#define DQ_AI217_FIR_ENABLE (0x1)

◆ DQ_AI217_FIR_SET_DECIMATION_RATE

#define DQ_AI217_FIR_SET_DECIMATION_RATE (0x2)

◆ DQ_AI217_FIR_SET_DEFAULT

#define DQ_AI217_FIR_SET_DEFAULT (0x8)

◆ DQ_AI217_FIR_SET_INDEX

#define DQ_AI217_FIR_SET_INDEX (0x80)

◆ DQ_AI217_FIR_TOTAL

#define DQ_AI217_FIR_TOTAL (1<<(DQ_AI217_COEFF_WIDTH-1))

◆ DQ_AI217_GAIN_1

#define DQ_AI217_GAIN_1 (0)

◆ DQ_AI217_GAIN_16

#define DQ_AI217_GAIN_16 (4)

◆ DQ_AI217_GAIN_2

#define DQ_AI217_GAIN_2 (1)

◆ DQ_AI217_GAIN_32

#define DQ_AI217_GAIN_32 (5)

◆ DQ_AI217_GAIN_4

#define DQ_AI217_GAIN_4 (2)

◆ DQ_AI217_GAIN_4_CJC

#define DQ_AI217_GAIN_4_CJC (7)

◆ DQ_AI217_GAIN_64

#define DQ_AI217_GAIN_64 (6)

◆ DQ_AI217_GAIN_8

#define DQ_AI217_GAIN_8 (3)

◆ DQ_AI217_GAINS

#define DQ_AI217_GAINS (8)

◆ DQ_AI217_GAINS_NORM

#define DQ_AI217_GAINS_NORM (7)

◆ DQ_AI217_GET_PARAM_PGA

#define DQ_AI217_GET_PARAM_PGA (0)

◆ DQ_AI217_HEX_TO_V

#define DQ_AI217_HEX_TO_V ( HEX ) (HEX*DQ_AI217_STEP-DQ_AI217_SPAN_V/2)

◆ DQ_AI217_INFOSZ

#define DQ_AI217_INFOSZ (DQ_MAX_INFO_SIZE)

◆ DQ_AI217_MAX_AVG

#define DQ_AI217_MAX_AVG (0x14)

◆ DQ_AI217_MAXCLFRQ

#define DQ_AI217_MAXCLFRQ (29891.30 * 4.0)

◆ DQ_AI217_MAXCLOCL

#define DQ_AI217_MAXCLOCL (DQ_AI217_MAXCLFRQ*4*DQ_AI217_ADC_CLOCK_FACTOR)

◆ DQ_AI217_MAXDECR

#define DQ_AI217_MAXDECR (65536)

◆ DQ_AI217_MAXPLLCLFRQ

#define DQ_AI217_MAXPLLCLFRQ (120000.0)

◆ DQ_AI217_MAXTAPS

#define DQ_AI217_MAXTAPS (128)

◆ DQ_AI217_MINCLOCL

#define DQ_AI217_MINCLOCL (DQ_AI217_MAXCLOCL/2)

◆ DQ_AI217_MINPLLCLFRQ

#define DQ_AI217_MINPLLCLFRQ (100.0)

◆ DQ_AI217_MODECONT

#define DQ_AI217_MODECONT (DQ_FIFO_MODECONT)

◆ DQ_AI217_MODEFIFO

#define DQ_AI217_MODEFIFO (DQ_FIFO_MODEFIFO)

◆ DQ_AI217_MODESCAN

#define DQ_AI217_MODESCAN (DQ_FIFO_MODESCAN)

◆ DQ_AI217_NAMELEN

#define DQ_AI217_NAMELEN (32)

◆ DQ_AI217_OFFSET

#define DQ_AI217_OFFSET (10.0)

◆ DQ_AI217_OFFSET_16

#define DQ_AI217_OFFSET_16 (DQ_AI217_OFFSET/16.0)

◆ DQ_AI217_OFFSET_2

#define DQ_AI217_OFFSET_2 (DQ_AI217_OFFSET/2.0)

◆ DQ_AI217_OFFSET_32

#define DQ_AI217_OFFSET_32 (DQ_AI217_OFFSET/32.0)

◆ DQ_AI217_OFFSET_4

#define DQ_AI217_OFFSET_4 (DQ_AI217_OFFSET/4.0)

◆ DQ_AI217_OFFSET_4_CJC

#define DQ_AI217_OFFSET_4_CJC (0.0)

◆ DQ_AI217_OFFSET_64

#define DQ_AI217_OFFSET_64 (DQ_AI217_OFFSET/64.0)

◆ DQ_AI217_OFFSET_8

#define DQ_AI217_OFFSET_8 (DQ_AI217_OFFSET/8.0)

◆ DQ_AI217_PGAERR_BUFA

#define DQ_AI217_PGAERR_BUFA (1UL<<5)

◆ DQ_AI217_PGAERR_CHKERR

#define DQ_AI217_PGAERR_CHKERR (1UL<<7)

◆ DQ_AI217_PGAERR_ERRFLAG

#define DQ_AI217_PGAERR_ERRFLAG (1UL<<3)

◆ DQ_AI217_PGAERR_GAINERR

#define DQ_AI217_PGAERR_GAINERR (1UL<<1)

◆ DQ_AI217_PGAERR_IARERR

#define DQ_AI217_PGAERR_IARERR (1UL<<6)

◆ DQ_AI217_PGAERR_ICAERR

#define DQ_AI217_PGAERR_ICAERR (1UL<<4)

◆ DQ_AI217_PGAERR_IOVERR

#define DQ_AI217_PGAERR_IOVERR (1UL<<0)

◆ DQ_AI217_PGAERR_OUTERR

#define DQ_AI217_PGAERR_OUTERR (1UL<<2)

◆ DQ_AI217_SEL_QFIR_A

#define DQ_AI217_SEL_QFIR_A (0x01)

◆ DQ_AI217_SEL_QFIR_ALL

#define DQ_AI217_SEL_QFIR_ALL (0x0f)

◆ DQ_AI217_SEL_QFIR_B

#define DQ_AI217_SEL_QFIR_B (0x02)

◆ DQ_AI217_SEL_QFIR_C

#define DQ_AI217_SEL_QFIR_C (0x04)

◆ DQ_AI217_SEL_QFIR_D

#define DQ_AI217_SEL_QFIR_D (0x08)

◆ DQ_AI217_SET_CJC_AVG

#define DQ_AI217_SET_CJC_AVG (0x100)

◆ DQ_AI217_SNAP_FREQ

#define DQ_AI217_SNAP_FREQ (7500.0)

◆ DQ_AI217_SPAN

#define DQ_AI217_SPAN (20.0)

◆ DQ_AI217_SPAN_H

#define DQ_AI217_SPAN_H (0xFFFFFF)

◆ DQ_AI217_SPAN_V

#define DQ_AI217_SPAN_V (20.0)

◆ DQ_AI217_STARTRATE

#define DQ_AI217_STARTRATE (DQ_AI217_BASE/1000-1)

◆ DQ_AI217_STEP

#define DQ_AI217_STEP (DQ_AI217_SPAN_V/DQ_AI217_SPAN_H)

◆ DQ_AI217_STEP_16

#define DQ_AI217_STEP_16 (DQ_AI217_STEP/16.0)

◆ DQ_AI217_STEP_2

#define DQ_AI217_STEP_2 (DQ_AI217_STEP/2.0)

◆ DQ_AI217_STEP_32

#define DQ_AI217_STEP_32 (DQ_AI217_STEP/32.0)

◆ DQ_AI217_STEP_4

#define DQ_AI217_STEP_4 (DQ_AI217_STEP/4.0)

◆ DQ_AI217_STEP_4_CJC

#define DQ_AI217_STEP_4_CJC (DQ_AI217_STEP/4.0)

◆ DQ_AI217_STEP_64

#define DQ_AI217_STEP_64 (DQ_AI217_STEP/64.0)

◆ DQ_AI217_STEP_8

#define DQ_AI217_STEP_8 (DQ_AI217_STEP/8.0)

◆ DQ_AI224_ANULL_FACTOR

#define DQ_AI224_ANULL_FACTOR ( G )

Value:

((G==DQ_AI224_GAIN_1)?4.0: \
                                    (G==DQ_AI224_GAIN_2)?4.0: \
                                    (G==DQ_AI224_GAIN_80)?0.5: \
                                    (G==DQ_AI224_GAIN_100)?0.2: \
                                    (G==DQ_AI224_GAIN_200)?0.2: \
                                    (G==DQ_AI224_GAIN_400)?0.1:1.0)

◆ DQ_AI224_AVG_FLAG

#define DQ_AI224_AVG_FLAG (0x4)

◆ DQ_AI224_BASE

#define DQ_AI224_BASE BUS_FREQUENCY

◆ DQ_AI224_BASE_28MHZ

#define DQ_AI224_BASE_28MHZ (28160000)

◆ DQ_AI224_CALCHAN

#define DQ_AI224_CALCHAN (8)

◆ DQ_AI224_CALDACS

#define DQ_AI224_CALDACS (0)

◆ DQ_AI224_CHAN

#define DQ_AI224_CHAN (4)

◆ DQ_AI224_COEFF_WIDTH

#define DQ_AI224_COEFF_WIDTH (16)

◆ DQ_AI224_CUST_FIR0

#define DQ_AI224_CUST_FIR0 (0)

◆ DQ_AI224_CUST_FIR1

#define DQ_AI224_CUST_FIR1 (1)

◆ DQ_AI224_DAC_CAL_MULTIPLIER

#define DQ_AI224_DAC_CAL_MULTIPLIER (53687)

◆ DQ_AI224_DAC_CAL_SHIFT

#define DQ_AI224_DAC_CAL_SHIFT (14)

◆ DQ_AI224_DACS

#define DQ_AI224_DACS (4)

◆ DQ_AI224_DEF_FIR0

#define DQ_AI224_DEF_FIR0 (0xe)

◆ DQ_AI224_DEF_FIR1

#define DQ_AI224_DEF_FIR1 (0xf)

◆ DQ_AI224_ENABLE_EXC_A

#define DQ_AI224_ENABLE_EXC_A (1L<<0)

◆ DQ_AI224_ENABLE_EXC_B

#define DQ_AI224_ENABLE_EXC_B (1L<<1)

◆ DQ_AI224_EXC_RMS_DEFAULT

#define DQ_AI224_EXC_RMS_DEFAULT (0x1f0000)

◆ DQ_AI224_FIFO_GET_DATA

#define DQ_AI224_FIFO_GET_DATA (DQ_FIFO_GET_DATA)

◆ DQ_AI224_FIR_COEFF_LOAD

#define DQ_AI224_FIR_COEFF_LOAD (0x4)

◆ DQ_AI224_FIR_DISABLE

#define DQ_AI224_FIR_DISABLE (0x0)

◆ DQ_AI224_FIR_ENABLE

#define DQ_AI224_FIR_ENABLE (0x1)

◆ DQ_AI224_FIR_SET_DECRATE

#define DQ_AI224_FIR_SET_DECRATE (0x2)

◆ DQ_AI224_FIR_SET_DEFAULT

#define DQ_AI224_FIR_SET_DEFAULT (0x8)

◆ DQ_AI224_FIR_STAGES

#define DQ_AI224_FIR_STAGES (2)

◆ DQ_AI224_FIR_TOTAL

#define DQ_AI224_FIR_TOTAL (1<<(DQ_AI224_COEFF_WIDTH-1))

◆ DQ_AI224_GAIN_1

#define DQ_AI224_GAIN_1 (0)

◆ DQ_AI224_GAIN_100

#define DQ_AI224_GAIN_100 (7)

◆ DQ_AI224_GAIN_2

#define DQ_AI224_GAIN_2 (1)

◆ DQ_AI224_GAIN_20

#define DQ_AI224_GAIN_20 (4)

◆ DQ_AI224_GAIN_200

#define DQ_AI224_GAIN_200 (8)

◆ DQ_AI224_GAIN_4

#define DQ_AI224_GAIN_4 (2)

◆ DQ_AI224_GAIN_40

#define DQ_AI224_GAIN_40 (5)

◆ DQ_AI224_GAIN_400

#define DQ_AI224_GAIN_400 (9)

◆ DQ_AI224_GAIN_8

#define DQ_AI224_GAIN_8 (3)

◆ DQ_AI224_GAIN_80

#define DQ_AI224_GAIN_80 (6)

◆ DQ_AI224_GAINS

#define DQ_AI224_GAINS (DQ_AI224_GAIN_400+1)

◆ DQ_AI224_GAINV_0

#define DQ_AI224_GAINV_0 (1)

◆ DQ_AI224_GAINV_1

#define DQ_AI224_GAINV_1 (2)

◆ DQ_AI224_GAINV_2

#define DQ_AI224_GAINV_2 (4)

◆ DQ_AI224_GAINV_3

#define DQ_AI224_GAINV_3 (8)

◆ DQ_AI224_GAINV_4

#define DQ_AI224_GAINV_4 (20)

◆ DQ_AI224_GAINV_5

#define DQ_AI224_GAINV_5 (40)

◆ DQ_AI224_GAINV_6

#define DQ_AI224_GAINV_6 (80)

◆ DQ_AI224_GAINV_7

#define DQ_AI224_GAINV_7 (100)

◆ DQ_AI224_GAINV_8

#define DQ_AI224_GAINV_8 (200)

◆ DQ_AI224_GAINV_9

#define DQ_AI224_GAINV_9 (400)

◆ DQ_AI224_INFOSZ

#define DQ_AI224_INFOSZ DQ_MAX_INFO_SIZE

◆ DQ_AI224_MAX_CH_LIST

#define DQ_AI224_MAX_CH_LIST (DQ_AI224_CHAN*2)

◆ DQ_AI224_MAX_DIV

#define DQ_AI224_MAX_DIV (99)

◆ DQ_AI224_MAX_DIV2

#define DQ_AI224_MAX_DIV2 (199)

◆ DQ_AI224_MAX_DIV3

#define DQ_AI224_MAX_DIV3 (329)

◆ DQ_AI224_MAX_FRQ

#define DQ_AI224_MAX_FRQ (600000)

◆ DQ_AI224_MAX_PTS_PERIOD

#define DQ_AI224_MAX_PTS_PERIOD (256)

◆ DQ_AI224_MAXAVG

#define DQ_AI224_MAXAVG (0x14)

◆ DQ_AI224_MAXCLFRQ

#define DQ_AI224_MAXCLFRQ (600000)

◆ DQ_AI224_MAXCVFRQ

#define DQ_AI224_MAXCVFRQ (600000)

◆ DQ_AI224_MAXDECR

#define DQ_AI224_MAXDECR (0x7ff)

◆ DQ_AI224_MAXTAPS0

#define DQ_AI224_MAXTAPS0 (0x60)

◆ DQ_AI224_MAXTAPS1

#define DQ_AI224_MAXTAPS1 (0x1a0)

◆ DQ_AI224_MIN_SAMPLE_RATE

#define DQ_AI224_MIN_SAMPLE_RATE (586.0)

◆ DQ_AI224_MODECONT

#define DQ_AI224_MODECONT (DQ_FIFO_MODECONT)

◆ DQ_AI224_MODEFIFO

#define DQ_AI224_MODEFIFO (DQ_FIFO_MODEFIFO)

◆ DQ_AI224_MODESCAN

#define DQ_AI224_MODESCAN (DQ_FIFO_MODESCAN)

◆ DQ_AI224_MUX_5K

#define DQ_AI224_MUX_5K (0x70)

◆ DQ_AI224_MUX_CS

#define DQ_AI224_MUX_CS (0x10)

◆ DQ_AI224_MUX_EXCN

#define DQ_AI224_MUX_EXCN (0x60)

◆ DQ_AI224_MUX_EXCP

#define DQ_AI224_MUX_EXCP (0x20)

◆ DQ_AI224_MUX_NULL

#define DQ_AI224_MUX_NULL (0x40)

◆ DQ_AI224_MUX_PPS

#define DQ_AI224_MUX_PPS (0x30)

◆ DQ_AI224_MUX_PS

#define DQ_AI224_MUX_PS (0x50)

◆ DQ_AI224_MUX_SS

#define DQ_AI224_MUX_SS (0x00)

◆ DQ_AI224_NAMELEN

#define DQ_AI224_NAMELEN (20)

◆ DQ_AI224_OFFSET

#define DQ_AI224_OFFSET (10.0)

◆ DQ_AI224_OFFSET_100

#define DQ_AI224_OFFSET_100 (DQ_AI224_OFFSET/100)

◆ DQ_AI224_OFFSET_2

#define DQ_AI224_OFFSET_2 (DQ_AI224_OFFSET/2)

◆ DQ_AI224_OFFSET_20

#define DQ_AI224_OFFSET_20 (DQ_AI224_OFFSET/20)

◆ DQ_AI224_OFFSET_200

#define DQ_AI224_OFFSET_200 (DQ_AI224_OFFSET/200)

◆ DQ_AI224_OFFSET_4

#define DQ_AI224_OFFSET_4 (DQ_AI224_OFFSET/4)

◆ DQ_AI224_OFFSET_40

#define DQ_AI224_OFFSET_40 (DQ_AI224_OFFSET/40)

◆ DQ_AI224_OFFSET_400

#define DQ_AI224_OFFSET_400 (DQ_AI224_OFFSET/400)

◆ DQ_AI224_OFFSET_8

#define DQ_AI224_OFFSET_8 (DQ_AI224_OFFSET/8)

◆ DQ_AI224_OFFSET_80

#define DQ_AI224_OFFSET_80 (DQ_AI224_OFFSET/80)

◆ DQ_AI224_PT_PT_ADC_RATE

#define DQ_AI224_PT_PT_ADC_RATE (512000.0)

◆ DQ_AI224_RS

#define DQ_AI224_RS (4990)

◆ DQ_AI224_SEL_CHAN_0

#define DQ_AI224_SEL_CHAN_0 (0x01)

◆ DQ_AI224_SEL_CHAN_1

#define DQ_AI224_SEL_CHAN_1 (0x02)

◆ DQ_AI224_SEL_CHAN_2

#define DQ_AI224_SEL_CHAN_2 (0x04)

◆ DQ_AI224_SEL_CHAN_3

#define DQ_AI224_SEL_CHAN_3 (0x08)

◆ DQ_AI224_SEL_CHAN_ALL

#define DQ_AI224_SEL_CHAN_ALL (0x0f)

◆ DQ_AI224_SET_AC_EXC

#define DQ_AI224_SET_AC_EXC (2)

◆ DQ_AI224_SET_BCOMP

#define DQ_AI224_SET_BCOMP (3)

◆ DQ_AI224_SET_CHAN

#define DQ_AI224_SET_CHAN	(	M,
		N
	)	(((M))\|((N)&0x7))

◆ DQ_AI224_SET_DC_EXC

#define DQ_AI224_SET_DC_EXC (1)

◆ DQ_AI224_SET_NULL

#define DQ_AI224_SET_NULL (4)

◆ DQ_AI224_SHUNT_A

#define DQ_AI224_SHUNT_A (2)

◆ DQ_AI224_SHUNT_B

#define DQ_AI224_SHUNT_B (3)

◆ DQ_AI224_SHUNT_DISABLED

#define DQ_AI224_SHUNT_DISABLED (0)

◆ DQ_AI224_SHUNT_FREQ

#define DQ_AI224_SHUNT_FREQ (100000)

◆ DQ_AI224_SHUNT_NOMINAL

#define DQ_AI224_SHUNT_NOMINAL (200000)

◆ DQ_AI224_SHUNT_STEPS

#define DQ_AI224_SHUNT_STEPS (256)

◆ DQ_AI224_SPAN

#define DQ_AI224_SPAN (20.0)

◆ DQ_AI224_STEP

#define DQ_AI224_STEP (DQ_AI224_SPAN/0xFFFF)

◆ DQ_AI224_STEP18

#define DQ_AI224_STEP18 (DQ_AI224_SPAN/0x3FFFF)

◆ DQ_AI224_STEP18_100

#define DQ_AI224_STEP18_100 (DQ_AI224_STEP18/100)

◆ DQ_AI224_STEP18_2

#define DQ_AI224_STEP18_2 (DQ_AI224_STEP18/2)

◆ DQ_AI224_STEP18_20

#define DQ_AI224_STEP18_20 (DQ_AI224_STEP18/20)

◆ DQ_AI224_STEP18_200

#define DQ_AI224_STEP18_200 (DQ_AI224_STEP18/200)

◆ DQ_AI224_STEP18_4

#define DQ_AI224_STEP18_4 (DQ_AI224_STEP18/4)

◆ DQ_AI224_STEP18_40

#define DQ_AI224_STEP18_40 (DQ_AI224_STEP18/40)

◆ DQ_AI224_STEP18_400

#define DQ_AI224_STEP18_400 (DQ_AI224_STEP18/400)

◆ DQ_AI224_STEP18_8

#define DQ_AI224_STEP18_8 (DQ_AI224_STEP18/8)

◆ DQ_AI224_STEP18_80

#define DQ_AI224_STEP18_80 (DQ_AI224_STEP18/80)

◆ DQ_AI224_TAPMASK0

#define DQ_AI224_TAPMASK0 (0x7f)

◆ DQ_AI224_TAPMASK1

#define DQ_AI224_TAPMASK1 (0x1FF)

◆ DQ_AI224_V_R5K

#define DQ_AI224_V_R5K (0x3)

◆ DQ_AI224_V_SHUNT_A

#define DQ_AI224_V_SHUNT_A (0x1)

◆ DQ_AI224_V_SHUNT_B

#define DQ_AI224_V_SHUNT_B (0x2)

◆ DQ_AI224_VREFS

#define DQ_AI224_VREFS (0)

◆ DQ_AI224_WFAVG

#define DQ_AI224_WFAVG (16)

◆ DQ_AI224_ZERO_LEVEL

#define DQ_AI224_ZERO_LEVEL (0x8000)

◆ DQ_AI225_BASE

#define DQ_AI225_BASE BUS_FREQUENCY

◆ DQ_AI225_CALLEVEL

#define DQ_AI225_CALLEVEL 1024000000

◆ DQ_AI225_CHAN

#define DQ_AI225_CHAN (26)

◆ DQ_AI225_CHAN_

#define DQ_AI225_CHAN_ ( SM ) (((SM)&(1L<<DQ_AI225_TS_CHAN))?(DQ_AI225_CHAN+1):(DQ_AI225_CHAN))

◆ DQ_AI225_CL_TIMES

#define DQ_AI225_CL_TIMES 2

◆ DQ_AI225_CLENTRIES_DEF

#define DQ_AI225_CLENTRIES_DEF 1

◆ DQ_AI225_CLGETSPD

#define DQ_AI225_CLGETSPD ( L ) ((L&0xf000)>>12)

◆ DQ_AI225_CLPERINT

#define DQ_AI225_CLPERINT 16

◆ DQ_AI225_CLSETSPD

#define DQ_AI225_CLSETSPD ( S ) ((S&0xf)<<12)

◆ DQ_AI225_CLSPDMASK

#define DQ_AI225_CLSPDMASK (0xf000)

◆ DQ_AI225_FIFO_BUFSZ

#define DQ_AI225_FIFO_BUFSZ 16

◆ DQ_AI225_FIFO_CH

#define DQ_AI225_FIFO_CH 128

◆ DQ_AI225_FIFO_GET_CAL

#define DQ_AI225_FIFO_GET_CAL DQ_FIFO_GET_CAL

◆ DQ_AI225_FIFO_GET_DATA

#define DQ_AI225_FIFO_GET_DATA DQ_FIFO_GET_DATA

◆ DQ_AI225_GAIN_1

#define DQ_AI225_GAIN_1 0

◆ DQ_AI225_INFOSZ

#define DQ_AI225_INFOSZ DQ_MAX_INFO_SIZE

◆ DQ_AI225_MAXCHAN

#define DQ_AI225_MAXCHAN 128

◆ DQ_AI225_MAXRATE

#define DQ_AI225_MAXRATE 3200

◆ DQ_AI225_MODECONT

#define DQ_AI225_MODECONT (DQ_FIFO_MODECONT)

◆ DQ_AI225_MODEFIFO

#define DQ_AI225_MODEFIFO (DQ_FIFO_MODEFIFO)

◆ DQ_AI225_MODESCAN

#define DQ_AI225_MODESCAN (DQ_FIFO_MODESCAN)

◆ DQ_AI225_NAMELEN

#define DQ_AI225_NAMELEN (16)

◆ DQ_AI225_OFFSET

#define DQ_AI225_OFFSET (1.25)

◆ DQ_AI225_SPAN

#define DQ_AI225_SPAN (2.5)

◆ DQ_AI225_STEP

#define DQ_AI225_STEP (DQ_AI225_SPAN/(double)0xffffff)

◆ DQ_AI225_TS_CHAN

#define DQ_AI225_TS_CHAN (26)

◆ DQ_AI225BINRANGE

#define DQ_AI225BINRANGE 0xffffff

◆ DQ_AI225HALFRANGE

#define DQ_AI225HALFRANGE 1.25

◆ DQ_AI225ONEVOLTNV

#define DQ_AI225ONEVOLTNV 1000000000

◆ DQ_AI225RANGE

#define DQ_AI225RANGE 2.5

◆ DQ_AI254_ADCS

#define DQ_AI254_ADCS 2

◆ DQ_AI254_AMP2RMS

#define DQ_AI254_AMP2RMS (1.414213562)

◆ DQ_AI254_AOUT0_WR

#define DQ_AI254_AOUT0_WR (0x60)

◆ DQ_AI254_AOUT1_WR

#define DQ_AI254_AOUT1_WR (0x70)

◆ DQ_AI254_AOUT2_WR

#define DQ_AI254_AOUT2_WR (0x80)

◆ DQ_AI254_AOUT3_WR

#define DQ_AI254_AOUT3_WR (0x90)

◆ DQ_AI254_AVG

#define DQ_AI254_AVG (0x20)

◆ DQ_AI254_BASE

#define DQ_AI254_BASE BUS_FREQUENCY

◆ DQ_AI254_CALCHAN

#define DQ_AI254_CALCHAN 8

◆ DQ_AI254_CALDACS

#define DQ_AI254_CALDACS 0

◆ DQ_AI254_CHAN

#define DQ_AI254_CHAN 4

◆ DQ_AI254_CHNUM

#define DQ_AI254_CHNUM (0x3)

◆ DQ_AI254_CHTYPE

#define DQ_AI254_CHTYPE (0xf8)

◆ DQ_AI254_CLOCK24

#define DQ_AI254_CLOCK24 24000000

◆ DQ_AI254_CLOCK33

#define DQ_AI254_CLOCK33 33000000

◆ DQ_AI254_DACS

#define DQ_AI254_DACS 4

◆ DQ_AI254_DIV_CAL

#define DQ_AI254_DIV_CAL (0x00)

◆ DQ_AI254_DIV_RAW

#define DQ_AI254_DIV_RAW (0x10)

◆ DQ_AI254_ENABLE_EXC_A

#define DQ_AI254_ENABLE_EXC_A (1L<<0)

◆ DQ_AI254_ENABLE_EXC_B

#define DQ_AI254_ENABLE_EXC_B (1L<<1)

◆ DQ_AI254_EXC_OFFSET

#define DQ_AI254_EXC_OFFSET (10.0)

◆ DQ_AI254_EXC_RMS_DEFAULT

#define DQ_AI254_EXC_RMS_DEFAULT 0x1f0000

◆ DQ_AI254_EXC_SPAN

#define DQ_AI254_EXC_SPAN (20.0)

◆ DQ_AI254_EXC_STEP

#define DQ_AI254_EXC_STEP (DQ_AI254_EXC_SPAN/0xFFFF)

◆ DQ_AI254_FFIFO

#define DQ_AI254_FFIFO (0x50)

◆ DQ_AI254_FIFO_GET_DATA

#define DQ_AI254_FIFO_GET_DATA DQ_FIFO_GET_DATA

◆ DQ_AI254_GAIN_1

#define DQ_AI254_GAIN_1 0

◆ DQ_AI254_GAIN_10

#define DQ_AI254_GAIN_10 3

◆ DQ_AI254_GAIN_2

#define DQ_AI254_GAIN_2 1

◆ DQ_AI254_GAIN_4

#define DQ_AI254_GAIN_4 2

◆ DQ_AI254_GAIN_5

#define DQ_AI254_GAIN_5 2

◆ DQ_AI254_GAIN_8

#define DQ_AI254_GAIN_8 3

◆ DQ_AI254_GAIN_A

#define DQ_AI254_GAIN_A (0x00)

◆ DQ_AI254_GAIN_B

#define DQ_AI254_GAIN_B (0x10)

◆ DQ_AI254_GAINS

#define DQ_AI254_GAINS 4

◆ DQ_AI254_GAINV

#define DQ_AI254_GAINV 1

◆ DQ_AI254_GAINV_10

#define DQ_AI254_GAINV_10 (DQ_AI254_GAINV*10)

◆ DQ_AI254_GAINV_2

#define DQ_AI254_GAINV_2 (DQ_AI254_GAINV*2)

◆ DQ_AI254_GAINV_5

#define DQ_AI254_GAINV_5 (DQ_AI254_GAINV*5)

◆ DQ_AI254_INFOSZ

#define DQ_AI254_INFOSZ DQ_MAX_INFO_SIZE

◆ DQ_AI254_LAST_A

#define DQ_AI254_LAST_A (0x40)

◆ DQ_AI254_LAST_B

#define DQ_AI254_LAST_B (0x50)

◆ DQ_AI254_LAST_Sa

#define DQ_AI254_LAST_Sa (0x60)

◆ DQ_AI254_LAST_Sb

#define DQ_AI254_LAST_Sb (0x70)

◆ DQ_AI254_MAX_A

#define DQ_AI254_MAX_A (0x48)

◆ DQ_AI254_MAX_B

#define DQ_AI254_MAX_B (0x58)

◆ DQ_AI254_MAX_CH_LIST

#define DQ_AI254_MAX_CH_LIST 32

◆ DQ_AI254_MAX_DIV

#define DQ_AI254_MAX_DIV 99

◆ DQ_AI254_MAX_DIV2

#define DQ_AI254_MAX_DIV2 199

◆ DQ_AI254_MAX_DIV3

#define DQ_AI254_MAX_DIV3 329

◆ DQ_AI254_MAX_FRQ

#define DQ_AI254_MAX_FRQ 330000

◆ DQ_AI254_MAX_FRQ_SMOKE_TEST

#define DQ_AI254_MAX_FRQ_SMOKE_TEST 22000.0

◆ DQ_AI254_MAX_PTS_PERIOD

#define DQ_AI254_MAX_PTS_PERIOD 256

◆ DQ_AI254_MAXCLFRQ

#define DQ_AI254_MAXCLFRQ 20000

◆ DQ_AI254_MAXCVFRQ2

#define DQ_AI254_MAXCVFRQ2 640000

◆ DQ_AI254_MAXCVFRQ4

#define DQ_AI254_MAXCVFRQ4 320000

◆ DQ_AI254_MIN_A

#define DQ_AI254_MIN_A (0x68)

◆ DQ_AI254_MIN_B

#define DQ_AI254_MIN_B (0x78)

◆ DQ_AI254_MIN_FRQ_SMOKE_TEST

#define DQ_AI254_MIN_FRQ_SMOKE_TEST 350.0

◆ DQ_AI254_MINCLFRQ

#define DQ_AI254_MINCLFRQ 400

◆ DQ_AI254_MODE_EXT_4

#define DQ_AI254_MODE_EXT_4 3

◆ DQ_AI254_MODE_EXT_5

#define DQ_AI254_MODE_EXT_5 2

◆ DQ_AI254_MODE_INT_4

#define DQ_AI254_MODE_INT_4 1

◆ DQ_AI254_MODE_INT_5

#define DQ_AI254_MODE_INT_5 0

◆ DQ_AI254_MODE_SETAVG

#define DQ_AI254_MODE_SETAVG (1L<<0)

◆ DQ_AI254_MODE_SETMMAVG

#define DQ_AI254_MODE_SETMMAVG (1L<<1)

◆ DQ_AI254_MODE_SETZEROC

#define DQ_AI254_MODE_SETZEROC (1L<<2)

◆ DQ_AI254_MODE_SIM_4

#define DQ_AI254_MODE_SIM_4 5

◆ DQ_AI254_MODE_SIM_5

#define DQ_AI254_MODE_SIM_5 4

◆ DQ_AI254_MODE_USE_SXAVG

#define DQ_AI254_MODE_USE_SXAVG (1L<<30)

◆ DQ_AI254_MODE_USEREFB

#define DQ_AI254_MODE_USEREFB (1L<<16)

◆ DQ_AI254_MODECONT

#define DQ_AI254_MODECONT (DQ_FIFO_MODECONT)

◆ DQ_AI254_MODEFIFO

#define DQ_AI254_MODEFIFO (DQ_FIFO_MODEFIFO)

◆ DQ_AI254_MODESCAN

#define DQ_AI254_MODESCAN (DQ_FIFO_MODESCAN)

◆ DQ_AI254_NAMELEN

#define DQ_AI254_NAMELEN 20

◆ DQ_AI254_OFFSET

#define DQ_AI254_OFFSET (40.0)

◆ DQ_AI254_PHASE_A

#define DQ_AI254_PHASE_A (0x20)

◆ DQ_AI254_PHASE_AUTO

#define DQ_AI254_PHASE_AUTO (0x40)

◆ DQ_AI254_PHASE_B

#define DQ_AI254_PHASE_B (0x30)

◆ DQ_AI254_SPAN

#define DQ_AI254_SPAN (80.0)

◆ DQ_AI254_STATUS

#define DQ_AI254_STATUS (0x18)

◆ DQ_AI254_STEP

#define DQ_AI254_STEP (DQ_AI254_SPAN/0xFFFF)

◆ DQ_AI254_STEP16

#define DQ_AI254_STEP16 (DQ_AI254_SPAN/0xFFFF)

◆ DQ_AI254_STEP_10

#define DQ_AI254_STEP_10 (DQ_AI254_STEP/10)

◆ DQ_AI254_STEP_2

#define DQ_AI254_STEP_2 (DQ_AI254_STEP/2)

◆ DQ_AI254_STEP_5

#define DQ_AI254_STEP_5 (DQ_AI254_STEP/5)

◆ DQ_AI254_SUM2RMS

#define DQ_AI254_SUM2RMS (1.114303027)

◆ DQ_AI254_USRGAIN_1

#define DQ_AI254_USRGAIN_1 0x800000

◆ DQ_AI254_USROFFS_1

#define DQ_AI254_USROFFS_1 0x0

◆ DQ_AI254_VREFS

#define DQ_AI254_VREFS 0

◆ DQ_AI254_WFAVG

#define DQ_AI254_WFAVG 16

◆ DQ_AI254_ZC

#define DQ_AI254_ZC (0x30)

◆ DQ_AI254_ZERO_LEVEL

#define DQ_AI254_ZERO_LEVEL 0x8000

◆ DQ_AI255_360

#define DQ_AI255_360 0x19228

◆ DQ_AI255_ACC_LIM

#define DQ_AI255_ACC_LIM (DQ_AI255_360>>1)

◆ DQ_AI255_ACCEL_CAL

#define DQ_AI255_ACCEL_CAL (0x10)

◆ DQ_AI255_ADCS

#define DQ_AI255_ADCS 4

◆ DQ_AI255_AMPL

#define DQ_AI255_AMPL (40.0)

◆ DQ_AI255_ANGLE_CAL

#define DQ_AI255_ANGLE_CAL (0x00)

◆ DQ_AI255_AOUT0_WR

#define DQ_AI255_AOUT0_WR (0x30)

◆ DQ_AI255_AOUT1_WR

#define DQ_AI255_AOUT1_WR (0x40)

◆ DQ_AI255_AOUT2_WR

#define DQ_AI255_AOUT2_WR (0x50)

◆ DQ_AI255_AOUT3_WR

#define DQ_AI255_AOUT3_WR (0x60)

◆ DQ_AI255_AOUT_FFCMD_GA

#define DQ_AI255_AOUT_FFCMD_GA (4L<<28)

◆ DQ_AI255_AOUT_FFCMD_GB

#define DQ_AI255_AOUT_FFCMD_GB (5L<<28)

◆ DQ_AI255_AOUT_FFCMD_GC

#define DQ_AI255_AOUT_FFCMD_GC (6L<<28)

◆ DQ_AI255_AOUT_FFCMD_GD

#define DQ_AI255_AOUT_FFCMD_GD (7L<<28)

◆ DQ_AI255_AOUT_FFCMD_PHA

#define DQ_AI255_AOUT_FFCMD_PHA (0L<<28)

◆ DQ_AI255_AOUT_FFCMD_PHB

#define DQ_AI255_AOUT_FFCMD_PHB (1L<<28)

◆ DQ_AI255_AOUT_FFCMD_PHC

#define DQ_AI255_AOUT_FFCMD_PHC (2L<<28)

◆ DQ_AI255_AOUT_FFCMD_PHD

#define DQ_AI255_AOUT_FFCMD_PHD (3L<<28)

◆ DQ_AI255_AOUT_FFCMD_WZ

#define DQ_AI255_AOUT_FFCMD_WZ (8L<<28)

◆ DQ_AI255_BASE

#define DQ_AI255_BASE BUS_FREQUENCY

◆ DQ_AI255_CALCHAN

#define DQ_AI255_CALCHAN 8

◆ DQ_AI255_CALDACS

#define DQ_AI255_CALDACS 0

◆ DQ_AI255_CHAN

#define DQ_AI255_CHAN 2

◆ DQ_AI255_CHANNEL_A

#define DQ_AI255_CHANNEL_A 0

◆ DQ_AI255_CHANNEL_B

#define DQ_AI255_CHANNEL_B 1

◆ DQ_AI255_CHANNEL_C

#define DQ_AI255_CHANNEL_C 2

◆ DQ_AI255_CHANNEL_D

#define DQ_AI255_CHANNEL_D 3

◆ DQ_AI255_CHTYPE

#define DQ_AI255_CHTYPE (0xfc)

◆ DQ_AI255_CLOCK24

#define DQ_AI255_CLOCK24 24000000

◆ DQ_AI255_CLOCK33

#define DQ_AI255_CLOCK33 33000000

◆ DQ_AI255_COIL_X

#define DQ_AI255_COIL_X ( D ) (-(D)-30)

◆ DQ_AI255_COIL_X_r

#define DQ_AI255_COIL_X_r ( D ) (-(D)-30.0/360.0*6.283185307)

◆ DQ_AI255_COIL_Y

#define DQ_AI255_COIL_Y ( D ) (-(D)-150)

◆ DQ_AI255_COIL_Y_r

#define DQ_AI255_COIL_Y_r ( D ) (-(D)-150.0/360.0*6.283185307)

◆ DQ_AI255_COIL_Z

#define DQ_AI255_COIL_Z ( D ) (-(D)-270)

◆ DQ_AI255_COIL_Z_r

#define DQ_AI255_COIL_Z_r ( D ) (-(D)-270.0/360.0*6.283185307)

◆ DQ_AI255_DACS

#define DQ_AI255_DACS 4

◆ DQ_AI255_ENABLE_EXC_A

#define DQ_AI255_ENABLE_EXC_A (1L<<0)

◆ DQ_AI255_ENABLE_EXC_B

#define DQ_AI255_ENABLE_EXC_B (1L<<1)

◆ DQ_AI255_ENABLE_EXC_C

#define DQ_AI255_ENABLE_EXC_C (1L<<2)

◆ DQ_AI255_ENABLE_EXC_D

#define DQ_AI255_ENABLE_EXC_D (1L<<3)

◆ DQ_AI255_EXC_RMS_DEFAULT

#define DQ_AI255_EXC_RMS_DEFAULT 0x1f0000

◆ DQ_AI255_FFIFO

#define DQ_AI255_FFIFO (0x20)

◆ DQ_AI255_FIFO_GET_DATA

#define DQ_AI255_FIFO_GET_DATA DQ_FIFO_GET_DATA

◆ DQ_AI255_FL_HWLOOP

#define DQ_AI255_FL_HWLOOP (1L<<1)

◆ DQ_AI255_GAIN_1

#define DQ_AI255_GAIN_1 0

◆ DQ_AI255_GAIN_10

#define DQ_AI255_GAIN_10 3

◆ DQ_AI255_GAIN_2

#define DQ_AI255_GAIN_2 1

◆ DQ_AI255_GAIN_4

#define DQ_AI255_GAIN_4 2

◆ DQ_AI255_GAIN_5

#define DQ_AI255_GAIN_5 2

◆ DQ_AI255_GAIN_8

#define DQ_AI255_GAIN_8 3

◆ DQ_AI255_GAIN_A

#define DQ_AI255_GAIN_A (0x00)

◆ DQ_AI255_GAIN_B

#define DQ_AI255_GAIN_B (0x04)

◆ DQ_AI255_GAIN_C

#define DQ_AI255_GAIN_C (0x08)

◆ DQ_AI255_GAIN_D

#define DQ_AI255_GAIN_D (0x0C)

◆ DQ_AI255_GAINS

#define DQ_AI255_GAINS 4

◆ DQ_AI255_GAINV

#define DQ_AI255_GAINV 1

◆ DQ_AI255_GAINV_10

#define DQ_AI255_GAINV_10 (DQ_AI255_GAINV*10)

◆ DQ_AI255_GAINV_2

#define DQ_AI255_GAINV_2 (DQ_AI255_GAINV*2)

◆ DQ_AI255_GAINV_5

#define DQ_AI255_GAINV_5 (DQ_AI255_GAINV*5)

◆ DQ_AI255_INFOSZ

#define DQ_AI255_INFOSZ DQ_MAX_INFO_SIZE

◆ DQ_AI255_LAST_A

#define DQ_AI255_LAST_A (0x40)

◆ DQ_AI255_LAST_B

#define DQ_AI255_LAST_B (0x44)

◆ DQ_AI255_LAST_C

#define DQ_AI255_LAST_C (0x48)

◆ DQ_AI255_LAST_D

#define DQ_AI255_LAST_D (0x4C)

◆ DQ_AI255_LAST_SxA

#define DQ_AI255_LAST_SxA (0x50)

◆ DQ_AI255_LAST_SxB

#define DQ_AI255_LAST_SxB (0x54)

◆ DQ_AI255_LAST_SxC

#define DQ_AI255_LAST_SxC (0x58)

◆ DQ_AI255_LAST_SxD

#define DQ_AI255_LAST_SxD (0x5C)

◆ DQ_AI255_MAX_A

#define DQ_AI255_MAX_A (0x70)

◆ DQ_AI255_MAX_B

#define DQ_AI255_MAX_B (0x74)

◆ DQ_AI255_MAX_C

#define DQ_AI255_MAX_C (0x78)

◆ DQ_AI255_MAX_CH_LIST

#define DQ_AI255_MAX_CH_LIST 32

◆ DQ_AI255_MAX_D

#define DQ_AI255_MAX_D (0x7C)

◆ DQ_AI255_MAX_DIV

#define DQ_AI255_MAX_DIV 99

◆ DQ_AI255_MAX_DIV2

#define DQ_AI255_MAX_DIV2 199

◆ DQ_AI255_MAX_DIV3

#define DQ_AI255_MAX_DIV3 329

◆ DQ_AI255_MAX_FRQ

#define DQ_AI255_MAX_FRQ 330000

◆ DQ_AI255_MAX_PTS_PERIOD

#define DQ_AI255_MAX_PTS_PERIOD 256

◆ DQ_AI255_MAXCLFRQ

#define DQ_AI255_MAXCLFRQ 20000

◆ DQ_AI255_MAXCVFRQ

#define DQ_AI255_MAXCVFRQ 330000

◆ DQ_AI255_MIN_A

#define DQ_AI255_MIN_A (0x60)

◆ DQ_AI255_MIN_B

#define DQ_AI255_MIN_B (0x64)

◆ DQ_AI255_MIN_C

#define DQ_AI255_MIN_C (0x68)

◆ DQ_AI255_MIN_D

#define DQ_AI255_MIN_D (0x6C)

◆ DQ_AI255_MODE_DISABLE

#define DQ_AI255_MODE_DISABLE 0xf

◆ DQ_AI255_MODE_EN_AIN

#define DQ_AI255_MODE_EN_AIN 9

◆ DQ_AI255_MODE_EN_AOUT

#define DQ_AI255_MODE_EN_AOUT 8

◆ DQ_AI255_MODE_RI_EXT

#define DQ_AI255_MODE_RI_EXT 3

◆ DQ_AI255_MODE_RI_INT

#define DQ_AI255_MODE_RI_INT 1

◆ DQ_AI255_MODE_RS_EXT

#define DQ_AI255_MODE_RS_EXT 7

◆ DQ_AI255_MODE_RS_INT

#define DQ_AI255_MODE_RS_INT 5

◆ DQ_AI255_MODE_SETAVG

#define DQ_AI255_MODE_SETAVG (1L<<0)

◆ DQ_AI255_MODE_SETZEROC

#define DQ_AI255_MODE_SETZEROC (1L<<1)

◆ DQ_AI255_MODE_SI_EXT

#define DQ_AI255_MODE_SI_EXT 2

◆ DQ_AI255_MODE_SI_INT

#define DQ_AI255_MODE_SI_INT 0

◆ DQ_AI255_MODE_SS_EXT

#define DQ_AI255_MODE_SS_EXT 6

◆ DQ_AI255_MODE_SS_INT

#define DQ_AI255_MODE_SS_INT 4

◆ DQ_AI255_MODECONT

#define DQ_AI255_MODECONT (DQ_FIFO_MODECONT)

◆ DQ_AI255_MODEFIFO

#define DQ_AI255_MODEFIFO (DQ_FIFO_MODEFIFO)

◆ DQ_AI255_MODESCAN

#define DQ_AI255_MODESCAN (DQ_FIFO_MODESCAN)

◆ DQ_AI255_NAMELEN

#define DQ_AI255_NAMELEN 20

◆ DQ_AI255_OFFSET

#define DQ_AI255_OFFSET (40.0)

◆ DQ_AI255_PHASE_A

#define DQ_AI255_PHASE_A (0x10)

◆ DQ_AI255_PHASE_B

#define DQ_AI255_PHASE_B (0x14)

◆ DQ_AI255_PHASE_C

#define DQ_AI255_PHASE_C (0x18)

◆ DQ_AI255_PHASE_D

#define DQ_AI255_PHASE_D (0x1C)

◆ DQ_AI255_RAW_DATA

#define DQ_AI255_RAW_DATA (0x20)

◆ DQ_AI255_SPAN

#define DQ_AI255_SPAN (80.0)

◆ DQ_AI255_STATUS

#define DQ_AI255_STATUS (0x18)

◆ DQ_AI255_STEP

#define DQ_AI255_STEP (DQ_AI255_SPAN/0xFFFF)

◆ DQ_AI255_STEP18

#define DQ_AI255_STEP18 (DQ_AI255_SPAN/0x3FFFF)

◆ DQ_AI255_STEP_10

#define DQ_AI255_STEP_10 (DQ_AI255_STEP/10)

◆ DQ_AI255_STEP_2

#define DQ_AI255_STEP_2 (DQ_AI255_STEP/2)

◆ DQ_AI255_STEP_5

#define DQ_AI255_STEP_5 (DQ_AI255_STEP/5)

◆ DQ_AI255_VREFS

#define DQ_AI255_VREFS 0

◆ DQ_AI255_WFAVG

#define DQ_AI255_WFAVG 16

◆ DQ_AI255_ZC

#define DQ_AI255_ZC (0x30)

◆ DQ_AI255_ZERO_LEVEL

#define DQ_AI255_ZERO_LEVEL 0x8000

◆ DQ_AI301_CL_TIMES

#define DQ_AI301_CL_TIMES 2

◆ DQ_AI301_FIFO_BUFSZ

#define DQ_AI301_FIFO_BUFSZ 16

◆ DQ_AI301_FIFO_CH

#define DQ_AI301_FIFO_CH 128

◆ DQ_AO224_PHASE_SET

#define DQ_AO224_PHASE_SET	(	PHASE,
		DELAY
	)	(((PHASE)<<18)\|((DELAY)&0x3ffff))

◆ DQ_AO254_PHASE_SET

#define DQ_AO254_PHASE_SET	(	PHASE,
		DELAY
	)	(((PHASE)<<18)\|((DELAY)&0x3ffff))

◆ DQ_AO255_PHASE_SET

#define DQ_AO255_PHASE_SET	(	PHASE,
		DELAY
	)	(((PHASE)<<18)\|((DELAY)&0x3ffff))

◆ DQ_AO301_BASE

#define DQ_AO301_BASE BUS_FREQUENCY

◆ DQ_AO301_BI10

#define DQ_AO301_BI10 (3L << 19)

◆ DQ_AO301_CALSZ

#define DQ_AO301_CALSZ 4

◆ DQ_AO301_CHAN

#define DQ_AO301_CHAN 8

◆ DQ_AO301_CHANSVC

#define DQ_AO301_CHANSVC 32

◆ DQ_AO301_DCALSZ

#define DQ_AO301_DCALSZ 16

◆ DQ_AO301_DMAPCV

#define DQ_AO301_DMAPCV ((DQ_AO301_BASE/8000)-1)

◆ DQ_AO301_ENCOUT

#define DQ_AO301_ENCOUT (1L << 18)

◆ DQ_AO301_FIFO_SET_DATA

#define DQ_AO301_FIFO_SET_DATA DQ_FIFO_SET_DATA

◆ DQ_AO301_INFOSZ

#define DQ_AO301_INFOSZ DQ_MAX_INFO_SIZE

◆ DQ_AO301_MAXCLFRQ

#define DQ_AO301_MAXCLFRQ 100000

◆ DQ_AO301_MAXCVFRQ

#define DQ_AO301_MAXCVFRQ 800000

◆ DQ_AO301_MIDSCALE

#define DQ_AO301_MIDSCALE 0x8000

◆ DQ_AO301_MODECONT

#define DQ_AO301_MODECONT (DQ_FIFO_MODECONT)

◆ DQ_AO301_MODEFIFO

#define DQ_AO301_MODEFIFO (DQ_FIFO_MODEFIFO)

◆ DQ_AO301_MODESCAN

#define DQ_AO301_MODESCAN (DQ_FIFO_MODESCAN)

◆ DQ_AO301_MODEWFGEN

#define DQ_AO301_MODEWFGEN (3L << 16)

◆ DQ_AO301_NAMELEN

#define DQ_AO301_NAMELEN 32

◆ DQ_AO301_NEG10

#define DQ_AO301_NEG10 (2L << 19)

◆ DQ_AO301_OFF

#define DQ_AO301_OFF (0L << 19)

◆ DQ_AO301_OFFSET

#define DQ_AO301_OFFSET (10.0)

◆ DQ_AO301_POS10

#define DQ_AO301_POS10 (1L << 19)

◆ DQ_AO301_SPAN

#define DQ_AO301_SPAN (20.0)

◆ DQ_AO301_STARTRATE

#define DQ_AO301_STARTRATE DQ_AO301_DMAPCV

◆ DQ_AO301_STEP

#define DQ_AO301_STEP (DQ_AO301_SPAN/0xFFFF)

◆ DQ_AO308_352_OFFSET

#define DQ_AO308_352_OFFSET (13.517)

◆ DQ_AO308_352_SPAN

#define DQ_AO308_352_SPAN (27.034)

◆ DQ_AO308_352_STEP

#define DQ_AO308_352_STEP (DQ_AO308_352_SPAN/0xFFFF)

◆ DQ_AO308_353_OFFSET

#define DQ_AO308_353_OFFSET (40.0)

◆ DQ_AO308_353_SPAN

#define DQ_AO308_353_SPAN (80.0)

◆ DQ_AO308_353_STEP

#define DQ_AO308_353_STEP (DQ_AO308_353_SPAN/0xFFFF)

◆ DQ_AO332_BASE

#define DQ_AO332_BASE (BUS_FREQUENCY)

◆ DQ_AO332_CALSZ

#define DQ_AO332_CALSZ (32)

◆ DQ_AO332_CHAN

#define DQ_AO332_CHAN (32)

◆ DQ_AO332_CHANMASK

#define DQ_AO332_CHANMASK (DQ_AO332_CHAN-1)

◆ DQ_AO332_CHANSVC

#define DQ_AO332_CHANSVC (32)

◆ DQ_AO332_DMAPCV

#define DQ_AO332_DMAPCV ((DQ_AO332_BASE/8000)-1)

◆ DQ_AO332_INFOSZ

#define DQ_AO332_INFOSZ (DQ_MAX_INFO_SIZE)

◆ DQ_AO332_MAXCLFRQ

#define DQ_AO332_MAXCLFRQ (100000)

◆ DQ_AO332_MAXCVFRQ

#define DQ_AO332_MAXCVFRQ (800000)

◆ DQ_AO332_MIDSCALE

#define DQ_AO332_MIDSCALE (0x8000)

◆ DQ_AO332_NAMELEN

#define DQ_AO332_NAMELEN 12

◆ DQ_AO332_OFFSET

#define DQ_AO332_OFFSET (10.0)

◆ DQ_AO332_SPAN

#define DQ_AO332_SPAN (20.0)

◆ DQ_AO332_STARTRATE

#define DQ_AO332_STARTRATE (DQ_AO332_DMAPCV)

◆ DQ_AO332_STEP

#define DQ_AO332_STEP (DQ_AO332_SPAN/0xFFFF)

◆ DQ_AO333_ADC_OFFSET

#define DQ_AO333_ADC_OFFSET (10.0)

◆ DQ_AO333_ADC_RESULT

#define DQ_AO333_ADC_RESULT (0x2100)

◆ DQ_AO333_ADC_SPAN

#define DQ_AO333_ADC_SPAN (20.0)

◆ DQ_AO333_ADC_STEP

#define DQ_AO333_ADC_STEP (DQ_AO333_ADC_SPAN/(double)0xffff)

◆ DQ_AO333_ADC_STEP24

#define DQ_AO333_ADC_STEP24 (DQ_AO333_ADC_SPAN/(double)0xffffff)

◆ DQ_AO333_CAL_0V

#define DQ_AO333_CAL_0V (DQ_AO332_MIDSCALE)

◆ DQ_AO333_CAL_N9_5V

#define DQ_AO333_CAL_N9_5V (0x0667)

◆ DQ_AO333_CAL_P9_5V

#define DQ_AO333_CAL_P9_5V (0xf999)

◆ DQ_AO333_CAL_READINGS_AVGD

#define DQ_AO333_CAL_READINGS_AVGD (6)

◆ DQ_AO333_DEF_GAIN_CAL

#define DQ_AO333_DEF_GAIN_CAL (0x7c60)

◆ DQ_AO333_DEF_GAIN_SF_CAL

#define DQ_AO333_DEF_GAIN_SF_CAL (0x0b)

◆ DQ_AO333_DEF_OFFSET_CAL

#define DQ_AO333_DEF_OFFSET_CAL (0x69)

◆ DQ_AO333_I2C_CTRL

#define DQ_AO333_I2C_CTRL (0x2000)

◆ DQ_AO333_I2C_CTRL_RDY_ALL

#define DQ_AO333_I2C_CTRL_RDY_ALL (1L<<1)

◆ DQ_AO333_I2C_NEW_DATA

#define DQ_AO333_I2C_NEW_DATA (0x2018)

◆ DQ_AO333_MAX_GAIN_CAL_DEV

#define DQ_AO333_MAX_GAIN_CAL_DEV (0x0600)

◆ DQ_AO333_MAX_N9_5V_DEV

#define DQ_AO333_MAX_N9_5V_DEV (0x2a)

◆ DQ_AO333_MAX_OFFSET_CAL_DEV

#define DQ_AO333_MAX_OFFSET_CAL_DEV (0x120)

◆ DQ_AO358_ADC_CHAN_CHAN

#define DQ_AO358_ADC_CHAN_CHAN (5)

◆ DQ_AO358_ADC_CHAN_MASK

#define DQ_AO358_ADC_CHAN_MASK (0x07)

◆ DQ_AO358_ADC_CHANS

#define DQ_AO358_ADC_CHANS (DQ_AO358_CHAN*DQ_AO358_ADC_CHAN_CHAN)

◆ DQ_AO358_BASE

#define DQ_AO358_BASE (BUS_FREQUENCY)

◆ DQ_AO358_CFCH_MERGE

#define DQ_AO358_CFCH_MERGE	(	C,
		F,
		CH
	)	(((C)&0x3FF)\|(((F)&0x3FF)<<DQ_AO358_FINE_SHIFT)\|((CH)<<DQ_AO358_WR_CH_SHIFT))

◆ DQ_AO358_CH_MASK

#define DQ_AO358_CH_MASK (DQ_AO358_CHAN-1)

◆ DQ_AO358_CHAN

#define DQ_AO358_CHAN (8)

◆ DQ_AO358_CL_MASK

#define DQ_AO358_CL_MASK (0x3f)

◆ DQ_AO358_CL_TIMES

#define DQ_AO358_CL_TIMES (2)

◆ DQ_AO358_COARSE_SHIFT

#define DQ_AO358_COARSE_SHIFT (0)

◆ DQ_AO358_CONVERGE_LIMIT

#define DQ_AO358_CONVERGE_LIMIT (500)

◆ DQ_AO358_DEF_MIDPOS

#define DQ_AO358_DEF_MIDPOS (800)

◆ DQ_AO358_DMAPCV

#define DQ_AO358_DMAPCV ((DQ_AO358_BASE/8000)-1)

◆ DQ_AO358_EE_CHK_STS

#define DQ_AO358_EE_CHK_STS (0x01)

◆ DQ_AO358_EE_CHKSTS_RETLEN

#define DQ_AO358_EE_CHKSTS_RETLEN (5)

◆ DQ_AO358_EE_ERASE

#define DQ_AO358_EE_ERASE (0x32)

◆ DQ_AO358_EE_ERASE_SECTOR

#define DQ_AO358_EE_ERASE_SECTOR (0x35)

◆ DQ_AO358_EE_ESTS_BUSY

#define DQ_AO358_EE_ESTS_BUSY (1L<<4)

◆ DQ_AO358_EE_ESTS_COMPLETE

#define DQ_AO358_EE_ESTS_COMPLETE (1L<<31)

◆ DQ_AO358_EE_ESTS_ERR

#define DQ_AO358_EE_ESTS_ERR (1L<<30)

◆ DQ_AO358_EE_ESTS_RFF

#define DQ_AO358_EE_ESTS_RFF (1L<<3)

◆ DQ_AO358_EE_ESTS_RFHF

#define DQ_AO358_EE_ESTS_RFHF (1L<<2)

◆ DQ_AO358_EE_ESTS_WFE

#define DQ_AO358_EE_ESTS_WFE (1L<<1)

◆ DQ_AO358_EE_ESTS_WFHF

#define DQ_AO358_EE_ESTS_WFHF (1L<<0)

◆ DQ_AO358_EE_ID_1M

#define DQ_AO358_EE_ID_1M (0x10)

◆ DQ_AO358_EE_ID_4M

#define DQ_AO358_EE_ID_4M (0x12)

◆ DQ_AO358_EE_INVALID_RDSTS

#define DQ_AO358_EE_INVALID_RDSTS (1L<<31)

◆ DQ_AO358_EE_RD

#define DQ_AO358_EE_RD (0x22)

◆ DQ_AO358_EE_RD_ID_ADDR

#define DQ_AO358_EE_RD_ID_ADDR (0x21)

◆ DQ_AO358_EE_RD_MAX_LEN

#define DQ_AO358_EE_RD_MAX_LEN (1024)

◆ DQ_AO358_EE_RDSTS_BP

#define DQ_AO358_EE_RDSTS_BP (3L<<2)

◆ DQ_AO358_EE_RDSTS_WEL

#define DQ_AO358_EE_RDSTS_WEL (1L<<1)

◆ DQ_AO358_EE_RDSTS_WIP

#define DQ_AO358_EE_RDSTS_WIP (1L<<0)

◆ DQ_AO358_EE_WR

#define DQ_AO358_EE_WR (0x33)

◆ DQ_AO358_EE_WR_CLOSE

#define DQ_AO358_EE_WR_CLOSE (0x34)

◆ DQ_AO358_EE_WR_MAX_LEN

#define DQ_AO358_EE_WR_MAX_LEN (256)

◆ DQ_AO358_EE_WR_OPEN

#define DQ_AO358_EE_WR_OPEN (0x31)

◆ DQ_AO358_FIFO_CH

#define DQ_AO358_FIFO_CH (128)

◆ DQ_AO358_FINE_SHIFT

#define DQ_AO358_FINE_SHIFT (12)

◆ DQ_AO358_INFOSZ

#define DQ_AO358_INFOSZ (DQ_MAX_INFO_SIZE)

◆ DQ_AO358_LCR_DCDIS

#define DQ_AO358_LCR_DCDIS (1L<<0)

◆ DQ_AO358_LCR_LED

#define DQ_AO358_LCR_LED (1L<<1)

◆ DQ_AO358_MAKE_CL

#define DQ_AO358_MAKE_CL	(	CH,
		SUBCH
	)	((((CH)&DQ_AO358_CH_MASK)<<3)\|((SUBCH)& DQ_AO358_ADC_CHAN_MASK))

◆ DQ_AO358_MAXCLFRQ

#define DQ_AO358_MAXCLFRQ (10000)

◆ DQ_AO358_MAXCVFRQ

#define DQ_AO358_MAXCVFRQ (DQ_AO358_MAXCLFRQ*DQ_AO358_CHAN)

◆ DQ_AO358_NAMELEN

#define DQ_AO358_NAMELEN (32)

◆ DQ_AO358_R123_350

#define DQ_AO358_R123_350 (1050.011)

◆ DQ_AO358_R4DELTA

#define DQ_AO358_R4DELTA (12.37112)

◆ DQ_AO358_R4FDELTA

#define DQ_AO358_R4FDELTA (0.09885)

◆ DQ_AO358_RDIV_350

#define DQ_AO358_RDIV_350 (20804.0)

◆ DQ_AO358_RF_0X100_350

#define DQ_AO358_RF_0X100_350 (5004.887586)

◆ DQ_AO358_RPAR_350

#define DQ_AO358_RPAR_350 (365.0)

◆ DQ_AO358_RPOTNOM_350

#define DQ_AO358_RPOTNOM_350 (20000.0)

◆ DQ_AO358_RPROTC_350

#define DQ_AO358_RPROTC_350 (3000.0)

◆ DQ_AO358_RPROTF_350

#define DQ_AO358_RPROTF_350 (120000.0)

◆ DQ_AO358_RSTART_350

#define DQ_AO358_RSTART_350 (344.75)

◆ DQ_AO358_RWIPER_350

#define DQ_AO358_RWIPER_350 (60.0)

◆ DQ_AO358_STARTRATE

#define DQ_AO358_STARTRATE (DQ_AO358_DMAPCV)

◆ DQ_AO358_SUBCH_EX1

#define DQ_AO358_SUBCH_EX1 (1)

◆ DQ_AO358_SUBCH_EX2

#define DQ_AO358_SUBCH_EX2 (2)

◆ DQ_AO358_SUBCH_I_SENSE

#define DQ_AO358_SUBCH_I_SENSE (0)

◆ DQ_AO358_SUBCH_THERM

#define DQ_AO358_SUBCH_THERM (4)

◆ DQ_AO358_SUBCH_VS_N

#define DQ_AO358_SUBCH_VS_N (3)

◆ DQ_AO358_WR_CH_SHIFT

#define DQ_AO358_WR_CH_SHIFT (28)

◆ DQ_AO358_WR_CMD_ACB

#define DQ_AO358_WR_CMD_ACB (1<<24)

◆ DQ_AO358_WRITE_STOP

#define DQ_AO358_WRITE_STOP ((3L<<22)|(3L<<10))

◆ DQ_AO385_350_I_SHUNT

#define DQ_AO385_350_I_SHUNT (4.7)

◆ DQ_AO385_AI_SPAN

#define DQ_AO385_AI_SPAN (5.0)

◆ DQ_AO385_AO_SPAN_350

#define DQ_AO385_AO_SPAN_350 (DQ_AO385_R4_MAX_350-DQ_AO385_R4_MIN_350)

◆ DQ_AO385_EXC_SCALER

#define DQ_AO385_EXC_SCALER (51.75124)

◆ DQ_AO385_OFFSET

#define DQ_AO385_OFFSET (DQ_AO385_AI_SPAN/2.0)

◆ DQ_AO385_R4_MAX_350

#define DQ_AO385_R4_MAX_350 (355.25)

◆ DQ_AO385_R4_MIN_350

#define DQ_AO385_R4_MIN_350 (344.75)

◆ DQ_AO385_RFINE_AT_CAL

#define DQ_AO385_RFINE_AT_CAL (256)

◆ DQ_AO385_RLUT_SZ

#define DQ_AO385_RLUT_SZ (65536)

◆ DQ_AO385_RPOT_MASK

#define DQ_AO385_RPOT_MASK (0x3ff)

◆ DQ_AO385_RPOT_MAX

#define DQ_AO385_RPOT_MAX (1023.0)

◆ DQ_AO385_STEP

#define DQ_AO385_STEP (DQ_AO385_AI_SPAN/(double)0xffffff)

◆ DQ_AO385_T_OFFSET

#define DQ_AO385_T_OFFSET (273.0)

◆ DQ_AO385_T_SLOPE

#define DQ_AO385_T_SLOPE (314.0)

◆ DQ_AO3xx_CONT_WF

#define DQ_AO3xx_CONT_WF (3)

◆ DQ_AO3xx_PAUSE_WF

#define DQ_AO3xx_PAUSE_WF (2)

◆ DQ_AO3xx_PROG_WF

#define DQ_AO3xx_PROG_WF (4)

◆ DQ_AO3xx_START_WF

#define DQ_AO3xx_START_WF (1)

◆ DQ_AO3xx_STOP_WF

#define DQ_AO3xx_STOP_WF (0)

◆ DQ_AR512_CHAN

#define DQ_AR512_CHAN 12

◆ DQ_AR566_BASE

#define DQ_AR566_BASE 66000000

◆ DQ_AR566_CH_CMDMASK

#define DQ_AR566_CH_CMDMASK 0xf0

◆ DQ_AR566_CH_FILTER

#define DQ_AR566_CH_FILTER 0x60

◆ DQ_AR566_CH_LASTDATA

#define DQ_AR566_CH_LASTDATA 0x70

◆ DQ_AR566_CH_MASK

#define DQ_AR566_CH_MASK 0x0f

◆ DQ_AR566_CH_RXFIFOAVL

#define DQ_AR566_CH_RXFIFOAVL 0x20

◆ DQ_AR566_CH_SCHDATA

#define DQ_AR566_CH_SCHDATA 0x50

◆ DQ_AR566_CH_SCHED

#define DQ_AR566_CH_SCHED 0x40

◆ DQ_AR566_CH_TXFIFOAVL

#define DQ_AR566_CH_TXFIFOAVL 0x30

◆ DQ_AR566_CHAN

#define DQ_AR566_CHAN 6

◆ DQ_AR566_CHAN_RX

#define DQ_AR566_CHAN_RX 12

◆ DQ_AR566_CHAN_TX

#define DQ_AR566_CHAN_TX 6

◆ DQ_AR566_FIFO_GET_DATA

#define DQ_AR566_FIFO_GET_DATA DQ_FIFO_GET_DATA

◆ DQ_AR566_FIFO_SET_DATA

#define DQ_AR566_FIFO_SET_DATA DQ_FIFO_SET_DATA

◆ DQ_AR566_ID_EXTENDED

#define DQ_AR566_ID_EXTENDED (0x1L << 18)

◆ DQ_AR566_ID_STANDARD

#define DQ_AR566_ID_STANDARD (0x0L << 18)

◆ DQ_AR566_INFOSZ

#define DQ_AR566_INFOSZ DQ_MAX_INFO_SIZE

◆ DQ_AR566_INTCLKUS

#define DQ_AR566_INTCLKUS 100

◆ DQ_AR566_MAXCLFRQ

#define DQ_AR566_MAXCLFRQ 2000

◆ DQ_AR566_MAXCVFRQ

#define DQ_AR566_MAXCVFRQ 2000

◆ DQ_AR566_MAXDLYCNT

#define DQ_AR566_MAXDLYCNT 65535

◆ DQ_AR566_MODECONT

#define DQ_AR566_MODECONT (DQ_FIFO_MODECONT)

◆ DQ_AR566_MODEFIFO

#define DQ_AR566_MODEFIFO (DQ_FIFO_MODEFIFO)

◆ DQ_AR566_MODESCAN

#define DQ_AR566_MODESCAN (DQ_FIFO_MODESCAN)

◆ DQ_AR566_NAMELEN

#define DQ_AR566_NAMELEN 32

◆ DQ_AR_ADD_TIMESTAMP

#define DQ_AR_ADD_TIMESTAMP (1L<<13)

◆ DQ_AR_ALL_ERROR_FLASG

#define DQ_AR_ALL_ERROR_FLASG (0x1FFFFFFF)

◆ DQ_AR_ALLOW_FIFO_HIGH

#define DQ_AR_ALLOW_FIFO_HIGH (1L<<16)

◆ DQ_AR_ALLOW_ZERO_LBL

#define DQ_AR_ALLOW_ZERO_LBL (1L<<15)

◆ DQ_AR_ENABLE_DIO0

#define DQ_AR_ENABLE_DIO0 (1L<<0)

◆ DQ_AR_ENABLE_DIO1

#define DQ_AR_ENABLE_DIO1 (1L<<1)

◆ DQ_AR_ENABLE_DIO2

#define DQ_AR_ENABLE_DIO2 (1L<<2)

◆ DQ_AR_ENABLE_FILTER

#define DQ_AR_ENABLE_FILTER (1L<<12)

◆ DQ_AR_ENABLE_LOOPBACK

#define DQ_AR_ENABLE_LOOPBACK (1L<<11)

◆ DQ_AR_ENABLE_Rx

#define DQ_AR_ENABLE_Rx (1L<<9)

◆ DQ_AR_ENABLE_RxFIFO

#define DQ_AR_ENABLE_RxFIFO (1L<<13)

◆ DQ_AR_ENABLE_SCHEDULER

#define DQ_AR_ENABLE_SCHEDULER (1L<<10)

◆ DQ_AR_ENABLE_Tx

#define DQ_AR_ENABLE_Tx (1L<<8)

◆ DQ_AR_ENABLE_TxFIFO

#define DQ_AR_ENABLE_TxFIFO (1L<<14)

◆ DQ_AR_FEW_DISABLED

#define DQ_AR_FEW_DISABLED (0)

◆ DQ_AR_FEW_ENABLED

#define DQ_AR_FEW_ENABLED (1L<<5)

◆ DQ_AR_FIFO_PSTB0

#define DQ_AR_FIFO_PSTB0 (1L<<20)

◆ DQ_AR_FIFO_PSTB1

#define DQ_AR_FIFO_PSTB1 (3L<<20)

◆ DQ_AR_FIFO_RATE

#define DQ_AR_FIFO_RATE 1

◆ DQ_AR_IGNORE_BAD_DATA

#define DQ_AR_IGNORE_BAD_DATA (1L<<19)

◆ DQ_AR_LB_CHECK_PARITY

#define DQ_AR_LB_CHECK_PARITY (1L<<12)

◆ DQ_AR_LOGIC_LOOPBACK

#define DQ_AR_LOGIC_LOOPBACK (1L<<15)

◆ DQ_AR_MASTER

#define DQ_AR_MASTER (1L<<17)

◆ DQ_AR_PARITYEVEN

#define DQ_AR_PARITYEVEN (1L<<2)

◆ DQ_AR_PARITYODD

#define DQ_AR_PARITYODD (1L<<1)

◆ DQ_AR_PARITYOFF

#define DQ_AR_PARITYOFF (0)

◆ DQ_AR_RATEHIGH

#define DQ_AR_RATEHIGH (1L<<0)

◆ DQ_AR_RATELOW

#define DQ_AR_RATELOW (0)

◆ DQ_AR_RECYCLE

#define DQ_AR_RECYCLE (1L<<16)

◆ DQ_AR_Rx_BLOCKING

#define DQ_AR_Rx_BLOCKING (1L<<2)

◆ DQ_AR_Rx_FIFO

#define DQ_AR_Rx_FIFO (1L<<1)

◆ DQ_AR_Rx_LATEST

#define DQ_AR_Rx_LATEST (1L<<0)

◆ DQ_AR_RXCTR_NDO

#define DQ_AR_RXCTR_NDO (1L<<8)

◆ DQ_AR_RXCTR_TRIG

#define DQ_AR_RXCTR_TRIG (1L<<9)

◆ DQ_AR_SCHED_PS100us

#define DQ_AR_SCHED_PS100us (1L<<20)

◆ DQ_AR_SCHED_PSDISABLED

#define DQ_AR_SCHED_PSDISABLED (0)

◆ DQ_AR_SCHED_PSTB0

#define DQ_AR_SCHED_PSTB0 (2L<<20)

◆ DQ_AR_SCHED_PSTB1

#define DQ_AR_SCHED_PSTB1 (3L<<20)

◆ DQ_AR_SCHEDULER_RATE

#define DQ_AR_SCHEDULER_RATE 0

◆ DQ_AR_SDI_DISABLED

#define DQ_AR_SDI_DISABLED (0)

◆ DQ_AR_SDI_ENABLED

#define DQ_AR_SDI_ENABLED (1L<<3)

◆ DQ_AR_SDIMASK0

#define DQ_AR_SDIMASK0 (1L<<9)

◆ DQ_AR_SDIMASK1

#define DQ_AR_SDIMASK1 (1L<<10)

◆ DQ_AR_SDIMASKOFFSET

#define DQ_AR_SDIMASKOFFSET (9)

◆ DQ_AR_SETFILTER_FILL_TABLE

#define DQ_AR_SETFILTER_FILL_TABLE (1L<<4)

◆ DQ_AR_SETFILTER_GET

#define DQ_AR_SETFILTER_GET (1L<<1)

◆ DQ_AR_SETFILTER_PUT

#define DQ_AR_SETFILTER_PUT (1L<<0)

◆ DQ_AR_SETSCHED_DATA_ONLY

#define DQ_AR_SETSCHED_DATA_ONLY (1L<<2)

◆ DQ_AR_SETSCHED_FILL_TABLE

#define DQ_AR_SETSCHED_FILL_TABLE (1L<<4)

◆ DQ_AR_SETSCHED_GET

#define DQ_AR_SETSCHED_GET (1L<<1)

◆ DQ_AR_SETSCHED_PUT

#define DQ_AR_SETSCHED_PUT (1L<<0)

◆ DQ_AR_SHORTGAP_DISABLED

#define DQ_AR_SHORTGAP_DISABLED (0)

◆ DQ_AR_SHORTGAP_ENABLED

#define DQ_AR_SHORTGAP_ENABLED (1L<<6)

◆ DQ_AR_SLOWSLEW_DISABLED

#define DQ_AR_SLOWSLEW_DISABLED (0)

◆ DQ_AR_SLOWSLEW_ENABLED

#define DQ_AR_SLOWSLEW_ENABLED (1L<<8)

◆ DQ_AR_STATUS_CLEAR_COUNT

#define DQ_AR_STATUS_CLEAR_COUNT (1L<<1)

◆ DQ_AR_STATUS_CLEAR_ERROR

#define DQ_AR_STATUS_CLEAR_ERROR (1L<<0)

◆ DQ_AR_STATUS_GET_FIFO_CNT

#define DQ_AR_STATUS_GET_FIFO_CNT (1L<<6)

◆ DQ_AR_STATUS_GET_FRM_CTR

#define DQ_AR_STATUS_GET_FRM_CTR (1L<<3)

◆ DQ_AR_STATUS_GET_FRM_ERR

#define DQ_AR_STATUS_GET_FRM_ERR (1L<<4)

◆ DQ_AR_STATUS_GET_FRM_MIS

#define DQ_AR_STATUS_GET_FRM_MIS (1L<<5)

◆ DQ_AR_STATUS_GET_TOTAL

#define DQ_AR_STATUS_GET_TOTAL (1L<<2)

◆ DQ_AR_TIMESTAMP_DISABLED

#define DQ_AR_TIMESTAMP_DISABLED (0)

◆ DQ_AR_TIMESTAMP_ENABLED

#define DQ_AR_TIMESTAMP_ENABLED (1L<<7)

◆ DQ_AR_Tx_BLOCKING

#define DQ_AR_Tx_BLOCKING (1L<<2)

◆ DQ_AR_TxPRIORITY_HIGH

#define DQ_AR_TxPRIORITY_HIGH (1L<<0)

◆ DQ_AR_TxPRIORITY_LOW

#define DQ_AR_TxPRIORITY_LOW (1L<<1)

◆ DQ_AR_XBIT_DISABLED

#define DQ_AR_XBIT_DISABLED (0)

◆ DQ_AR_XBIT_ENABLED

#define DQ_AR_XBIT_ENABLED (1L<<4)

◆ DQ_BROADCAST_DEVN

#define DQ_BROADCAST_DEVN (0xF)

◆ DQ_C3PLL_BASE

#define DQ_C3PLL_BASE (66000000)

◆ DQ_C3PLL_CFG_24MHZ_C

#define DQ_C3PLL_CFG_24MHZ_C (0)

◆ DQ_C3PLL_CFG_24MHZ_I

#define DQ_C3PLL_CFG_24MHZ_I (1)

◆ DQ_C3PLL_CFG_24MHZ_R

#define DQ_C3PLL_CFG_24MHZ_R (19)

◆ DQ_C3PLL_CFG_24MHZ_VCO_POST

#define DQ_C3PLL_CFG_24MHZ_VCO_POST (0)

◆ DQ_C3PLL_MAX_FREQ_501

#define DQ_C3PLL_MAX_FREQ_501 (32000000)

◆ DQ_C3PLL_MAX_M

#define DQ_C3PLL_MAX_M (510)

◆ DQ_C3PLL_MAX_N

#define DQ_C3PLL_MAX_N (510)

◆ DQ_C3PLL_MAX_VCO

#define DQ_C3PLL_MAX_VCO (1300000000.0)

◆ DQ_C3PLL_MIN_FREQ_501

#define DQ_C3PLL_MIN_FREQ_501 (16000000)

◆ DQ_C3PLL_MIN_M

#define DQ_C3PLL_MIN_M (2)

◆ DQ_C3PLL_MIN_N

#define DQ_C3PLL_MIN_N (2)

◆ DQ_C3PLL_MIN_VCO

#define DQ_C3PLL_MIN_VCO (600000000.0)

◆ DQ_CAN503_BC_TX0

#define DQ_CAN503_BC_TX0 (0x0A)

◆ DQ_CAN503_BE_ACK_DEL

#define DQ_CAN503_BE_ACK_DEL (0x1a)

◆ DQ_CAN503_BE_ACK_SLT

#define DQ_CAN503_BE_ACK_SLT (0x19)

◆ DQ_CAN503_BE_AEF

#define DQ_CAN503_BE_AEF (0x11)

◆ DQ_CAN503_BE_CRC_DEL

#define DQ_CAN503_BE_CRC_DEL (0x18)

◆ DQ_CAN503_BE_CRC_SEQ

#define DQ_CAN503_BE_CRC_SEQ (0x8)

◆ DQ_CAN503_BE_DF

#define DQ_CAN503_BE_DF (0xa)

◆ DQ_CAN503_BE_DLC

#define DQ_CAN503_BE_DLC (0xb)

◆ DQ_CAN503_BE_EOF

#define DQ_CAN503_BE_EOF (0x1a)

◆ DQ_CAN503_BE_ERR_DEL

#define DQ_CAN503_BE_ERR_DEL (0x17)

◆ DQ_CAN503_BE_ID_12_5

#define DQ_CAN503_BE_ID_12_5 (0xf)

◆ DQ_CAN503_BE_ID_17_13

#define DQ_CAN503_BE_ID_17_13 (0x7)

◆ DQ_CAN503_BE_ID_20_18

#define DQ_CAN503_BE_ID_20_18 (0x6)

◆ DQ_CAN503_BE_ID_28_21

#define DQ_CAN503_BE_ID_28_21 (0x2)

◆ DQ_CAN503_BE_ID_4_0

#define DQ_CAN503_BE_ID_4_0 (0xe)

◆ DQ_CAN503_BE_IDE

#define DQ_CAN503_BE_IDE (0x5)

◆ DQ_CAN503_BE_IM

#define DQ_CAN503_BE_IM (0x12)

◆ DQ_CAN503_BE_OL

#define DQ_CAN503_BE_OL (0x1c)

◆ DQ_CAN503_BE_PEF

#define DQ_CAN503_BE_PEF (0x16)

◆ DQ_CAN503_BE_RTR

#define DQ_CAN503_BE_RTR (0xc)

◆ DQ_CAN503_BE_SOF

#define DQ_CAN503_BE_SOF (0x3)

◆ DQ_CAN503_BE_SRTR

#define DQ_CAN503_BE_SRTR (0x4)

◆ DQ_CAN503_BE_TDB

#define DQ_CAN503_BE_TDB (0x13)

◆ DQ_CAN503_DIR_RX

#define DQ_CAN503_DIR_RX (0x20)

◆ DQ_CAN503_DIR_TX

#define DQ_CAN503_DIR_TX (0x0)

◆ DQ_CAN503_EC_BIT

#define DQ_CAN503_EC_BIT (0x00)

◆ DQ_CAN503_EC_FORM

#define DQ_CAN503_EC_FORM (0x40)

◆ DQ_CAN503_EC_OTHER

#define DQ_CAN503_EC_OTHER (0xC0)

◆ DQ_CAN503_EC_STUFF

#define DQ_CAN503_EC_STUFF (0x80)

◆ DQ_CAN503_ERR_AE

#define DQ_CAN503_ERR_AE (2)

◆ DQ_CAN503_ERR_BE

#define DQ_CAN503_ERR_BE (3)

◆ DQ_CAN503_ERR_NONE

#define DQ_CAN503_ERR_NONE (0)

◆ DQ_CAN503_ERR_OR

#define DQ_CAN503_ERR_OR (4)

◆ DQ_CAN503_ERR_PASS

#define DQ_CAN503_ERR_PASS (7)

◆ DQ_CAN503_ERR_RESET

#define DQ_CAN503_ERR_RESET (6)

◆ DQ_CAN503_ERR_TO

#define DQ_CAN503_ERR_TO (5)

◆ DQ_CAN503_ERR_WARN

#define DQ_CAN503_ERR_WARN (1)

◆ DQ_CAN503_MODE_BASIC

#define DQ_CAN503_MODE_BASIC (0 << 12)

◆ DQ_CAN503_MODE_XTEND

#define DQ_CAN503_MODE_XTEND (1 << 12)

◆ DQ_CAN503_OPER_LISTEN

#define DQ_CAN503_OPER_LISTEN (1 << 13)

◆ DQ_CAN503_OPER_NORMAL

#define DQ_CAN503_OPER_NORMAL (0 << 13)

◆ DQ_CAN503_PC_TX0

#define DQ_CAN503_PC_TX0 (0x10)

◆ DQ_CAN503_RATE_100K

#define DQ_CAN503_RATE_100K (3 << 8)

◆ DQ_CAN503_RATE_100K_Baud

#define DQ_CAN503_RATE_100K_Baud (100000)

◆ DQ_CAN503_RATE_10K

#define DQ_CAN503_RATE_10K (0 << 8)

◆ DQ_CAN503_RATE_10K_Baud

#define DQ_CAN503_RATE_10K_Baud (10000)

◆ DQ_CAN503_RATE_125K

#define DQ_CAN503_RATE_125K (4 << 8)

◆ DQ_CAN503_RATE_125K_Baud

#define DQ_CAN503_RATE_125K_Baud (125000)

◆ DQ_CAN503_RATE_1M

#define DQ_CAN503_RATE_1M (8 << 8)

◆ DQ_CAN503_RATE_1M_Baud

#define DQ_CAN503_RATE_1M_Baud (1000000)

◆ DQ_CAN503_RATE_20K

#define DQ_CAN503_RATE_20K (1 << 8)

◆ DQ_CAN503_RATE_20K_Baud

#define DQ_CAN503_RATE_20K_Baud (20000)

◆ DQ_CAN503_RATE_250K

#define DQ_CAN503_RATE_250K (5 << 8)

◆ DQ_CAN503_RATE_250K_Baud

#define DQ_CAN503_RATE_250K_Baud (250000)

◆ DQ_CAN503_RATE_500K

#define DQ_CAN503_RATE_500K (6 << 8)

◆ DQ_CAN503_RATE_500K_Baud

#define DQ_CAN503_RATE_500K_Baud (500000)

◆ DQ_CAN503_RATE_50K

#define DQ_CAN503_RATE_50K (2 << 8)

◆ DQ_CAN503_RATE_50K_Baud

#define DQ_CAN503_RATE_50K_Baud (50000)

◆ DQ_CAN503_RATE_800K

#define DQ_CAN503_RATE_800K (7 << 8)

◆ DQ_CAN503_RATE_800K_Baud

#define DQ_CAN503_RATE_800K_Baud (800000)

◆ DQ_CAN503_VMAP_STAT

#define DQ_CAN503_VMAP_STAT (1L<<9)

◆ DQ_CAN503_VMAP_TIMESTAMP

#define DQ_CAN503_VMAP_TIMESTAMP (1L<<8)

◆ DQ_CAR550_WIRELESS_EN_DIS

#define DQ_CAR550_WIRELESS_EN_DIS (0)

◆ DQ_CCR_CRM0

#define DQ_CCR_CRM0 24

◆ DQ_CCR_CRM1

#define DQ_CCR_CRM1 25

◆ DQ_CCR_CRM2

#define DQ_CCR_CRM2 26

◆ DQ_CCR_CRM3

#define DQ_CCR_CRM3 27

◆ DQ_CCR_EC0

#define DQ_CCR_EC0 28

◆ DQ_CCR_EC1

#define DQ_CCR_EC1 29

◆ DQ_CCR_EC2

#define DQ_CCR_EC2 30

◆ DQ_CCR_ENC

#define DQ_CCR_ENC 21

◆ DQ_CCR_MM2X

#define DQ_CCR_MM2X 14

◆ DQ_CCR_PSG

#define DQ_CCR_PSG 23

◆ DQ_CCR_PSS

#define DQ_CCR_PSS 15

◆ DQ_CCR_RE

#define DQ_CCR_RE 31

◆ DQ_CCR_TBS

#define DQ_CCR_TBS 18

◆ DQ_CCR_TRS

#define DQ_CCR_TRS 22

◆ DQ_CDS_CTR

#define DQ_CDS_CTR 0x00

◆ DQ_CDS_FCNTI

#define DQ_CDS_FCNTI 0x1C

◆ DQ_CDS_FCNTO

#define DQ_CDS_FCNTO 0x20

◆ DQ_CDS_FDTI

#define DQ_CDS_FDTI 0x14

◆ DQ_CDS_FDTO

#define DQ_CDS_FDTO 0x18

◆ DQ_CDS_IFWR

#define DQ_CDS_IFWR 0x0C

◆ DQ_CDS_OFWR

#define DQ_CDS_OFWR 0x10

◆ DQ_CDS_STR

#define DQ_CDS_STR 0x00

◆ DQ_CDU_MSGSIZE

#define DQ_CDU_MSGSIZE 1

◆ DQ_CDU_START_MASK

#define DQ_CDU_START_MASK 0x001FFBFE

◆ DQ_CDU_STOP_MASK

#define DQ_CDU_STOP_MASK 0x00200400

◆ DQ_CF_UPUSER_SEC

#define DQ_CF_UPUSER_SEC (4) /* start user sector CF5272*/

◆ DQ_CFG_RECORD_SIZE

#define DQ_CFG_RECORD_SIZE (0x2000) /* our parameters can be as big as 8kB */

◆ DQ_CL_OFS

#define DQ_CL_OFS (8L)

◆ DQ_CLI_CDS0S

#define DQ_CLI_CDS0S 0x2000

◆ DQ_CLI_CTU0E

#define DQ_CLI_CTU0E 0x207C

◆ DQ_CLI_CTU0S

#define DQ_CLI_CTU0S 0x2000

◆ DQ_CLI_CTU1E

#define DQ_CLI_CTU1E 0x20FC

◆ DQ_CLI_CTU1S

#define DQ_CLI_CTU1S 0x2080

◆ DQ_CLI_CTU2E

#define DQ_CLI_CTU2E 0x217C

◆ DQ_CLI_CTU2S

#define DQ_CLI_CTU2S 0x2100

◆ DQ_CLI_CTU3E

#define DQ_CLI_CTU3E 0x21FC

◆ DQ_CLI_CTU3S

#define DQ_CLI_CTU3S 0x2180

◆ DQ_CLI_CTU4E

#define DQ_CLI_CTU4E 0x227C

◆ DQ_CLI_CTU4S

#define DQ_CLI_CTU4S 0x2200

◆ DQ_CLI_CTU5E

#define DQ_CLI_CTU5E 0x22FC

◆ DQ_CLI_CTU5S

#define DQ_CLI_CTU5S 0x2280

◆ DQ_CLI_CTU6E

#define DQ_CLI_CTU6E 0x237C

◆ DQ_CLI_CTU6S

#define DQ_CLI_CTU6S 0x2300

◆ DQ_CLI_CTU7E

#define DQ_CLI_CTU7E 0x23FC

◆ DQ_CLI_CTU7S

#define DQ_CLI_CTU7S 0x2380

◆ DQ_CLI_MANSS

#define DQ_CLI_MANSS 0x2100

◆ DQ_CLSZ

#define DQ_CLSZ (0x40)

◆ DQ_CM_CT

#define DQ_CM_CT (0x0)

◆ DQ_CM_ECT

#define DQ_CM_ECT (0x8)

◆ DQ_CM_HP

#define DQ_CM_HP (0x9)

◆ DQ_CM_NP

#define DQ_CM_NP (0xA)

◆ DQ_CM_QE

#define DQ_CM_QE (0xB)

◆ DQ_CM_RTCT

#define DQ_CM_RTCT (0x7)

◆ DQ_CM_TCT

#define DQ_CM_TCT (0x4)

◆ DQ_CM_TECT

#define DQ_CM_TECT (0xC)

◆ DQ_CM_THP

#define DQ_CM_THP (0xD)

◆ DQ_CM_TNP

#define DQ_CM_TNP (0xE)

◆ DQ_CM_TPPM

#define DQ_CM_TPPM (0x1)

◆ DQ_CM_TTPPM

#define DQ_CM_TTPPM (0x5)

◆ DQ_COM_CNT

#define DQ_COM_CNT 0x24

◆ DQ_COM_DATA

#define DQ_COM_DATA 0x28

◆ DQ_COM_TS

#define DQ_COM_TS 0x2C

◆ DQ_CPU_DEVN

#define DQ_CPU_DEVN (0xE)

◆ DQ_CR801_LB

#define DQ_CR801_LB 0x00010

◆ DQ_CR801_OEC

#define DQ_CR801_OEC 0x00001

◆ DQ_CR801_OED

#define DQ_CR801_OED 0x00004

◆ DQ_CR801_OES

#define DQ_CR801_OES 0x00002

◆ DQ_CR801_RXF

#define DQ_CR801_RXF 0x10000

◆ DQ_CR801_TS

#define DQ_CR801_TS 0x00008

◆ DQ_CR801_TXF

#define DQ_CR801_TXF 0x20000

◆ DQ_CR802_LB

#define DQ_CR802_LB 0x00010

◆ DQ_CR802_PRIMUS

#define DQ_CR802_PRIMUS 0x00004

◆ DQ_CR802_RAW

#define DQ_CR802_RAW 0x00008

◆ DQ_CR802_RXF

#define DQ_CR802_RXF 0x10000

◆ DQ_CR802_TXF

#define DQ_CR802_TXF 0x20000

◆ DQ_CT651_CH_M_AUTO_DUTY

#define DQ_CT651_CH_M_AUTO_DUTY (7)

◆ DQ_CT651_CH_M_AUTO_FOL

#define DQ_CT651_CH_M_AUTO_FOL (3)

◆ DQ_CT651_CH_M_DIS_BUF

#define DQ_CT651_CH_M_DIS_BUF (0)

◆ DQ_CT651_CH_M_FLYWHEEL

#define DQ_CT651_CH_M_FLYWHEEL (2)

◆ DQ_CT651_CH_M_FOL_DUTY

#define DQ_CT651_CH_M_FOL_DUTY (6)

◆ DQ_CT651_CH_M_FOLLOW

#define DQ_CT651_CH_M_FOLLOW (1)

◆ DQ_CT651_CH_M_OUT_0

#define DQ_CT651_CH_M_OUT_0 (4)

◆ DQ_CT651_CH_M_OUT_1

#define DQ_CT651_CH_M_OUT_1 (5)

◆ DQ_CT651_CH_M_SYNC_0

#define DQ_CT651_CH_M_SYNC_0 (8)

◆ DQ_CT651_CH_M_SYNC_1

#define DQ_CT651_CH_M_SYNC_1 (9)

◆ DQ_CT651_CH_M_SYNC_2

#define DQ_CT651_CH_M_SYNC_2 (0xa)

◆ DQ_CT651_CH_M_SYNC_3

#define DQ_CT651_CH_M_SYNC_3 (0xb)

◆ DQ_CT651_CH_MODE_MASK

#define DQ_CT651_CH_MODE_MASK (0xf)

◆ DQ_CT651_DW_A_ALLAOUTS

#define DQ_CT651_DW_A_ALLAOUTS (7L<<16)

◆ DQ_CT651_DW_A_AOUTA

#define DQ_CT651_DW_A_AOUTA (0L<<16)

◆ DQ_CT651_DW_A_AOUTB

#define DQ_CT651_DW_A_AOUTB (1L<<16)

◆ DQ_CT651_DW_A_AOUTC

#define DQ_CT651_DW_A_AOUTC (2L<<16)

◆ DQ_CT651_DW_A_AOUTD

#define DQ_CT651_DW_A_AOUTD (3L<<16)

◆ DQ_CT651_DW_C_LD_LDAC

#define DQ_CT651_DW_C_LD_LDAC (6L<<19)

◆ DQ_CT651_DW_C_PWR_DN

#define DQ_CT651_DW_C_PWR_DN (4L<<19)

◆ DQ_CT651_DW_C_RESET

#define DQ_CT651_DW_C_RESET (5L<<19)

◆ DQ_CT651_DW_C_UPD_CH

#define DQ_CT651_DW_C_UPD_CH (1L<<19)

◆ DQ_CT651_DW_C_WR_UPD_CH

#define DQ_CT651_DW_C_WR_UPD_CH (3L<<19)

◆ DQ_CT651_DW_C_WRUPD_ALL

#define DQ_CT651_DW_C_WRUPD_ALL (2L<<19)

◆ DQ_CT651_DW_D_HYST_DEF

#define DQ_CT651_DW_D_HYST_DEF (0x800)

◆ DQ_CT651_DW_D_LSB

#define DQ_CT651_DW_D_LSB (1L<<0)

◆ DQ_CT651_DW_D_MIDSCALE

#define DQ_CT651_DW_D_MIDSCALE (0x8000)

◆ DQ_CT651_DW_D_MSB

#define DQ_CT651_DW_D_MSB (1L<<15)

◆ DQ_CT651_FWCFG_ACFWDC

#define DQ_CT651_FWCFG_ACFWDC (1L<<17)

◆ DQ_CT651_FWCFG_ACFWDIV

#define DQ_CT651_FWCFG_ACFWDIV (1L<<16)

◆ DQ_CT651_FWCFG_ACRFW

#define DQ_CT651_FWCFG_ACRFW (1L<<18)

◆ DQ_CT651_FWCFG_CH0

#define DQ_CT651_FWCFG_CH0 (0)

◆ DQ_CT651_FWCFG_CH0_M0

#define DQ_CT651_FWCFG_CH0_M0 (1L<<0)

◆ DQ_CT651_FWCFG_CH0_M3

#define DQ_CT651_FWCFG_CH0_M3 (1L<<3)

◆ DQ_CT651_FWCFG_CH1

#define DQ_CT651_FWCFG_CH1 (4)

◆ DQ_CT651_FWCFG_CH1_M0

#define DQ_CT651_FWCFG_CH1_M0 (1L<<4)

◆ DQ_CT651_FWCFG_CH1_M3

#define DQ_CT651_FWCFG_CH1_M3 (1L<<7)

◆ DQ_CT651_FWCFG_CH2

#define DQ_CT651_FWCFG_CH2 (8)

◆ DQ_CT651_FWCFG_CH2_M0

#define DQ_CT651_FWCFG_CH2_M0 (1L<<8)

◆ DQ_CT651_FWCFG_CH2_M3

#define DQ_CT651_FWCFG_CH2_M3 (1L<<11)

◆ DQ_CT651_FWCFG_CH3

#define DQ_CT651_FWCFG_CH3 (12)

◆ DQ_CT651_FWCFG_CH3_M0

#define DQ_CT651_FWCFG_CH3_M0 (1L<<12)

◆ DQ_CT651_FWCFG_CH3_M3

#define DQ_CT651_FWCFG_CH3_M3 (1L<<15)

◆ DQ_CT651_FWCFG_EIH

#define DQ_CT651_FWCFG_EIH (1L<<19)

◆ DQ_CT651_FWCLK_MAX_D0

#define DQ_CT651_FWCLK_MAX_D0 (1L<<0)

◆ DQ_CT651_FWCLK_MAX_D31

#define DQ_CT651_FWCLK_MAX_D31 (1L<<31)

◆ DQ_CT651_FWCLK_MIN_D0

#define DQ_CT651_FWCLK_MIN_D0 (1L<<0)

◆ DQ_CT651_FWCLK_MIN_D31

#define DQ_CT651_FWCLK_MIN_D31 (1L<<31)

◆ DQ_CT651_FWCNT_D0

#define DQ_CT651_FWCNT_D0 (1L<<0)

◆ DQ_CT651_FWCNT_D31

#define DQ_CT651_FWCNT_D31 (1L<<31)

◆ DQ_CT651_FWCRH_D0

#define DQ_CT651_FWCRH_D0 (1L<<0)

◆ DQ_CT651_FWCRH_D30

#define DQ_CT651_FWCRH_D30 (1L<<30)

◆ DQ_CT651_FWCRH_STOP

#define DQ_CT651_FWCRH_STOP (1L<<31)

◆ DQ_CT651_FWCRP_D0

#define DQ_CT651_FWCRP_D0 (1L<<0)

◆ DQ_CT651_FWCRP_D31

#define DQ_CT651_FWCRP_D31 (1L<<30)

◆ DQ_CT651_FWCRP_STOP

#define DQ_CT651_FWCRP_STOP (1L<<31)

◆ DQ_CT651_FWDC_D0

#define DQ_CT651_FWDC_D0 (1L<<0)

◆ DQ_CT651_FWDC_D31

#define DQ_CT651_FWDC_D31 (1L<<31)

◆ DQ_CT651_FWDIV_D0

#define DQ_CT651_FWDIV_D0 (1L<<0)

◆ DQ_CT651_FWDIV_D31

#define DQ_CT651_FWDIV_D31 (1L<<31)

◆ DQ_CT_651_BASE_100

#define DQ_CT_651_BASE_100 (100000000)

◆ DQ_CT_651_BASE_160

#define DQ_CT_651_BASE_160 (160000000)

◆ DQ_CT_651_BASE_66

#define DQ_CT_651_BASE_66 (66000000)

◆ DQ_CT_651_CHAN

#define DQ_CT_651_CHAN (4)

◆ DQ_CT_651_CHAN_MASK

#define DQ_CT_651_CHAN_MASK (0x3)

◆ DQ_CT_651_INFOSZ

#define DQ_CT_651_INFOSZ (DQ_MAX_INFO_SIZE)

◆ DQ_CTR_CLFI

#define DQ_CTR_CLFI 23

◆ DQ_CTR_CLFO

#define DQ_CTR_CLFO 22

◆ DQ_CTR_CLR

#define DQ_CTR_CLR 21

◆ DQ_CTR_EN

#define DQ_CTR_EN 31

◆ DQ_CTR_GIE

#define DQ_CTR_GIE 27

◆ DQ_CTR_GPIO

#define DQ_CTR_GPIO 20

◆ DQ_CTR_GTPE

#define DQ_CTR_GTPE 18

◆ DQ_CTR_GTSE

#define DQ_CTR_GTSE 19

◆ DQ_CTR_IFE

#define DQ_CTR_IFE 30

◆ DQ_CTR_IFS

#define DQ_CTR_IFS 29

◆ DQ_CTR_IIE

#define DQ_CTR_IIE 28

◆ DQ_CTR_OFE

#define DQ_CTR_OFE 24

◆ DQ_CTR_OIE

#define DQ_CTR_OIE 26

◆ DQ_CTR_OU

#define DQ_CTR_OU 25

◆ DQ_CTU_CCR

#define DQ_CTU_CCR 0x04

◆ DQ_CTU_CR

#define DQ_CTU_CR 0x0C

◆ DQ_CTU_CR0

#define DQ_CTU_CR0 0x1C

◆ DQ_CTU_CR1

#define DQ_CTU_CR1 0x20

◆ DQ_CTU_CRH

#define DQ_CTU_CRH 0x1C

◆ DQ_CTU_CRL

#define DQ_CTU_CRL 0x20

◆ DQ_CTU_CTR

#define DQ_CTU_CTR 0x00

◆ DQ_CTU_FCNTI

#define DQ_CTU_FCNTI 0x28

◆ DQ_CTU_FCNTO

#define DQ_CTU_FCNTO 0x34

◆ DQ_CTU_FDDO

#define DQ_CTU_FDDO 0x48

◆ DQ_CTU_FDTI

#define DQ_CTU_FDTI 0x30

◆ DQ_CTU_FDTO

#define DQ_CTU_FDTO 0x3C

◆ DQ_CTU_ICR

#define DQ_CTU_ICR 0x44

◆ DQ_CTU_IDBC

#define DQ_CTU_IDBC 0x10

◆ DQ_CTU_IDBG

#define DQ_CTU_IDBG 0x14

◆ DQ_CTU_IER

#define DQ_CTU_IER 0x40

◆ DQ_CTU_IFWR

#define DQ_CTU_IFWR 0x2C

◆ DQ_CTU_ISR

#define DQ_CTU_ISR 0x40

◆ DQ_CTU_LR

#define DQ_CTU_LR 0x0C

◆ DQ_CTU_OFWR

#define DQ_CTU_OFWR 0x38

◆ DQ_CTU_PC

#define DQ_CTU_PC 0x18

◆ DQ_CTU_PS

#define DQ_CTU_PS 0x08

◆ DQ_CTU_REGADDR

#define DQ_CTU_REGADDR ( CLE ) (0x2000|CLE)

◆ DQ_CTU_STR

#define DQ_CTU_STR 0x00

◆ DQ_CTU_TBR

#define DQ_CTU_TBR 0x24

◆ DQ_CTU_TEST0

#define DQ_CTU_TEST0 0x4C

◆ DQ_CTU_TEST1

#define DQ_CTU_TEST1 0x50

◆ DQ_DEVNAME_SIZE

#define DQ_DEVNAME_SIZE (40)

◆ DQ_DIO403_BASE

#define DQ_DIO403_BASE BUS_FREQUENCY

◆ DQ_DIO403_CHAN

#define DQ_DIO403_CHAN 2

◆ DQ_DIO403_CHANSVC

#define DQ_DIO403_CHANSVC 2

◆ DQ_DIO403_ENPORT0

#define DQ_DIO403_ENPORT0 (1UL << 23)

◆ DQ_DIO403_ENPORT1

#define DQ_DIO403_ENPORT1 (1UL << 24)

◆ DQ_DIO403_ENPORT2

#define DQ_DIO403_ENPORT2 (1UL << 25)

◆ DQ_DIO403_ENPORT3

#define DQ_DIO403_ENPORT3 (1UL << 26)

◆ DQ_DIO403_ENPORT4

#define DQ_DIO403_ENPORT4 (1UL << 27)

◆ DQ_DIO403_ENPORT5

#define DQ_DIO403_ENPORT5 (1UL << 28)

◆ DQ_DIO403_FIFO_GET_DATA

#define DQ_DIO403_FIFO_GET_DATA DQ_FIFO_GET_DATA

◆ DQ_DIO403_FIFO_SET_DATA

#define DQ_DIO403_FIFO_SET_DATA DQ_FIFO_SET_DATA

◆ DQ_DIO403_INFOSZ

#define DQ_DIO403_INFOSZ DQ_MAX_INFO_SIZE

◆ DQ_DIO403_LINES

#define DQ_DIO403_LINES 48

◆ DQ_DIO403_MAXCVFRQ

#define DQ_DIO403_MAXCVFRQ 10000

◆ DQ_DIO403_MODECONT

#define DQ_DIO403_MODECONT (DQ_FIFO_MODECONT)

◆ DQ_DIO403_MODEFIFO

#define DQ_DIO403_MODEFIFO (DQ_FIFO_MODEFIFO)

◆ DQ_DIO403_MODESCAN

#define DQ_DIO403_MODESCAN (DQ_FIFO_MODESCAN)

◆ DQ_DIO403_NAMELEN

#define DQ_DIO403_NAMELEN 10

◆ DQ_DIO403_PORTS

#define DQ_DIO403_PORTS 6

◆ DQ_DIO416_BASE

#define DQ_DIO416_BASE BUS_FREQUENCY

◆ DQ_DIO416_CHAN

#define DQ_DIO416_CHAN (16)

◆ DQ_DIO416_INFOSZ

#define DQ_DIO416_INFOSZ DQ_MAX_INFO_SIZE

◆ DQ_DIO416_MAXCLFRQ

#define DQ_DIO416_MAXCLFRQ 100000

◆ DQ_DIO416_MAXCVFRQ

#define DQ_DIO416_MAXCVFRQ 100000

◆ DQ_DIO432_BASE

#define DQ_DIO432_BASE BUS_FREQUENCY

◆ DQ_DIO432_CHAN

#define DQ_DIO432_CHAN (32)

◆ DQ_DIO432_INFOSZ

#define DQ_DIO432_INFOSZ DQ_MAX_INFO_SIZE

◆ DQ_DIO432_MAXCLFRQ

#define DQ_DIO432_MAXCLFRQ 100000

◆ DQ_DIO432_MAXCVFRQ

#define DQ_DIO432_MAXCVFRQ 100000

◆ DQ_DIO432_PORT0ACT_CH

#define DQ_DIO432_PORT0ACT_CH 0x42

◆ DQ_DIO432_PORT0OCS_CH

#define DQ_DIO432_PORT0OCS_CH 0x40

◆ DQ_DIO432_PORT1ACT_CH

#define DQ_DIO432_PORT1ACT_CH 0x43

◆ DQ_DIO432_PORT1OCS_CH

#define DQ_DIO432_PORT1OCS_CH 0x41

◆ DQ_DIO448_BASE

#define DQ_DIO448_BASE BUS_FREQUENCY

◆ DQ_DIO448_CALDACS

#define DQ_DIO448_CALDACS 4

◆ DQ_DIO448_CHAN

#define DQ_DIO448_CHAN 2

◆ DQ_DIO448_CHANSVC

#define DQ_DIO448_CHANSVC 52

◆ DQ_DIO448_CVT_CHNL

#define DQ_DIO448_CVT_CHNL ( V ) ((((float)V)*DQ_DIO448_STEP)-(DQ_DIO448_RANGE/2))

◆ DQ_DIO448_INFOSZ

#define DQ_DIO448_INFOSZ DQ_MAX_INFO_SIZE

◆ DQ_DIO448_LINES

#define DQ_DIO448_LINES 48

◆ DQ_DIO448_MAX_Hyst

#define DQ_DIO448_MAX_Hyst 30.0

◆ DQ_DIO448_MAX_Offset

#define DQ_DIO448_MAX_Offset 250

◆ DQ_DIO448_MAX_uVCnt

#define DQ_DIO448_MAX_uVCnt 800

◆ DQ_DIO448_MIN_uVCnt

#define DQ_DIO448_MIN_uVCnt 600

◆ DQ_DIO448_NAMELEN

#define DQ_DIO448_NAMELEN 10

◆ DQ_DIO448_PORTS

#define DQ_DIO448_PORTS 2

◆ DQ_DIO448_RANGE

#define DQ_DIO448_RANGE 45.0

◆ DQ_DIO448_STEP

#define DQ_DIO448_STEP 0.000686646

◆ DQ_DIO462_ADC0_CFG_G1

#define DQ_DIO462_ADC0_CFG_G1 (0xB080)

◆ DQ_DIO462_ADC0_CFG_G1_2X

#define DQ_DIO462_ADC0_CFG_G1_2X (0xB088)

◆ DQ_DIO462_ADC1_CFG_G1

#define DQ_DIO462_ADC1_CFG_G1 (0xB880)

◆ DQ_DIO462_ADC1_CFG_G1_2X

#define DQ_DIO462_ADC1_CFG_G1_2X (0xB888)

◆ DQ_DIO462_ADC1_CFG_G8

#define DQ_DIO462_ADC1_CFG_G8 (0xB882)

◆ DQ_DIO462_ADC1_CFG_G8_2X

#define DQ_DIO462_ADC1_CFG_G8_2X (0xB88b)

◆ DQ_DIO462_ADC2_CFG_G1

#define DQ_DIO462_ADC2_CFG_G1 (0xB180)

◆ DQ_DIO462_ADC2_CFG_G1_2X

#define DQ_DIO462_ADC2_CFG_G1_2X (0xB188)

◆ DQ_DIO462_ADC2_CFG_G2_2X

#define DQ_DIO462_ADC2_CFG_G2_2X (0xB189)

◆ DQ_DIO462_ADC2_CFG_G4_2X

#define DQ_DIO462_ADC2_CFG_G4_2X (0xB18a)

◆ DQ_DIO462_ADC2_CFG_G8

#define DQ_DIO462_ADC2_CFG_G8 (0xB182)

◆ DQ_DIO462_ADC2_CFG_G8_2X

#define DQ_DIO462_ADC2_CFG_G8_2X (0xB18b)

◆ DQ_DIO462_ADC3_CFG_G1

#define DQ_DIO462_ADC3_CFG_G1 (0xB980)

◆ DQ_DIO462_ADC3_CFG_G1_2X

#define DQ_DIO462_ADC3_CFG_G1_2X (0xB988)

◆ DQ_DIO462_ADC4_CFG

#define DQ_DIO462_ADC4_CFG (0xB0C0)

◆ DQ_DIO462_ADC_CHAN_CHAN

#define DQ_DIO462_ADC_CHAN_CHAN (5)

◆ DQ_DIO462_ADC_CHAN_MASK

#define DQ_DIO462_ADC_CHAN_MASK (0x07)

◆ DQ_DIO462_ADC_CHANS

#define DQ_DIO462_ADC_CHANS (DQ_DIO462_CHAN*DQ_DIO462_ADC_CHAN_CHAN)

◆ DQ_DIO462_ADC_EOC

#define DQ_DIO462_ADC_EOC (1L<<18)

◆ DQ_DIO462_ADC_MSB

#define DQ_DIO462_ADC_MSB (1L<<15)

◆ DQ_DIO462_ADC_SETTLE_1

#define DQ_DIO462_ADC_SETTLE_1 (0x10)

◆ DQ_DIO462_ADC_SETTLE_1_2X

#define DQ_DIO462_ADC_SETTLE_1_2X (0x8)

◆ DQ_DIO462_ADC_SIG

#define DQ_DIO462_ADC_SIG (1L<<16)

◆ DQ_DIO462_ADC_VREF

#define DQ_DIO462_ADC_VREF (3.0)

◆ DQ_DIO462_BASE

#define DQ_DIO462_BASE (BUS_FREQUENCY)

◆ DQ_DIO462_CH_MASK

#define DQ_DIO462_CH_MASK (0xf)

◆ DQ_DIO462_CHAN

#define DQ_DIO462_CHAN (12)

◆ DQ_DIO462_CL_MASK

#define DQ_DIO462_CL_MASK (0x7f)

◆ DQ_DIO462_CL_UNCALFLAG

#define DQ_DIO462_CL_UNCALFLAG (0x80)

◆ DQ_DIO462_DCDCCFG

#define DQ_DIO462_DCDCCFG (0x5f)

◆ DQ_DIO462_DCDCCFG_MAX

#define DQ_DIO462_DCDCCFG_MAX (0x5f)

◆ DQ_DIO462_DCDCCFG_MIN

#define DQ_DIO462_DCDCCFG_MIN (0x1E)

◆ DQ_DIO462_DCDCX

#define DQ_DIO462_DCDCX ( N ) (DQ_DIO462_DCDCX_START+((N)*DQ_DIO462_DCDCX_CH_SP)+((DQ_DIO462_DCDCX_START+DQ_DIO462_DCDCX_WIDTH+((N)*DQ_DIO462_DCDCX_CH_SP))<<16))

◆ DQ_DIO462_DCDCX_0

#define DQ_DIO462_DCDCX_0 (DQ_DIO462_DCDCX_START+(0*DQ_DIO462_DCDCX_CH_SP)+((DQ_DIO462_DCDCX_START+DQ_DIO462_DCDCX_WIDTH+(0*DQ_DIO462_DCDCX_CH_SP))<<16))

◆ DQ_DIO462_DCDCX_1

#define DQ_DIO462_DCDCX_1 (DQ_DIO462_DCDCX_START+(1*DQ_DIO462_DCDCX_CH_SP)+((DQ_DIO462_DCDCX_START+DQ_DIO462_DCDCX_WIDTH+(1*DQ_DIO462_DCDCX_CH_SP))<<16))

◆ DQ_DIO462_DCDCX_2

#define DQ_DIO462_DCDCX_2 (DQ_DIO462_DCDCX_START+(2*DQ_DIO462_DCDCX_CH_SP)+((DQ_DIO462_DCDCX_START+DQ_DIO462_DCDCX_WIDTH+(2*DQ_DIO462_DCDCX_CH_SP))<<16))

◆ DQ_DIO462_DCDCX_3

#define DQ_DIO462_DCDCX_3 (DQ_DIO462_DCDCX_START+(3*DQ_DIO462_DCDCX_CH_SP)+((DQ_DIO462_DCDCX_START+DQ_DIO462_DCDCX_WIDTH+(3*DQ_DIO462_DCDCX_CH_SP))<<16))

◆ DQ_DIO462_DCDCX_CH_SP

#define DQ_DIO462_DCDCX_CH_SP (DQ_DIO462_DCDCCFG/4)

◆ DQ_DIO462_DCDCX_START

#define DQ_DIO462_DCDCX_START (0x3)

◆ DQ_DIO462_DCDCX_WIDTH

#define DQ_DIO462_DCDCX_WIDTH (0xb)

◆ DQ_DIO462_DEF_GAIN_CAL

#define DQ_DIO462_DEF_GAIN_CAL (0x8000)

◆ DQ_DIO462_DEF_OFFSET_CAL

#define DQ_DIO462_DEF_OFFSET_CAL (0)

◆ DQ_DIO462_DFLT_RDCNT

#define DQ_DIO462_DFLT_RDCNT (3)

◆ DQ_DIO462_DISABLE_BREAKER

#define DQ_DIO462_DISABLE_BREAKER (5)

◆ DQ_DIO462_I_SCALER

#define DQ_DIO462_I_SCALER (1.0/DQ_DIO462_ISH)

◆ DQ_DIO462_IAC_ADCGAIN

#define DQ_DIO462_IAC_ADCGAIN (1.0)

◆ DQ_DIO462_IAC_BGAIN

#define DQ_DIO462_IAC_BGAIN (19.21)

◆ DQ_DIO462_IAC_OFFSET

#define DQ_DIO462_IAC_OFFSET ((DQ_DIO462_IAC_SPAN/2.0)+(DQ_DIO462_IAC_STEP/2.0))

◆ DQ_DIO462_IAC_SCALER

#define DQ_DIO462_IAC_SCALER ((DQ_DIO462_I_SCALER)/DQ_DIO462_IAC_BGAIN)

◆ DQ_DIO462_IAC_SPAN

#define DQ_DIO462_IAC_SPAN ((DQ_DIO462_ADC_VREF)/DQ_DIO462_IAC_ADCGAIN)

◆ DQ_DIO462_IAC_STEP

#define DQ_DIO462_IAC_STEP (DQ_DIO462_IAC_SPAN/(double)0xffff)

◆ DQ_DIO462_IDC_ADCGAIN

#define DQ_DIO462_IDC_ADCGAIN (8.0)

◆ DQ_DIO462_IDC_OFFSET

#define DQ_DIO462_IDC_OFFSET ((DQ_DIO462_IDC_SPAN/2.0)+(DQ_DIO462_IDC_STEP/2.0))

◆ DQ_DIO462_IDC_SCALER

#define DQ_DIO462_IDC_SCALER (-DQ_DIO462_I_SCALER)

◆ DQ_DIO462_IDC_SPAN

#define DQ_DIO462_IDC_SPAN ((DQ_DIO462_ADC_VREF)/DQ_DIO462_IDC_ADCGAIN)

◆ DQ_DIO462_IDC_STEP

#define DQ_DIO462_IDC_STEP (DQ_DIO462_IDC_SPAN/(double)0xffff)

◆ DQ_DIO462_INFOSZ

#define DQ_DIO462_INFOSZ (DQ_MAX_INFO_SIZE)

◆ DQ_DIO462_ISH

#define DQ_DIO462_ISH (0.02)

◆ DQ_DIO462_ISO_DC_NUM

#define DQ_DIO462_ISO_DC_NUM (4)

◆ DQ_DIO462_MAKE_CL

#define DQ_DIO462_MAKE_CL	(	CH,
		SUBCH
	)	((((CH)&DQ_DIO462_CH_MASK)<<3)\|((SUBCH)& DQ_DIO462_ADC_CHAN_MASK))

◆ DQ_DIO462_MAXCVFRQ

#define DQ_DIO462_MAXCVFRQ (100000.0)

◆ DQ_DIO462_SUBCH_I_AC

#define DQ_DIO462_SUBCH_I_AC (1)

◆ DQ_DIO462_SUBCH_I_DC

#define DQ_DIO462_SUBCH_I_DC (2)

◆ DQ_DIO462_SUBCH_THERM

#define DQ_DIO462_SUBCH_THERM (4)

◆ DQ_DIO462_SUBCH_V_NC

#define DQ_DIO462_SUBCH_V_NC (3)

◆ DQ_DIO462_SUBCH_V_NO

#define DQ_DIO462_SUBCH_V_NO (0)

◆ DQ_DIO462_T_OFFSET

#define DQ_DIO462_T_OFFSET (273.0)

◆ DQ_DIO462_T_SLOPE

#define DQ_DIO462_T_SLOPE ((0.0000935)/DQ_DIO462_V_STEP)

◆ DQ_DIO462_UNDER_LIMIT_OFFS

#define DQ_DIO462_UNDER_LIMIT_OFFS (0x10)

◆ DQ_DIO462_V_ADCGAIN

#define DQ_DIO462_V_ADCGAIN (1.0)

◆ DQ_DIO462_V_OFFSET

#define DQ_DIO462_V_OFFSET ((DQ_DIO462_V_SPAN/2.0)+(DQ_DIO462_V_STEP/2.0))

◆ DQ_DIO462_V_SCALER

#define DQ_DIO462_V_SCALER (101.0)

◆ DQ_DIO462_V_SPAN

#define DQ_DIO462_V_SPAN (DQ_DIO462_ADC_VREF/DQ_DIO462_V_ADCGAIN)

◆ DQ_DIO462_V_STEP

#define DQ_DIO462_V_STEP (DQ_DIO462_V_SPAN/(double)0xffff)

◆ DQ_DIR_INPUT

#define DQ_DIR_INPUT (0)

◆ DQ_DIR_MASK

#define DQ_DIR_MASK (1)

◆ DQ_DIR_OUTPUT

#define DQ_DIR_OUTPUT (1)

◆ DQ_DMAP_DMAP

#define DQ_DMAP_DMAP (0x0000)

◆ DQ_DMAP_IDMASK

#define DQ_DMAP_IDMASK (0xfff)

◆ DQ_DMAP_LASTID_IN

#define DQ_DMAP_LASTID_IN (0x0FF0L)

◆ DQ_DMAP_LASTID_OUT

#define DQ_DMAP_LASTID_OUT (0x0FF1L)

◆ DQ_DMAP_MODEMASK

#define DQ_DMAP_MODEMASK (0xf000)

◆ DQ_DMAP_RESET_TRL

#define DQ_DMAP_RESET_TRL (1L<<31)

◆ DQ_DMAP_VMAP

#define DQ_DMAP_VMAP (0x1000)

◆ DQ_DQPKT_OFFS

#define DQ_DQPKT_OFFS (ETH_HDR_SIZE + IP_HDR_SIZE + UDP_HDR_SIZE)

◆ DQ_EDGE_FALLING

#define DQ_EDGE_FALLING (1)

◆ DQ_EDGE_RISING

#define DQ_EDGE_RISING (0)

◆ DQ_EM_CR0

#define DQ_EM_CR0 (0)

◆ DQ_EM_CR1

#define DQ_EM_CR1 (1)

◆ DQ_EM_FFF

#define DQ_EM_FFF (2)

◆ DQ_EM_GT

#define DQ_EM_GT (5)

◆ DQ_EM_PC

#define DQ_EM_PC (3)

◆ DQ_EM_TBR

#define DQ_EM_TBR (4)

◆ DQ_EXT_ADCBS

#define DQ_EXT_ADCBS (0x2F)

◆ DQ_EXT_ADCCVT

#define DQ_EXT_ADCCVT (0x2C)

◆ DQ_EXT_BOTH_CV_CL_FLAG

#define DQ_EXT_BOTH_CV_CL_FLAG (0x10)

◆ DQ_EXT_BURST

#define DQ_EXT_BURST (0x32)

◆ DQ_EXT_CLIN

#define DQ_EXT_CLIN (0x22)

◆ DQ_EXT_CLIN_OFS

#define DQ_EXT_CLIN_OFS (0)

◆ DQ_EXT_CLKIN

#define DQ_EXT_CLKIN (0x30)

◆ DQ_EXT_CLKIN_J3_10

#define DQ_EXT_CLKIN_J3_10 (DQ_EXT_EXT0)

◆ DQ_EXT_CLKOUT_J3_8

#define DQ_EXT_CLKOUT_J3_8 (DQ_EXT_INT0)

◆ DQ_EXT_CLOCK

#define DQ_EXT_CLOCK (0x33)

◆ DQ_EXT_CLOUT

#define DQ_EXT_CLOUT (0x23)

◆ DQ_EXT_CLOUT_OFS

#define DQ_EXT_CLOUT_OFS (1)

◆ DQ_EXT_CVIN

#define DQ_EXT_CVIN (0x24)

◆ DQ_EXT_CVIN_OFS

#define DQ_EXT_CVIN_OFS (2)

◆ DQ_EXT_CVOUT

#define DQ_EXT_CVOUT (0x25)

◆ DQ_EXT_CVOUT_OFS

#define DQ_EXT_CVOUT_OFS (3)

◆ DQ_EXT_DIO0

#define DQ_EXT_DIO0 (0x2A)

◆ DQ_EXT_DIO0_OFFS

#define DQ_EXT_DIO0_OFFS (0)

◆ DQ_EXT_DIO1

#define DQ_EXT_DIO1 (0x2B)

◆ DQ_EXT_DIO1_OFFS

#define DQ_EXT_DIO1_OFFS (1)

◆ DQ_EXT_DIO2_OFFS

#define DQ_EXT_DIO2_OFFS (2)

◆ DQ_EXT_DIO3_OFFS

#define DQ_EXT_DIO3_OFFS (3)

◆ DQ_EXT_DIO_DEFAULT

#define DQ_EXT_DIO_DEFAULT (0x0)

◆ DQ_EXT_DIO_INPUT

#define DQ_EXT_DIO_INPUT (0x1)

◆ DQ_EXT_DIO_INVERTED

#define DQ_EXT_DIO_INVERTED (0x10)

◆ DQ_EXT_DIO_OUTPUT

#define DQ_EXT_DIO_OUTPUT (0x2)

◆ DQ_EXT_EXT0

#define DQ_EXT_EXT0 (0x34)

◆ DQ_EXT_EXT1

#define DQ_EXT_EXT1 (0x35)

◆ DQ_EXT_GPIO_LOGIC0

#define DQ_EXT_GPIO_LOGIC0 (0x26)

◆ DQ_EXT_GPIO_LOGIC1

#define DQ_EXT_GPIO_LOGIC1 (0x27)

◆ DQ_EXT_IMMEDIATE

#define DQ_EXT_IMMEDIATE (0x80)

◆ DQ_EXT_INT0

#define DQ_EXT_INT0 (0x28)

◆ DQ_EXT_INT1

#define DQ_EXT_INT1 (0x29)

◆ DQ_EXT_INTER0

#define DQ_EXT_INTER0 (0x36)

◆ DQ_EXT_PUSH_BUTTON

#define DQ_EXT_PUSH_BUTTON (0x2E)

◆ DQ_EXT_RELEASE

#define DQ_EXT_RELEASE (0)

◆ DQ_EXT_SIG_CMD_DEF

#define DQ_EXT_SIG_CMD_DEF (0)

◆ DQ_EXT_SIG_CMD_DIO_R

#define DQ_EXT_SIG_CMD_DIO_R (2)

◆ DQ_EXT_SIG_CMD_DIO_RW

#define DQ_EXT_SIG_CMD_DIO_RW (1)

◆ DQ_EXT_SIG_CMD_SET_SYS

#define DQ_EXT_SIG_CMD_SET_SYS (0x20)

◆ DQ_EXT_START_TRIG

#define DQ_EXT_START_TRIG (0x20)

◆ DQ_EXT_START_TRIG_OFS

#define DQ_EXT_START_TRIG_OFS (0)

◆ DQ_EXT_STOP_TRIG

#define DQ_EXT_STOP_TRIG (0x21)

◆ DQ_EXT_STOP_TRIG_OFS

#define DQ_EXT_STOP_TRIG_OFS (1)

◆ DQ_EXT_SYNC0

#define DQ_EXT_SYNC0 (0x10)

◆ DQ_EXT_SYNC0_OFS

#define DQ_EXT_SYNC0_OFS (0)

◆ DQ_EXT_SYNC1

#define DQ_EXT_SYNC1 (0x11)

◆ DQ_EXT_SYNC1_OFS

#define DQ_EXT_SYNC1_OFS (1)

◆ DQ_EXT_SYNC2

#define DQ_EXT_SYNC2 (0x12)

◆ DQ_EXT_SYNC2_OFS

#define DQ_EXT_SYNC2_OFS (2)

◆ DQ_EXT_SYNC3

#define DQ_EXT_SYNC3 (0x13)

◆ DQ_EXT_SYNC3_OFS

#define DQ_EXT_SYNC3_OFS (3)

◆ DQ_EXT_TRIGIN

#define DQ_EXT_TRIGIN (0x31)

◆ DQ_EXT_TRIGIN_J3_6

#define DQ_EXT_TRIGIN_J3_6 (DQ_EXT_EXT1)

◆ DQ_EXT_TRIGOUT_J3_4

#define DQ_EXT_TRIGOUT_J3_4 (DQ_EXT_INT1)

◆ DQ_EXT_TSTD

#define DQ_EXT_TSTD (0x2D)

◆ DQ_EXTRACT_DIR

#define DQ_EXTRACT_DIR ( flags ) (((flags) & DQ_LNCL_INOUT) >> 30)

◆ DQ_EXTRACT_SS

#define DQ_EXTRACT_SS ( flags ) (((flags) & (DQ_LNCL_SS1 | DQ_LNCL_SS0)) >> 28)

◆ DQ_FGC_MSGSIZE

#define DQ_FGC_MSGSIZE 8

◆ DQ_FIFO_ALLOC_AT_ONCE

#define DQ_FIFO_ALLOC_AT_ONCE (1)

◆ DQ_FIFO_BUF_MAX

#define DQ_FIFO_BUF_MAX (4096)

◆ DQ_FIFO_BUF_SEC

#define DQ_FIFO_BUF_SEC (5)

◆ DQ_FIFO_CLPERINT

#define DQ_FIFO_CLPERINT (0)

◆ DQ_FIFO_GET_CAL

#define DQ_FIFO_GET_CAL (0x20)

◆ DQ_FIFO_GET_CUSTOM

#define DQ_FIFO_GET_CUSTOM (0x30)

◆ DQ_FIFO_GET_DATA

#define DQ_FIFO_GET_DATA (0x10)

◆ DQ_FIFO_MODECONT

#define DQ_FIFO_MODECONT (3L<<16)

◆ DQ_FIFO_MODEFIFO

#define DQ_FIFO_MODEFIFO (2L<<16)

◆ DQ_FIFO_MODESCAN

#define DQ_FIFO_MODESCAN (0L<<16)

◆ DQ_FIFO_NBUFS

#define DQ_FIFO_NBUFS (1024)

◆ DQ_FIFO_NBUFS_FAST

#define DQ_FIFO_NBUFS_FAST (2048)

◆ DQ_FIFO_NBUFS_MED

#define DQ_FIFO_NBUFS_MED (1024)

◆ DQ_FIFO_NBUFS_MIN

#define DQ_FIFO_NBUFS_MIN (64)

◆ DQ_FIFO_NBUFS_MSG

#define DQ_FIFO_NBUFS_MSG (1024)

◆ DQ_FIFO_NBUFS_SLOW

#define DQ_FIFO_NBUFS_SLOW (512)

◆ DQ_FIFO_PUT_COEFF

#define DQ_FIFO_PUT_COEFF (0x20)

◆ DQ_FIFO_PUT_CUSTOM

#define DQ_FIFO_PUT_CUSTOM (0x30)

◆ DQ_FIFO_REDUCE_FAST

#define DQ_FIFO_REDUCE_FAST (256)

◆ DQ_FIFO_REDUCE_MED

#define DQ_FIFO_REDUCE_MED (128)

◆ DQ_FIFO_REDUCE_MSG

#define DQ_FIFO_REDUCE_MSG (128)

◆ DQ_FIFO_REDUCE_SLOW

#define DQ_FIFO_REDUCE_SLOW (64)

◆ DQ_FIFO_SET_DATA

#define DQ_FIFO_SET_DATA (0x10)

◆ DQ_FIRMWARE_ENTRY_ROM

#define DQ_FIRMWARE_ENTRY_ROM (0xFFC10000)

◆ DQ_FLASH_ADDRESS

#define DQ_FLASH_ADDRESS (DQ_PPC_FLASH_ADDRESS)

◆ DQ_FLASH_FIRMWARE_OFFSET

#define DQ_FLASH_FIRMWARE_OFFSET (DQ_PPC_FLASH_FIRMWARE_OFFSET)

◆ DQ_FLASH_SIZE

#define DQ_FLASH_SIZE (DQ_PPC_FLASH_SIZE)

◆ DQ_FPGAC_ASDO

#define DQ_FPGAC_ASDO (1L<< 5)

◆ DQ_FPGAC_ASPGEN

#define DQ_FPGAC_ASPGEN (1L<< 6)

◆ DQ_FPGAC_DCLR0

#define DQ_FPGAC_DCLR0 (1L<< 8)

◆ DQ_FPGAC_DCLR1

#define DQ_FPGAC_DCLR1 (1L<< 9)

◆ DQ_FPGAC_DOE0

#define DQ_FPGAC_DOE0 (1L<<10)

◆ DQ_FPGAC_DOE1

#define DQ_FPGAC_DOE1 (1L<<11)

◆ DQ_FPGAC_ED

#define DQ_FPGAC_ED (1L<< 7)

◆ DQ_FPGAC_MSEL0

#define DQ_FPGAC_MSEL0 (1L<<12)

◆ DQ_FPGAC_MSEL1

#define DQ_FPGAC_MSEL1 (1L<<13)

◆ DQ_FPGAC_NCEO

#define DQ_FPGAC_NCEO (1L<< 4)

◆ DQ_FPGAC_NCFG

#define DQ_FPGAC_NCFG (1L<<14)

◆ DQ_FPGAC_NCSO

#define DQ_FPGAC_NCSO (1L<< 3)

◆ DQ_FPGAC_PRGEN

#define DQ_FPGAC_PRGEN (1L<<15)

◆ DQ_FPGAC_RESERVED0

#define DQ_FPGAC_RESERVED0 (1L<< 0)

◆ DQ_FPGAC_RESERVED1

#define DQ_FPGAC_RESERVED1 (1L<< 1)

◆ DQ_FPGAC_RESERVED2

#define DQ_FPGAC_RESERVED2 (1L<< 2)

◆ DQ_FPGAS_ASDO

#define DQ_FPGAS_ASDO (1L<< 4)

◆ DQ_FPGAS_CONFDONE

#define DQ_FPGAS_CONFDONE (1L<< 9)

◆ DQ_FPGAS_DATA0

#define DQ_FPGAS_DATA0 (1L<< 7)

◆ DQ_FPGAS_DCLK

#define DQ_FPGAS_DCLK (1L<< 8)

◆ DQ_FPGAS_DCLR

#define DQ_FPGAS_DCLR (1L<< 0)

◆ DQ_FPGAS_DOE

#define DQ_FPGAS_DOE (1L<< 1)

◆ DQ_FPGAS_MSEL0

#define DQ_FPGAS_MSEL0 (1L<< 5)

◆ DQ_FPGAS_MSEL1

#define DQ_FPGAS_MSEL1 (1L<< 6)

◆ DQ_FPGAS_NCEO

#define DQ_FPGAS_NCEO (1L<< 3)

◆ DQ_FPGAS_NCFG

#define DQ_FPGAS_NCFG (1L<<11)

◆ DQ_FPGAS_NCSO

#define DQ_FPGAS_NCSO (1L<< 2)

◆ DQ_FPGAS_NSTAT

#define DQ_FPGAS_NSTAT (1L<<10)

◆ DQ_FPGAS_RDY

#define DQ_FPGAS_RDY (1L<<12)

◆ DQ_FRCNT_COUNT_ALL

#define DQ_FRCNT_COUNT_ALL (0L<<14)

◆ DQ_FRCNT_COUNT_FIFO

#define DQ_FRCNT_COUNT_FIFO (2L<<14)

◆ DQ_FRCNT_COUNT_GOOD

#define DQ_FRCNT_COUNT_GOOD (1L<<14)

◆ DQ_FRCNT_COUNT_OFFSET

#define DQ_FRCNT_COUNT_OFFSET (14)

◆ DQ_FRCNT_COUNT_PAR_ERR

#define DQ_FRCNT_COUNT_PAR_ERR (4L<<14)

◆ DQ_FRCNT_COUNT_TRIGGER

#define DQ_FRCNT_COUNT_TRIGGER (3L<<14)

◆ DQ_ICR_CTU0

#define DQ_ICR_CTU0 (1L<<0)

◆ DQ_ICR_CTU1

#define DQ_ICR_CTU1 (1L<<1)

◆ DQ_ICR_CTU2

#define DQ_ICR_CTU2 (1L<<2)

◆ DQ_ICR_CTU3

#define DQ_ICR_CTU3 (1L<<3)

◆ DQ_ICR_CTU4

#define DQ_ICR_CTU4 (1L<<4)

◆ DQ_ICR_CTU5

#define DQ_ICR_CTU5 (1L<<5)

◆ DQ_ICR_CTU6

#define DQ_ICR_CTU6 (1L<<6)

◆ DQ_ICR_CTU7

#define DQ_ICR_CTU7 (1L<<7)

◆ DQ_ICR_QDU0

#define DQ_ICR_QDU0 0

◆ DQ_ICR_QDU1

#define DQ_ICR_QDU1 1

◆ DQ_ICR_QDU2

#define DQ_ICR_QDU2 2

◆ DQ_ICR_QDU3

#define DQ_ICR_QDU3 3

◆ DQ_ICR_QDU_MASK

#define DQ_ICR_QDU_MASK (0xf)

◆ DQ_IOCTL3XX_RD_TEST_CVT

#define DQ_IOCTL3XX_RD_TEST_CVT (1L)

◆ DQ_IOCTL3XX_RD_TEST_END

#define DQ_IOCTL3XX_RD_TEST_END (2L)

◆ DQ_IOCTL3XX_RD_TEST_INIT

#define DQ_IOCTL3XX_RD_TEST_INIT (0L)

◆ DQ_IOM_ACCESS_CALIBR

#define DQ_IOM_ACCESS_CALIBR (DQ_IOMODE_CFG)

◆ DQ_IOM_ACCESS_EECMNDEVS

#define DQ_IOM_ACCESS_EECMNDEVS (DQ_IOMODE_EECMNDEVS)

◆ DQ_IOM_ACCESS_GETPRM

#define DQ_IOM_ACCESS_GETPRM (DQ_IOMODE_GETPRM)

◆ DQ_IOM_ACCESS_INIT

#define DQ_IOM_ACCESS_INIT (DQ_IOMODE_INIT)

◆ DQ_IOM_ACCESS_MODEMASK

#define DQ_IOM_ACCESS_MODEMASK (DQ_IOMODE_MODEMASK)

◆ DQ_IOM_ACCESS_NAMEDPRM

#define DQ_IOM_ACCESS_NAMEDPRM (DQ_IOMODE_NAMEDPRM)

◆ DQ_IOM_ACCESS_NAMES

#define DQ_IOM_ACCESS_NAMES (DQ_IOMODE_NAMES)

◆ DQ_IOM_ACCESS_OPERS

#define DQ_IOM_ACCESS_OPERS (DQ_IOMODE_OPS)

◆ DQ_IOM_ACCESS_SHUTDOWN

#define DQ_IOM_ACCESS_SHUTDOWN (DQ_IOMODE_SD)

◆ DQ_IOMODE_CFG

#define DQ_IOMODE_CFG (2L)

◆ DQ_IOMODE_EECMNDEVS

#define DQ_IOMODE_EECMNDEVS (0xC)

◆ DQ_IOMODE_EEFLAGS

#define DQ_IOMODE_EEFLAGS (0xD)

◆ DQ_IOMODE_GETPRM

#define DQ_IOMODE_GETPRM (0x40)

◆ DQ_IOMODE_INIT

#define DQ_IOMODE_INIT (1L)

◆ DQ_IOMODE_MASK

#define DQ_IOMODE_MASK (0x3fff)

◆ DQ_IOMODE_MODEMASK

#define DQ_IOMODE_MODEMASK (0x3f)

◆ DQ_IOMODE_NAMEDPRM

#define DQ_IOMODE_NAMEDPRM (0x20)

◆ DQ_IOMODE_NAMES

#define DQ_IOMODE_NAMES (0xB)

◆ DQ_IOMODE_OPS

#define DQ_IOMODE_OPS (4L)

◆ DQ_IOMODE_PWRDN

#define DQ_IOMODE_PWRDN (0x9)

◆ DQ_IOMODE_PWRUP

#define DQ_IOMODE_PWRUP (0xA)

◆ DQ_IOMODE_SD

#define DQ_IOMODE_SD (8L)

◆ DQ_IOMODE_SLEEP

#define DQ_IOMODE_SLEEP (0x3)

◆ DQ_IOMODE_STORE

#define DQ_IOMODE_STORE (0x80)

◆ DQ_IOPRM_ADDLDELAY

#define DQ_IOPRM_ADDLDELAY (0x400)

◆ DQ_IOPRM_CFG

#define DQ_IOPRM_CFG (0x2)

◆ DQ_IOPRM_CLPERINT

#define DQ_IOPRM_CLPERINT (0x200)

◆ DQ_IOPRM_EECMNDEVS

#define DQ_IOPRM_EECMNDEVS (0x800)

◆ DQ_IOPRM_EEFLAGS

#define DQ_IOPRM_EEFLAGS (0x2000)

◆ DQ_IOPRM_INIT

#define DQ_IOPRM_INIT (0x1)

◆ DQ_IOPRM_NAMES

#define DQ_IOPRM_NAMES (0x80)

◆ DQ_IOPRM_NBUFS

#define DQ_IOPRM_NBUFS (0x100)

◆ DQ_IOPRM_OPS

#define DQ_IOPRM_OPS (0x4)

◆ DQ_IOPRM_PWRDN

#define DQ_IOPRM_PWRDN (0x20)

◆ DQ_IOPRM_PWRUP

#define DQ_IOPRM_PWRUP (0x40)

◆ DQ_IOPRM_RESERVED0

#define DQ_IOPRM_RESERVED0 (0x300)

◆ DQ_IOPRM_RQID

#define DQ_IOPRM_RQID (0x1000)

◆ DQ_IOPRM_SD

#define DQ_IOPRM_SD (0x8)

◆ DQ_IOPRM_SLEEP

#define DQ_IOPRM_SLEEP (0x10)

◆ DQ_IR601_CPT

#define DQ_IR601_CPT (1L<<31)

◆ DQ_IR601_CR0GE

#define DQ_IR601_CR0GE (1L<<29)

◆ DQ_IR601_CR0L

#define DQ_IR601_CR0L (1L<<30)

◆ DQ_IR601_CR1

#define DQ_IR601_CR1 (1L<<28)

◆ DQ_IR601_CRH

#define DQ_IR601_CRH (1L<<23)

◆ DQ_IR601_CRL

#define DQ_IR601_CRL (1L<<22)

◆ DQ_IR601_HLG

#define DQ_IR601_HLG (1L<<24)

◆ DQ_IR601_HLI

#define DQ_IR601_HLI (1L<<25)

◆ DQ_IR601_IFE

#define DQ_IR601_IFE (1L<<21)

◆ DQ_IR601_IFF

#define DQ_IR601_IFF (1L<<19)

◆ DQ_IR601_IFH

#define DQ_IR601_IFH (1L<<20)

◆ DQ_IR601_LHG

#define DQ_IR601_LHG (1L<<26)

◆ DQ_IR601_LHI

#define DQ_IR601_LHI (1L<<27)

◆ DQ_IR601_OFE

#define DQ_IR601_OFE (1L<<18)

◆ DQ_IR601_OFF

#define DQ_IR601_OFF (1L<<16)

◆ DQ_IR601_OFH

#define DQ_IR601_OFH (1L<<17)

◆ DQ_IR_CPT

#define DQ_IR_CPT 31

◆ DQ_IR_CR0GE

#define DQ_IR_CR0GE 29

◆ DQ_IR_CR0L

#define DQ_IR_CR0L 30

◆ DQ_IR_CR1

#define DQ_IR_CR1 28

◆ DQ_IR_CRH

#define DQ_IR_CRH 23

◆ DQ_IR_CRL

#define DQ_IR_CRL 22

◆ DQ_IR_HLG

#define DQ_IR_HLG 24

◆ DQ_IR_HLI

#define DQ_IR_HLI 25

◆ DQ_IR_IFE

#define DQ_IR_IFE 21

◆ DQ_IR_IFF

#define DQ_IR_IFF 19

◆ DQ_IR_IFH

#define DQ_IR_IFH 20

◆ DQ_IR_LHG

#define DQ_IR_LHG 26

◆ DQ_IR_LHI

#define DQ_IR_LHI 27

◆ DQ_IR_OFE

#define DQ_IR_OFE 18

◆ DQ_IR_OFF

#define DQ_IR_OFF 16

◆ DQ_IR_OFH

#define DQ_IR_OFH 17

◆ DQ_L2_ADC_I_IN

#define DQ_L2_ADC_I_IN (10)

◆ DQ_L2_ADC_TEMP1

#define DQ_L2_ADC_TEMP1 (11)

◆ DQ_L2_ADC_TEMP2

#define DQ_L2_ADC_TEMP2 (12)

◆ DQ_L2_ADC_V_1_2

#define DQ_L2_ADC_V_1_2 (8)

◆ DQ_L2_ADC_V_1_5

#define DQ_L2_ADC_V_1_5 (7)

◆ DQ_L2_ADC_V_24DNR

#define DQ_L2_ADC_V_24DNR (4)

◆ DQ_L2_ADC_V_24NIC

#define DQ_L2_ADC_V_24NIC (5)

◆ DQ_L2_ADC_V_2_5DNR

#define DQ_L2_ADC_V_2_5DNR (0)

◆ DQ_L2_ADC_V_2_5NIC

#define DQ_L2_ADC_V_2_5NIC (1)

◆ DQ_L2_ADC_V_3_3DNR

#define DQ_L2_ADC_V_3_3DNR (2)

◆ DQ_L2_ADC_V_3_3NIC

#define DQ_L2_ADC_V_3_3NIC (3)

◆ DQ_L2_ADC_V_FAN

#define DQ_L2_ADC_V_FAN (9)

◆ DQ_L2_ADC_V_IN

#define DQ_L2_ADC_V_IN (6)

◆ DQ_L2_BASE

#define DQ_L2_BASE (BUS_FREQUENCY)

◆ DQ_L2_BLIM_I_IN

#define DQ_L2_BLIM_I_IN ( N ) ((N>0.01)&&(N<5.0))

◆ DQ_L2_BLIM_V_1_2

#define DQ_L2_BLIM_V_1_2 ( N ) ((N>(1.271*LM10p))&&(N<(1.271*LP10p)))

◆ DQ_L2_BLIM_V_1_5

#define DQ_L2_BLIM_V_1_5 ( N ) ((N>(1.576*LM10p))&&(N<(1.576*LP10p)))

◆ DQ_L2_BLIM_V_24DNR

#define DQ_L2_BLIM_V_24DNR ( N ) ((N>21.6)&&(N<27.0))

◆ DQ_L2_BLIM_V_24NIC

#define DQ_L2_BLIM_V_24NIC ( N ) ((N>21.6)&&(N<27.0))

◆ DQ_L2_BLIM_V_2_5DNR

#define DQ_L2_BLIM_V_2_5DNR ( N ) ((N>(2.5*LM10p))&&(N<(2.5*LP10p)))

◆ DQ_L2_BLIM_V_2_5NIC

#define DQ_L2_BLIM_V_2_5NIC ( N ) ((N>(2.5*LM10p))&&(N<(2.5*LP10p)))

◆ DQ_L2_BLIM_V_3_3DNR

#define DQ_L2_BLIM_V_3_3DNR ( N ) ((N>(3.3*LP10p))&&(N<(3.3*LP10p)))

◆ DQ_L2_BLIM_V_3_3NIC

#define DQ_L2_BLIM_V_3_3NIC ( N ) ((N>(3.3*LP10p))&&(N<(3.3*LP10p)))

◆ DQ_L2_BLIM_V_IN

#define DQ_L2_BLIM_V_IN ( N ) ((N>9)&&(N<36))

◆ DQ_L2_CFG_24BIT

#define DQ_L2_CFG_24BIT (1L<<30)

◆ DQ_L2_CFG_ADCDIV

#define DQ_L2_CFG_ADCDIV (1L<<20)

◆ DQ_L2_CFG_ADCFE

#define DQ_L2_CFG_ADCFE (1L<<29)

◆ DQ_L2_CFG_MASK

#define DQ_L2_CFG_MASK (DQ_L2_STS_DC24OFF|DQ_L2_STS_FANOFF)

◆ DQ_L2_CFG_UONLY

#define DQ_L2_CFG_UONLY (1L<<31)

◆ DQ_L2_CHAN

#define DQ_L2_CHAN (16)

◆ DQ_L2_CHAN_MAX

#define DQ_L2_CHAN_MAX (64)

◆ DQ_L2_CHAN_MESR

#define DQ_L2_CHAN_MESR (13)

◆ DQ_L2_CVT_I_IN

#define DQ_L2_CVT_I_IN ( N ) (((N-0x800000)*0.000000149)*12)

◆ DQ_L2_CVT_TEMP1

#define DQ_L2_CVT_TEMP1 ( N ) (((N-0x800000)*0.000000149)*339)

◆ DQ_L2_CVT_TEMP2

#define DQ_L2_CVT_TEMP2 ( N ) (((N-0x800000)*0.000000149)*339)

◆ DQ_L2_CVT_V_1_2

#define DQ_L2_CVT_V_1_2 ( N ) (((N-0x800000)*0.000000149)*23.1)

◆ DQ_L2_CVT_V_1_5

#define DQ_L2_CVT_V_1_5 ( N ) (((N-0x800000)*0.000000149)*23.1)

◆ DQ_L2_CVT_V_24DNR

#define DQ_L2_CVT_V_24DNR ( N ) (((N-0x800000)*0.000000149)*23.1)

◆ DQ_L2_CVT_V_24NIC

#define DQ_L2_CVT_V_24NIC ( N ) (((N-0x800000)*0.000000149)*23.1)

◆ DQ_L2_CVT_V_2_5DNR

#define DQ_L2_CVT_V_2_5DNR ( N ) (((N-0x800000)*0.000000149)*23.1)

◆ DQ_L2_CVT_V_2_5NIC

#define DQ_L2_CVT_V_2_5NIC ( N ) (((N-0x800000)*0.000000149)*23.1)

◆ DQ_L2_CVT_V_3_3DNR

#define DQ_L2_CVT_V_3_3DNR ( N ) (((N-0x800000)*0.000000149)*23.1)

◆ DQ_L2_CVT_V_3_3NIC

#define DQ_L2_CVT_V_3_3NIC ( N ) (((N-0x800000)*0.000000149)*23.1)

◆ DQ_L2_CVT_V_FAN

#define DQ_L2_CVT_V_FAN ( N ) (((N-0x800000)*0.000000149)*23.1)

◆ DQ_L2_CVT_V_IN

#define DQ_L2_CVT_V_IN ( N ) (((N-0x800000)*0.000000149)*45.3)

◆ DQ_L2_DNRP_CHECK_us

#define DQ_L2_DNRP_CHECK_us (100*1000)

◆ DQ_L2_DNRP_FAN_CH

#define DQ_L2_DNRP_FAN_CH (0x31)

◆ DQ_L2_DNRP_FAN_MNGD

#define DQ_L2_DNRP_FAN_MNGD (0x33)

◆ DQ_L2_DNRP_LED_CH

#define DQ_L2_DNRP_LED_CH (0x30)

◆ DQ_L2_DNRP_LED_MNGD

#define DQ_L2_DNRP_LED_MNGD (0x32)

◆ DQ_L2_DNRP_OL_CH

#define DQ_L2_DNRP_OL_CH (0x10)

◆ DQ_L2_DNRP_UL_CH

#define DQ_L2_DNRP_UL_CH (0x20)

◆ DQ_L2_EST_CURSTS0

#define DQ_L2_EST_CURSTS0 (1L<<0)

◆ DQ_L2_EST_ESTS0

#define DQ_L2_EST_ESTS0 (1L<<16)

◆ DQ_L2_INFOSZ

#define DQ_L2_INFOSZ (DQ_MAX_INFO_SIZE)

◆ DQ_L2_LED_1_5

#define DQ_L2_LED_1_5 (1L<<2)

◆ DQ_L2_LED_24_DNR

#define DQ_L2_LED_24_DNR (1L<<8)

◆ DQ_L2_LED_24_NIC

#define DQ_L2_LED_24_NIC (1L<<9)

◆ DQ_L2_LED_3_3_DNR

#define DQ_L2_LED_3_3_DNR (1L<<10)

◆ DQ_L2_LED_3_3_NIC

#define DQ_L2_LED_3_3_NIC (1L<<11)

◆ DQ_L2_LED_ATT

#define DQ_L2_LED_ATT (1L<<7)

◆ DQ_L2_LED_BLINK

#define DQ_L2_LED_BLINK ( N ) ((N<<16)|N)

◆ DQ_L2_LED_BLINK0

#define DQ_L2_LED_BLINK0 (1L<<16)

◆ DQ_L2_LED_FAN

#define DQ_L2_LED_FAN (1L<<3)

◆ DQ_L2_LED_IIN

#define DQ_L2_LED_IIN (1L<<1)

◆ DQ_L2_LED_IO

#define DQ_L2_LED_IO (1L<<5)

◆ DQ_L2_LED_LEDON0

#define DQ_L2_LED_LEDON0 (1L<<0)

◆ DQ_L2_LED_MASK

#define DQ_L2_LED_MASK (DQ_L2_LED_USR_|(DQ_L2_LED_USR_<<16))

◆ DQ_L2_LED_OVRT

#define DQ_L2_LED_OVRT (1L<<6)

◆ DQ_L2_LED_STOP_UPDATE

#define DQ_L2_LED_STOP_UPDATE (1L<<31)

◆ DQ_L2_LED_USR

#define DQ_L2_LED_USR (1L<<4)

◆ DQ_L2_LED_USR_

#define DQ_L2_LED_USR_ (DQ_L2_LED_USR|DQ_L2_LED_IO|DQ_L2_LED_ATT)

◆ DQ_L2_LED_VIN

#define DQ_L2_LED_VIN (1L<<0)

◆ DQ_L2_LIM_I_IN

#define DQ_L2_LIM_I_IN ( N ) ((N>0.1)&&(N<3.0))

◆ DQ_L2_LIM_TEMP1

#define DQ_L2_LIM_TEMP1 ( N ) ((N>(273-40))&&(N<(273+90)))

◆ DQ_L2_LIM_TEMP2

#define DQ_L2_LIM_TEMP2 ( N ) ((N>(273-40))&&(N<(273+90)))

◆ DQ_L2_LIM_V_1_2

#define DQ_L2_LIM_V_1_2 ( N ) ((N>(1.271*LM6p))&&(N<(1.271*LP6p)))

◆ DQ_L2_LIM_V_1_5

#define DQ_L2_LIM_V_1_5 ( N ) ((N>(1.576*LM6p))&&(N<(1.576*LP6p)))

◆ DQ_L2_LIM_V_24DNR

#define DQ_L2_LIM_V_24DNR ( N ) ((N>22.5)&&(N<26.0))

◆ DQ_L2_LIM_V_24NIC

#define DQ_L2_LIM_V_24NIC ( N ) ((N>22.5)&&(N<26.0))

◆ DQ_L2_LIM_V_2_5DNR

#define DQ_L2_LIM_V_2_5DNR ( N ) ((N>(2.5*LM6p))&&(N<(2.5*LP6p)))

◆ DQ_L2_LIM_V_2_5NIC

#define DQ_L2_LIM_V_2_5NIC ( N ) ((N>(2.5*LM6p))&&(N<(2.5*LP6p)))

◆ DQ_L2_LIM_V_3_3DNR

#define DQ_L2_LIM_V_3_3DNR ( N ) ((N>(3.3*LM6p))&&(N<(3.3*LP6p)))

◆ DQ_L2_LIM_V_3_3NIC

#define DQ_L2_LIM_V_3_3NIC ( N ) ((N>(3.3*LM6p))&&(N<(3.3*LP6p)))

◆ DQ_L2_LIM_V_FAN

#define DQ_L2_LIM_V_FAN ( N ) (N>0)

◆ DQ_L2_LIM_V_IN

#define DQ_L2_LIM_V_IN ( N ) ((N>11)&&(N<30))

◆ DQ_L2_MAXCLFRQ

#define DQ_L2_MAXCLFRQ (10)

◆ DQ_L2_MAXCVFRQ

#define DQ_L2_MAXCVFRQ (10)

◆ DQ_L2_NAMELEN

#define DQ_L2_NAMELEN (20)

◆ DQ_L2_NO_IP

#define DQ_L2_NO_IP (1)

◆ DQ_L2_OVERHEAT_IGNORE

#define DQ_L2_OVERHEAT_IGNORE (10)

◆ DQ_L2_PLIM

#define DQ_L2_PLIM	(	V,
		N,
		T
	)	((V>(N-NT))&&(V<(N+NT)))

◆ DQ_L2_PROGRAM_IP

#define DQ_L2_PROGRAM_IP (2)

◆ DQ_L2_SAFE_TEMP_HI

#define DQ_L2_SAFE_TEMP_HI (273+40)

◆ DQ_L2_SAFE_TEMP_LO

#define DQ_L2_SAFE_TEMP_LO (273+35)

◆ DQ_L2_SET_CONFIG

#define DQ_L2_SET_CONFIG (1)

◆ DQ_L2_SET_LED

#define DQ_L2_SET_LED (2)

◆ DQ_L2_SET_LIMITS

#define DQ_L2_SET_LIMITS (4)

◆ DQ_L2_STS_DC24OFF

#define DQ_L2_STS_DC24OFF (1L<<17)

◆ DQ_L2_STS_FAN0STS

#define DQ_L2_STS_FAN0STS (1L<<18)

◆ DQ_L2_STS_FAN1STS

#define DQ_L2_STS_FAN1STS (1L<<19)

◆ DQ_L2_STS_FANOFF

#define DQ_L2_STS_FANOFF (1L<<16)

◆ DQ_L401_BASE

#define DQ_L401_BASE BUS_FREQUENCY

◆ DQ_L401_CHAN

#define DQ_L401_CHAN 24

◆ DQ_L401_HYSTEN

#define DQ_L401_HYSTEN (1UL<<18)

◆ DQ_L401_INFOSZ

#define DQ_L401_INFOSZ DQ_MAX_INFO_SIZE

◆ DQ_L401_MAXCLFRQ

#define DQ_L401_MAXCLFRQ 100000

◆ DQ_L401_MAXCVFRQ

#define DQ_L401_MAXCVFRQ 100000

◆ DQ_L401_MODECONT

#define DQ_L401_MODECONT (DQ_FIFO_MODECONT)

◆ DQ_L401_MODEDGE

#define DQ_L401_MODEDGE (1UL << 16)

◆ DQ_L401_MODEFIFO

#define DQ_L401_MODEFIFO (DQ_FIFO_MODEFIFO)

◆ DQ_L401_MODESCAN

#define DQ_L401_MODESCAN (DQ_FIFO_MODESCAN)

◆ DQ_L401_NAMELEN

#define DQ_L401_NAMELEN 20

◆ DQ_L416_ADCDATA_LSB

#define DQ_L416_ADCDATA_LSB (0)

◆ DQ_L416_ADCDATA_MSB

#define DQ_L416_ADCDATA_MSB (23)

◆ DQ_L416_ADCDATA_OK

#define DQ_L416_ADCDATA_OK (0)

◆ DQ_L416_ADCDATA_OR

#define DQ_L416_ADCDATA_OR (3)

◆ DQ_L416_ADCDATA_STS0

#define DQ_L416_ADCDATA_STS0 (27)

◆ DQ_L416_ADCDATA_STS1

#define DQ_L416_ADCDATA_STS1 (28)

◆ DQ_L416_ADCDATA_UR

#define DQ_L416_ADCDATA_UR (1)

◆ DQ_L416_ADCSPD_0_8

#define DQ_L416_ADCSPD_0_8 (15)

◆ DQ_L416_ADCSPD_12

#define DQ_L416_ADCSPD_12 (6)

◆ DQ_L416_ADCSPD_130

#define DQ_L416_ADCSPD_130 (2)

◆ DQ_L416_ADCSPD_190

#define DQ_L416_ADCSPD_190 (1)

◆ DQ_L416_ADCSPD_1_6

#define DQ_L416_ADCSPD_1_6 (9)

◆ DQ_L416_ADCSPD_22

#define DQ_L416_ADCSPD_22 (5)

◆ DQ_L416_ADCSPD_24BIT

#define DQ_L416_ADCSPD_24BIT (29)

◆ DQ_L416_ADCSPD_3_2

#define DQ_L416_ADCSPD_3_2 (8)

◆ DQ_L416_ADCSPD_45

#define DQ_L416_ADCSPD_45 (4)

◆ DQ_L416_ADCSPD_6_5

#define DQ_L416_ADCSPD_6_5 (7)

◆ DQ_L416_ADCSPD_85

#define DQ_L416_ADCSPD_85 (3)

◆ DQ_L416_ADCSPD_ADCFE

#define DQ_L416_ADCSPD_ADCFE (28)

◆ DQ_L416_ADCSPD_ASL1BIT

#define DQ_L416_ADCSPD_ASL1BIT (19)

◆ DQ_L416_ADCSPD_DIVLSB

#define DQ_L416_ADCSPD_DIVLSB (20)

◆ DQ_L416_ADCSPD_DIVMSB

#define DQ_L416_ADCSPD_DIVMSB (27)

◆ DQ_L416_ADCSPD_LSB

#define DQ_L416_ADCSPD_LSB (0)

◆ DQ_L416_ADCSPD_MSB

#define DQ_L416_ADCSPD_MSB (3)

◆ DQ_L416_ADCSPD_NOBUSY

#define DQ_L416_ADCSPD_NOBUSY (30)

◆ DQ_L416_ADCSPD_UONLY

#define DQ_L416_ADCSPD_UONLY (31)

◆ DQ_L416_ADCSTS_ADC0CH_LSB

#define DQ_L416_ADCSTS_ADC0CH_LSB (12)

◆ DQ_L416_ADCSTS_ADC0CH_MSB

#define DQ_L416_ADCSTS_ADC0CH_MSB (14)

◆ DQ_L416_ADCSTS_ADC0SM_LSB

#define DQ_L416_ADCSTS_ADC0SM_LSB (4)

◆ DQ_L416_ADCSTS_ADC0SM_MSB

#define DQ_L416_ADCSTS_ADC0SM_MSB (6)

◆ DQ_L416_ADCSTS_ADC0TO

#define DQ_L416_ADCSTS_ADC0TO (7)

◆ DQ_L416_ADCSTS_ADC1CH_LSB

#define DQ_L416_ADCSTS_ADC1CH_LSB (16)

◆ DQ_L416_ADCSTS_ADC1CH_MSB

#define DQ_L416_ADCSTS_ADC1CH_MSB (18)

◆ DQ_L416_ADCSTS_ADC1SM_LSB

#define DQ_L416_ADCSTS_ADC1SM_LSB (8)

◆ DQ_L416_ADCSTS_ADC1SM_MSB

#define DQ_L416_ADCSTS_ADC1SM_MSB (10)

◆ DQ_L416_ADCSTS_ADC1TO

#define DQ_L416_ADCSTS_ADC1TO (11)

◆ DQ_L416_MAXCURRENT

#define DQ_L416_MAXCURRENT (2.0)

◆ DQ_L416_MAXRAW

#define DQ_L416_MAXRAW (0x00FFFFFF)

◆ DQ_L416_MINCURRENT

#define DQ_L416_MINCURRENT (-2.0)

◆ DQ_L416_MINRAW

#define DQ_L416_MINRAW (0x00000000)

◆ DQ_L416_MODECONT

#define DQ_L416_MODECONT (DQ_FIFO_MODECONT)

◆ DQ_L416_MODEFIFO

#define DQ_L416_MODEFIFO (DQ_FIFO_MODEFIFO)

◆ DQ_L416_MODESCAN

#define DQ_L416_MODESCAN (DQ_FIFO_MODESCAN)

◆ DQ_L416_NAMELEN

#define DQ_L416_NAMELEN 20

◆ DQ_L432_MAXCURRENT

#define DQ_L432_MAXCURRENT (2.0)

◆ DQ_L432_MAXRAW_16BIT

#define DQ_L432_MAXRAW_16BIT (0x0000FFFF)

◆ DQ_L432_MAXRAW_24BIT

#define DQ_L432_MAXRAW_24BIT (0x00FFFFFF)

◆ DQ_L432_MAXVOLTAGE

#define DQ_L432_MAXVOLTAGE (63.75)

◆ DQ_L432_MINCURRENT

#define DQ_L432_MINCURRENT (-2.0)

◆ DQ_L432_MINRAW

#define DQ_L432_MINRAW (0x00000000)

◆ DQ_L432_MINVOLTAGE

#define DQ_L432_MINVOLTAGE (-63.75)

◆ DQ_L432_NAMELEN

#define DQ_L432_NAMELEN 10

◆ DQ_L462_MAX_ACCURRENT

#define DQ_L462_MAX_ACCURRENT (3.0)

◆ DQ_L462_MAX_N_DCCURRENT

#define DQ_L462_MAX_N_DCCURRENT (-3.0)

◆ DQ_L462_MAX_N_DCSPAN

#define DQ_L462_MAX_N_DCSPAN (-DQ_DIO462_V_SPAN/2.0)

◆ DQ_L462_MAX_N_DCVOLT

#define DQ_L462_MAX_N_DCVOLT (-30.0)

◆ DQ_L462_MAX_P_DCCURRENT

#define DQ_L462_MAX_P_DCCURRENT (3.0)

◆ DQ_L462_MAX_P_DCVOLT

#define DQ_L462_MAX_P_DCVOLT (151.5)

◆ DQ_L462_MAXCURRENT

#define DQ_L462_MAXCURRENT (3.0)

◆ DQ_L462_MAXRAW

#define DQ_L462_MAXRAW (0x0FFFF)

◆ DQ_L462_MINCURRENT

#define DQ_L462_MINCURRENT (-3.0)

◆ DQ_L462_MINRAW

#define DQ_L462_MINRAW (0x0)

◆ DQ_L462_NAMELEN

#define DQ_L462_NAMELEN (20)

◆ DQ_L4_ADC_GND

#define DQ_L4_ADC_GND (1)

◆ DQ_L4_ADC_GND_2

#define DQ_L4_ADC_GND_2 (5)

◆ DQ_L4_ADC_GND_3

#define DQ_L4_ADC_GND_3 (11)

◆ DQ_L4_ADC_I_1_5

#define DQ_L4_ADC_I_1_5 (14)

◆ DQ_L4_ADC_I_3_3

#define DQ_L4_ADC_I_3_3 (12)

◆ DQ_L4_ADC_I_IN

#define DQ_L4_ADC_I_IN (10)

◆ DQ_L4_ADC_TEMP1

#define DQ_L4_ADC_TEMP1 (13)

◆ DQ_L4_ADC_TEMP2

#define DQ_L4_ADC_TEMP2 (15)

◆ DQ_L4_ADC_V_1_2

#define DQ_L4_ADC_V_1_2 (8)

◆ DQ_L4_ADC_V_1_5

#define DQ_L4_ADC_V_1_5 (7)

◆ DQ_L4_ADC_V_24DNR

#define DQ_L4_ADC_V_24DNR (4)

◆ DQ_L4_ADC_V_2_5DNR

#define DQ_L4_ADC_V_2_5DNR (0)

◆ DQ_L4_ADC_V_3_3DNR

#define DQ_L4_ADC_V_3_3DNR (2)

◆ DQ_L4_ADC_V_CAP

#define DQ_L4_ADC_V_CAP (3)

◆ DQ_L4_ADC_V_FAN

#define DQ_L4_ADC_V_FAN (9)

◆ DQ_L4_ADC_V_IN

#define DQ_L4_ADC_V_IN (6)

◆ DQ_L4_BLIM_I_IN

#define DQ_L4_BLIM_I_IN ( N ) ((N>0.01)&&(N<5.0))

◆ DQ_L4_BLIM_I_IN_1_5

#define DQ_L4_BLIM_I_IN_1_5 ( N ) ((N>0.1)&&(N<3.0))

◆ DQ_L4_BLIM_I_IN_3_3

#define DQ_L4_BLIM_I_IN_3_3 ( N ) ((N>0.1)&&(N<3.0))

◆ DQ_L4_BLIM_V_1_2A

#define DQ_L4_BLIM_V_1_2A ( N ) ((N>(1.21*LM10p))&&(N<(1.21*LP10p)))

◆ DQ_L4_BLIM_V_1_2R

#define DQ_L4_BLIM_V_1_2R ( N ) ((N>(1.271*LM10p))&&(N<(1.271*LP10p)))

◆ DQ_L4_BLIM_V_1_5

#define DQ_L4_BLIM_V_1_5 ( N ) ((N>(1.576*LM10p))&&(N<(1.576*LP10p)))

◆ DQ_L4_BLIM_V_24DNR

#define DQ_L4_BLIM_V_24DNR ( N ) ((N>21.6)&&(N<27.0))

◆ DQ_L4_BLIM_V_24NIC

#define DQ_L4_BLIM_V_24NIC ( N ) ((N>21.6)&&(N<27.0))

◆ DQ_L4_BLIM_V_2_5DNR

#define DQ_L4_BLIM_V_2_5DNR ( N ) ((N>(2.5*LM10p))&&(N<(2.5*LP10p)))

◆ DQ_L4_BLIM_V_2_5NIC

#define DQ_L4_BLIM_V_2_5NIC ( N ) ((N>(2.5*LM10p))&&(N<(2.5*LP10p)))

◆ DQ_L4_BLIM_V_3_3DNR

#define DQ_L4_BLIM_V_3_3DNR ( N ) ((N>(3.3*LP10p))&&(N<(3.3*LP10p)))

◆ DQ_L4_BLIM_V_3_3NIC

#define DQ_L4_BLIM_V_3_3NIC ( N ) ((N>(3.3*LP10p))&&(N<(3.3*LP10p)))

◆ DQ_L4_BLIM_V_IN

#define DQ_L4_BLIM_V_IN ( N ) ((N>9)&&(N<36))

◆ DQ_L4_CVT_I_IN

#define DQ_L4_CVT_I_IN ( N ) (((N-0x800000)*0.00000178))

◆ DQ_L4_CVT_I_IN_1_5

#define DQ_L4_CVT_I_IN_1_5 ( N ) (((N-0x800000)*0.00000745))

◆ DQ_L4_CVT_I_IN_3_3

#define DQ_L4_CVT_I_IN_3_3 ( N ) (((N-0x800000)*0.00000745))

◆ DQ_L4_CVT_TEMP1

#define DQ_L4_CVT_TEMP1 ( N ) ((N-0x800000)/644)

◆ DQ_L4_CVT_TEMP2

#define DQ_L4_CVT_TEMP2 ( N ) ((N-0x800000)/644)

◆ DQ_L4_CVT_V_1_2

#define DQ_L4_CVT_V_1_2 ( N ) (((N-0x800000)*0.000000149)*23.1)

◆ DQ_L4_CVT_V_1_5

#define DQ_L4_CVT_V_1_5 ( N ) (((N-0x800000)*0.000000149)*23.1)

◆ DQ_L4_CVT_V_24DNR

#define DQ_L4_CVT_V_24DNR ( N ) (((N-0x800000)*0.000000149)*23.1)

◆ DQ_L4_CVT_V_2_5DNR

#define DQ_L4_CVT_V_2_5DNR ( N ) (((N-0x800000)*0.000000149)*23.1)

◆ DQ_L4_CVT_V_3_3DNR

#define DQ_L4_CVT_V_3_3DNR ( N ) (((N-0x800000)*0.000000149)*23.1)

◆ DQ_L4_CVT_V_FAN

#define DQ_L4_CVT_V_FAN ( N ) (((N-0x800000)*0.000000149)*23.1)

◆ DQ_L4_CVT_V_GND

#define DQ_L4_CVT_V_GND ( N ) (((N-0x800000)*0.000000149))

◆ DQ_L4_CVT_V_GND2

#define DQ_L4_CVT_V_GND2 ( N ) (((N-0x800000)*0.000000149))

◆ DQ_L4_CVT_V_GND3

#define DQ_L4_CVT_V_GND3 ( N ) (((N-0x800000)*0.000000149))

◆ DQ_L4_CVT_V_IN

#define DQ_L4_CVT_V_IN ( N ) (((N-0x800000)*0.000000149)*47.5)

◆ DQ_L4_CVT_V_U_CAP

#define DQ_L4_CVT_V_U_CAP ( N ) (((N-0x800000)*0.000000149)*23.1)

◆ DQ_L4_LED_24_DNR

#define DQ_L4_LED_24_DNR (1L<<7)

◆ DQ_L4_LED_3_3_DNR

#define DQ_L4_LED_3_3_DNR (1L<<5)

◆ DQ_L4_LED_ATT

#define DQ_L4_LED_ATT (1L<<1)

◆ DQ_L4_LED_BLINK

#define DQ_L4_LED_BLINK ( N ) ((N<<16)|N)

◆ DQ_L4_LED_IO

#define DQ_L4_LED_IO (1L<<4)

◆ DQ_L4_LED_MASK

#define DQ_L4_LED_MASK (DQ_L4_LED_USR_|(DQ_L4_LED_USR_<<16))

◆ DQ_L4_LED_OVRT

#define DQ_L4_LED_OVRT (1L<<0)

◆ DQ_L4_LED_PG

#define DQ_L4_LED_PG (1L<<6)

◆ DQ_L4_LED_RW

#define DQ_L4_LED_RW (1L<<2)

◆ DQ_L4_LED_USR

#define DQ_L4_LED_USR (1L<<3)

◆ DQ_L4_LED_USR_

#define DQ_L4_LED_USR_ (DQ_L4_LED_USR|DQ_L4_LED_IO|DQ_L4_LED_ATT)

◆ DQ_L4_LIM_I_IN

#define DQ_L4_LIM_I_IN ( N ) ((N>0.1)&&(N<4.0))

◆ DQ_L4_LIM_I_IN_1_5

#define DQ_L4_LIM_I_IN_1_5 ( N ) ((N>0.1)&&(N<3.0))

◆ DQ_L4_LIM_I_IN_3_3

#define DQ_L4_LIM_I_IN_3_3 ( N ) ((N>0.1)&&(N<3.0))

◆ DQ_L4_LIM_TEMP1

#define DQ_L4_LIM_TEMP1 ( N ) ((N>(273-40))&&(N<(273+90)))

◆ DQ_L4_LIM_TEMP2

#define DQ_L4_LIM_TEMP2 ( N ) ((N>(273-40))&&(N<(273+90)))

◆ DQ_L4_LIM_V_1_2A

#define DQ_L4_LIM_V_1_2A ( N ) ((N>(1.21*LM6p))&&(N<(1.21*LP6p)))

◆ DQ_L4_LIM_V_1_2R

#define DQ_L4_LIM_V_1_2R ( N ) ((N>(1.271*LM6p))&&(N<(1.271*LP6p)))

◆ DQ_L4_LIM_V_1_5

#define DQ_L4_LIM_V_1_5 ( N ) ((N>(1.576*LM6p))&&(N<(1.576*LP6p)))

◆ DQ_L4_LIM_V_24DNR

#define DQ_L4_LIM_V_24DNR ( N ) ((N>22.5)&&(N<26.0))

◆ DQ_L4_LIM_V_24NIC

#define DQ_L4_LIM_V_24NIC ( N ) ((N>22.5)&&(N<26.0))

◆ DQ_L4_LIM_V_2_5DNR

#define DQ_L4_LIM_V_2_5DNR ( N ) ((N>(2.5*LM6p))&&(N<(2.5*LP6p)))

◆ DQ_L4_LIM_V_2_5NIC

#define DQ_L4_LIM_V_2_5NIC ( N ) ((N>(2.5*LM6p))&&(N<(2.5*LP6p)))

◆ DQ_L4_LIM_V_3_3DNR

#define DQ_L4_LIM_V_3_3DNR ( N ) ((N>(3.3*LM6p))&&(N<(3.3*LP6p)))

◆ DQ_L4_LIM_V_3_3NIC

#define DQ_L4_LIM_V_3_3NIC ( N ) ((N>(3.3*LM6p))&&(N<(3.3*LP6p)))

◆ DQ_L4_LIM_V_FAN

#define DQ_L4_LIM_V_FAN ( N ) (N)

◆ DQ_L4_LIM_V_IN

#define DQ_L4_LIM_V_IN ( N ) ((N>11)&&(N<30))

◆ DQ_L4_SAFE_TEMP_HI

#define DQ_L4_SAFE_TEMP_HI (273+40)

◆ DQ_L4_SAFE_TEMP_LO

#define DQ_L4_SAFE_TEMP_LO (273+35)

◆ DQ_L4_SET_CONFIG

#define DQ_L4_SET_CONFIG (DQ_L2_SET_CONFIG)

◆ DQ_L4_SET_LED

#define DQ_L4_SET_LED (DQ_L2_SET_LED)

◆ DQ_L4_SET_LIMITS

#define DQ_L4_SET_LIMITS (DQ_L2_SET_LIMITS)

◆ DQ_L500_BAUD_110

#define DQ_L500_BAUD_110 (0UL << 28)

◆ DQ_L500_BAUD_115200

#define DQ_L500_BAUD_115200 (12UL << 28)

◆ DQ_L500_BAUD_1200

#define DQ_L500_BAUD_1200 (3UL << 28)

◆ DQ_L500_BAUD_14400

#define DQ_L500_BAUD_14400 (7UL << 28)

◆ DQ_L500_BAUD_19200

#define DQ_L500_BAUD_19200 (8UL << 28)

◆ DQ_L500_BAUD_2400

#define DQ_L500_BAUD_2400 (4UL << 28)

◆ DQ_L500_BAUD_28800

#define DQ_L500_BAUD_28800 (9UL << 28)

◆ DQ_L500_BAUD_300

#define DQ_L500_BAUD_300 (1UL << 28)

◆ DQ_L500_BAUD_38400

#define DQ_L500_BAUD_38400 (10UL << 28)

◆ DQ_L500_BAUD_4800

#define DQ_L500_BAUD_4800 (5UL << 28)

◆ DQ_L500_BAUD_57600

#define DQ_L500_BAUD_57600 (11UL << 28)

◆ DQ_L500_BAUD_600

#define DQ_L500_BAUD_600 (2UL << 28)

◆ DQ_L500_BAUD_9600

#define DQ_L500_BAUD_9600 (6UL << 28)

◆ DQ_L500_PARITY_EVEN

#define DQ_L500_PARITY_EVEN (0UL << 24)

◆ DQ_L500_PARITY_NONE

#define DQ_L500_PARITY_NONE (2UL << 24)

◆ DQ_L500_PARITY_ODD

#define DQ_L500_PARITY_ODD (1UL << 24)

◆ DQ_L500_STOP_1

#define DQ_L500_STOP_1 (0UL << 22)

◆ DQ_L500_STOP_1_5

#define DQ_L500_STOP_1_5 (1UL << 22)

◆ DQ_L500_STOP_2

#define DQ_L500_STOP_2 (2UL << 22)

◆ DQ_L500_WIDTH_5

#define DQ_L500_WIDTH_5 (0UL << 26)

◆ DQ_L500_WIDTH_6

#define DQ_L500_WIDTH_6 (1UL << 26)

◆ DQ_L500_WIDTH_7

#define DQ_L500_WIDTH_7 (2UL << 26)

◆ DQ_L500_WIDTH_8

#define DQ_L500_WIDTH_8 (3UL << 26)

◆ DQ_L501_BASE_24

#define DQ_L501_BASE_24 (24000000)

◆ DQ_L501_BASE_29

#define DQ_L501_BASE_29 (29454545)

◆ DQ_L501_BASE_66

#define DQ_L501_BASE_66 (66000000)

◆ DQ_L501_BASE_CUSTOM

#define DQ_L501_BASE_CUSTOM (0)

◆ DQ_L501_CHAN

#define DQ_L501_CHAN (4)

◆ DQ_L501_FIFO_GET_DATA

#define DQ_L501_FIFO_GET_DATA (DQ_FIFO_GET_DATA)

◆ DQ_L501_FIFO_SET_DATA

#define DQ_L501_FIFO_SET_DATA (DQ_FIFO_SET_DATA)

◆ DQ_L501_FIFOSZ

#define DQ_L501_FIFOSZ (2048)

◆ DQ_L501_ID_EXTENDED

#define DQ_L501_ID_EXTENDED (0x1L<<18)

◆ DQ_L501_ID_STANDARD

#define DQ_L501_ID_STANDARD (0x0L<<18)

◆ DQ_L501_INFOSZ

#define DQ_L501_INFOSZ (DQ_MAX_INFO_SIZE)

◆ DQ_L501_MAXCLFRQ

#define DQ_L501_MAXCLFRQ (2000)

◆ DQ_L501_MAXCVFRQ

#define DQ_L501_MAXCVFRQ (2000)

◆ DQ_L501_MFIFO_1

#define DQ_L501_MFIFO_1 (1000000)

◆ DQ_L501_MODECONT

#define DQ_L501_MODECONT (DQ_FIFO_MODECONT)

◆ DQ_L501_MODEFIFO

#define DQ_L501_MODEFIFO (DQ_FIFO_MODEFIFO)

◆ DQ_L501_MODESCAN

#define DQ_L501_MODESCAN (DQ_FIFO_MODESCAN)

◆ DQ_L501_NAMELEN

#define DQ_L501_NAMELEN (32)

◆ DQ_L501_REPEAT_SUPPORTED

#define DQ_L501_REPEAT_SUPPORTED (0xf)

◆ DQ_L503_BASE

#define DQ_L503_BASE (BUS_FREQUENCY)

◆ DQ_L503_CHAN

#define DQ_L503_CHAN (4)

◆ DQ_L503_FIFO_GET_DATA

#define DQ_L503_FIFO_GET_DATA (DQ_FIFO_GET_DATA)

◆ DQ_L503_FIFO_RQ

#define DQ_L503_FIFO_RQ (10000)

◆ DQ_L503_FIFO_SET_DATA

#define DQ_L503_FIFO_SET_DATA (DQ_FIFO_SET_DATA)

◆ DQ_L503_INFOSZ

#define DQ_L503_INFOSZ (DQ_MAX_INFO_SIZE)

◆ DQ_L503_MAX_PACKET_BITS

#define DQ_L503_MAX_PACKET_BITS (120)

◆ DQ_L503_MAXCLFRQ

#define DQ_L503_MAXCLFRQ (2000)

◆ DQ_L503_MAXCVFRQ

#define DQ_L503_MAXCVFRQ (2000)

◆ DQ_L503_MODECONT

#define DQ_L503_MODECONT (DQ_FIFO_MODECONT)

◆ DQ_L503_MODEFIFO

#define DQ_L503_MODEFIFO (DQ_FIFO_MODEFIFO)

◆ DQ_L503_MODESCAN

#define DQ_L503_MODESCAN (DQ_FIFO_MODESCAN)

◆ DQ_L503_NAMELEN

#define DQ_L503_NAMELEN (32)

◆ DQ_L503_RX_FIFO_ONEMSG

#define DQ_L503_RX_FIFO_ONEMSG (4)

◆ DQ_L503_RX_FIFOSZ

#define DQ_L503_RX_FIFOSZ (1024)

◆ DQ_L503_SEC_FIFO_SUPPORTED

#define DQ_L503_SEC_FIFO_SUPPORTED (0xf)

◆ DQ_L503_TO_RQ

#define DQ_L503_TO_RQ (10)

◆ DQ_L503_TX_FIFOSZ

#define DQ_L503_TX_FIFOSZ (512)

◆ DQ_L504_BASE_66

#define DQ_L504_BASE_66 (66000000)

◆ DQ_L504_CHAN

#define DQ_L504_CHAN (4)

◆ DQ_L504_FIFO_GET_DATA

#define DQ_L504_FIFO_GET_DATA (DQ_FIFO_GET_DATA)

◆ DQ_L504_FIFO_SET_DATA

#define DQ_L504_FIFO_SET_DATA (DQ_FIFO_SET_DATA)

◆ DQ_L504_FIFOSZ

#define DQ_L504_FIFOSZ (2048)

◆ DQ_L504_ID_EXTENDED

#define DQ_L504_ID_EXTENDED (0x1L<<18)

◆ DQ_L504_ID_STANDARD

#define DQ_L504_ID_STANDARD (0x0L<<18)

◆ DQ_L504_INFOSZ

#define DQ_L504_INFOSZ (DQ_MAX_INFO_SIZE)

◆ DQ_L504_MAXCLFRQ

#define DQ_L504_MAXCLFRQ (2000)

◆ DQ_L504_MAXCVFRQ

#define DQ_L504_MAXCVFRQ (2000)

◆ DQ_L504_MODECONT

#define DQ_L504_MODECONT (DQ_FIFO_MODECONT)

◆ DQ_L504_MODEFIFO

#define DQ_L504_MODEFIFO (DQ_FIFO_MODEFIFO)

◆ DQ_L504_MODESCAN

#define DQ_L504_MODESCAN (DQ_FIFO_MODESCAN)

◆ DQ_L504_NAMELEN

#define DQ_L504_NAMELEN (32)

◆ DQ_L508_CHAN

#define DQ_L508_CHAN (8)

◆ DQ_L508_FIFOSZ

#define DQ_L508_FIFOSZ (1024)

◆ DQ_L508_MAJORSZ

#define DQ_L508_MAJORSZ (1024)

◆ DQ_L508_NAMELEN

#define DQ_L508_NAMELEN (24)

◆ DQ_L550_BASE

#define DQ_L550_BASE (66000000)

◆ DQ_L550_CHAN

#define DQ_L550_CHAN (1)

◆ DQ_L550_INFOSZ

#define DQ_L550_INFOSZ DQ_MAX_INFO_SIZE

◆ DQ_L550_NAMELEN

#define DQ_L550_NAMELEN (32)

◆ DQ_L553_A708_FIFO

#define DQ_L553_A708_FIFO 2048

◆ DQ_L553_A708_FRMSZ

#define DQ_L553_A708_FRMSZ 100

◆ DQ_L553_A708_RX_BE

#define DQ_L553_A708_RX_BE (1L<<5)

◆ DQ_L553_A708_TSTAMP_SZ

#define DQ_L553_A708_TSTAMP_SZ 2

◆ DQ_L553_A708_TX_BE

#define DQ_L553_A708_TX_BE (1L<<4)

◆ DQ_L553_BASE

#define DQ_L553_BASE 66000000

◆ DQ_L553_BC_BASE

#define DQ_L553_BC_BASE 1000000.0

◆ DQ_L553_BM_LIST_ADD

#define DQ_L553_BM_LIST_ADD (1L<<31)

◆ DQ_L553_BM_LSTN_A

#define DQ_L553_BM_LSTN_A (1L<<0)

◆ DQ_L553_BM_LSTN_B

#define DQ_L553_BM_LSTN_B (1L<<1)

◆ DQ_L553_BM_RT

#define DQ_L553_BM_RT ( N ) (((N)&0x1f)<<6)

◆ DQ_L553_BM_RT_SEL

#define DQ_L553_BM_RT_SEL (1L<<11)

◆ DQ_L553_BM_SADDR

#define DQ_L553_BM_SADDR ( N ) (((N)&0x1f)<<0)

◆ DQ_L553_BM_SADDR_SEL

#define DQ_L553_BM_SADDR_SEL (1L<<5)

◆ DQ_L553_BM_TX_A

#define DQ_L553_BM_TX_A (1L<<2)

◆ DQ_L553_BM_TX_B

#define DQ_L553_BM_TX_B (1L<<3)

◆ DQ_L553_BMSTATUS_OVER

#define DQ_L553_BMSTATUS_OVER (0x80)

◆ DQ_L553_BROADADDR

#define DQ_L553_BROADADDR 0x1f

◆ DQ_L553_CH_CMDMASK

#define DQ_L553_CH_CMDMASK 0xf0

◆ DQ_L553_CH_MASK

#define DQ_L553_CH_MASK 0x0f

◆ DQ_L553_CH_RT_SA

#define DQ_L553_CH_RT_SA	(	CH,
		RT,
		SA
	)	((((CH)&1)<<DQ_L553_RTS_CHAN_NUM_SHR)\|(DQ_L553_BM_RT((RT))\|DQ_L553_BM_RT_SEL)\|(DQ_L553_BM_SADDR((SA))\|DQ_L553_BM_SADDR_SEL))

◆ DQ_L553_CHAN

#define DQ_L553_CHAN 2

◆ DQ_L553_CHAN_RX

#define DQ_L553_CHAN_RX 2

◆ DQ_L553_CHAN_TX

#define DQ_L553_CHAN_TX 2

◆ DQ_L553_CONTROL_CFG

#define DQ_L553_CONTROL_CFG	(	CH,
		RT,
		RQ
	)	((((CH)&1)<<DQ_L553_RTS_CHAN_NUM_SHR)\|DQ_L553_RTS_RT_CTL\|DQ_L553_RTS_RT(RT)\|RQ)

◆ DQ_L553_COUPLE_DIRECTLY

#define DQ_L553_COUPLE_DIRECTLY (3L<<0)

◆ DQ_L553_DATA

#define DQ_L553_DATA	(	CH,
		RT,
		SA,
		BLK
	)	(DQ_L553_RTS_RT(RT)\|DQ_L553_RTS_SADDR(SA)\|DQ_L553_RTS_BLK(BLK)\|(((CH)&1)<<DQ_L553_RTS_CHAN_NUM_SHR))

◆ DQ_L553_DISCONNECT

#define DQ_L553_DISCONNECT (0L<<0)

◆ DQ_L553_DSIZE_MASK

#define DQ_L553_DSIZE_MASK 0x1f

◆ DQ_L553_FIFO_GET_DATA

#define DQ_L553_FIFO_GET_DATA DQ_FIFO_GET_DATA

◆ DQ_L553_FIFO_SET_DATA

#define DQ_L553_FIFO_SET_DATA DQ_FIFO_SET_DATA

◆ DQ_L553_FORCE_A

#define DQ_L553_FORCE_A (1L<<4)

◆ DQ_L553_INFOSZ

#define DQ_L553_INFOSZ DQ_MAX_INFO_SIZE

◆ DQ_L553_INTCLKUS

#define DQ_L553_INTCLKUS 100

◆ DQ_L553_LBLFILTSIZE

#define DQ_L553_LBLFILTSIZE 256

◆ DQ_L553_MAX_MSG

#define DQ_L553_MAX_MSG 64

◆ DQ_L553_MAX_WORDS

#define DQ_L553_MAX_WORDS 32

◆ DQ_L553_MAXBM_WORDS

#define DQ_L553_MAXBM_WORDS (DQ_L553_MAX_WORDS+4)

◆ DQ_L553_MAXCLFRQ

#define DQ_L553_MAXCLFRQ 2000

◆ DQ_L553_MAXCVFRQ

#define DQ_L553_MAXCVFRQ 2000

◆ DQ_L553_MAXDLYCNT

#define DQ_L553_MAXDLYCNT 65535

◆ DQ_L553_MAXRT_WORDS

#define DQ_L553_MAXRT_WORDS (DQ_L553_MAX_WORDS+7)

◆ DQ_L553_MD_FIFOSZ

#define DQ_L553_MD_FIFOSZ 19

◆ DQ_L553_MODE_A708

#define DQ_L553_MODE_A708 (1L<<3)

◆ DQ_L553_MODE_BC

#define DQ_L553_MODE_BC (1L<<2)

◆ DQ_L553_MODE_BM

#define DQ_L553_MODE_BM (1L<<0)

◆ DQ_L553_MODE_RT

#define DQ_L553_MODE_RT (1L<<1)

◆ DQ_L553_MODEADDR

#define DQ_L553_MODEADDR 0

◆ DQ_L553_MODECONT

#define DQ_L553_MODECONT (DQ_FIFO_MODECONT)

◆ DQ_L553_MODEFIFO

#define DQ_L553_MODEFIFO (DQ_FIFO_MODEFIFO)

◆ DQ_L553_MODESCAN

#define DQ_L553_MODESCAN (DQ_FIFO_MODESCAN)

◆ DQ_L553_NAMELEN

#define DQ_L553_NAMELEN 32

◆ DQ_L553_READFIFO

#define DQ_L553_READFIFO 100

◆ DQ_L553_READFIFO_ALL

#define DQ_L553_READFIFO_ALL (0x100)

◆ DQ_L553_READMEM_CYCLES

#define DQ_L553_READMEM_CYCLES 200

◆ DQ_L553_READMEM_nS

#define DQ_L553_READMEM_nS 200

◆ DQ_L553_READMEM_ONE_SA

#define DQ_L553_READMEM_ONE_SA 25

◆ DQ_L553_RT

#define DQ_L553_RT ( RT ) (DQ_L553_BM_RT((RT))|DQ_L553_BM_RT_SEL)

◆ DQ_L553_RT_BERRORS

#define DQ_L553_RT_BERRORS (5L<<12)

◆ DQ_L553_RT_CHSTAT

#define DQ_L553_RT_CHSTAT (4L<<12)

◆ DQ_L553_RT_DATA_RDY

#define DQ_L553_RT_DATA_RDY (6L<<12)

◆ DQ_L553_RT_DATA_SENT

#define DQ_L553_RT_DATA_SENT (7L<<12)

◆ DQ_L553_RT_DEFER_EN

#define DQ_L553_RT_DEFER_EN (1L<<30)

◆ DQ_L553_RT_INH_BCSTREP

#define DQ_L553_RT_INH_BCSTREP (1L<<16)

◆ DQ_L553_RT_INH_MODE

#define DQ_L553_RT_INH_MODE (1L<<14)

◆ DQ_L553_RT_INH_RX

#define DQ_L553_RT_INH_RX (1L<<12)

◆ DQ_L553_RT_INH_TX

#define DQ_L553_RT_INH_TX (1L<<13)

◆ DQ_L553_RT_LB_EN

#define DQ_L553_RT_LB_EN (1L<<15)

◆ DQ_L553_RT_LIST_ADD

#define DQ_L553_RT_LIST_ADD (1L<<31)

◆ DQ_L553_RT_LSTN_A

#define DQ_L553_RT_LSTN_A (1L<<0)

◆ DQ_L553_RT_LSTN_B

#define DQ_L553_RT_LSTN_B (1L<<1)

◆ DQ_L553_RT_MASK

#define DQ_L553_RT_MASK 0x1f

◆ DQ_L553_RT_RT

#define DQ_L553_RT_RT ( N ) (((N)&0x1f)<<6)

◆ DQ_L553_RT_RT_SEL

#define DQ_L553_RT_RT_SEL (1L<<11)

◆ DQ_L553_RT_RT_SHR

#define DQ_L553_RT_RT_SHR 6

◆ DQ_L553_RT_RX

#define DQ_L553_RT_RX	(	RT,
		SA,
		SIZE
	)	(DQ_L553_RT_RT(RT)\|DQ_L553_RT_RT_SEL\|DQ_L553_RT_SADDR(SA)\|DQ_L553_RT_SADDR_SEL\|DQ_L553_RT_TX_SIZE(SIZE))

◆ DQ_L553_RT_RX_BLK

#define DQ_L553_RT_RX_BLK	(	RT,
		SA,
		SIZE,
		BLK
	)	(DQ_L553_RT_RT(RT)\|DQ_L553_RT_RT_SEL\|DQ_L553_RT_SADDR(SA)\|DQ_L553_RT_SADDR_SEL\|DQ_L553_RT_TX_SIZE(SIZE)\|((BLK)?DQ_L553_RT_SET_BLK1:0))

◆ DQ_L553_RT_RX_CMD

#define DQ_L553_RT_RX_CMD (1L<<29)

◆ DQ_L553_RT_RX_DATA_RDY

#define DQ_L553_RT_RX_DATA_RDY	(	RT,
		BLK
	)	(DQ_L553_RT_RT(RT)\|DQ_L553_RT_RT_SEL\|DQ_L553_RT_SADDR(DQ_L553_RT_RX_DATA_RDY_NUM)\|DQ_L553_RT_SET_STATUS\|DQ_L553_RT_TX_SIZE(2)\|((BLK)?DQ_L553_RT_SET_BLK1:0))

◆ DQ_L553_RT_RX_DATA_RDY_NUM

#define DQ_L553_RT_RX_DATA_RDY_NUM 0

◆ DQ_L553_RT_RX_DATA_SENT

#define DQ_L553_RT_RX_DATA_SENT	(	RT,
		BLK
	)	(DQ_L553_RT_RT(RT)\|DQ_L553_RT_RT_SEL\|DQ_L553_RT_SADDR(DQ_L553_RT_RX_DATA_SENT_NUM)\|DQ_L553_RT_SET_STATUS\|DQ_L553_RT_TX_SIZE(2)\|((BLK)?DQ_L553_RT_SET_BLK1:0))

◆ DQ_L553_RT_RX_DATA_SENT_NUM

#define DQ_L553_RT_RX_DATA_SENT_NUM 1

◆ DQ_L553_RT_RX_MODE

#define DQ_L553_RT_RX_MODE ( RT ) (DQ_L553_RT_RT(RT)|DQ_L553_RT_RT_SEL|DQ_L553_RT_SADDR(DQ_L553_RT_RX_MODE_NUM)|DQ_L553_RT_SET_STATUS|DQ_L553_RT_TX_SIZE(2))

◆ DQ_L553_RT_RX_MODE_NUM

#define DQ_L553_RT_RX_MODE_NUM 4

◆ DQ_L553_RT_RX_PORT_STS

#define DQ_L553_RT_RX_PORT_STS ( RT ) (DQ_L553_RT_RT(RT)|DQ_L553_RT_RT_SEL|DQ_L553_RT_SADDR(DQ_L553_RT_RX_PORT_STS_NUM)|DQ_L553_RT_SET_STATUS|DQ_L553_RT_TX_SIZE(2))

◆ DQ_L553_RT_RX_PORT_STS_NUM

#define DQ_L553_RT_RX_PORT_STS_NUM 2

◆ DQ_L553_RT_RX_SYNC

#define DQ_L553_RT_RX_SYNC ( RT ) (DQ_L553_RT_RT(RT)|DQ_L553_RT_RT_SEL|DQ_L553_RT_SADDR(DQ_L553_RT_RX_SYNC_NUM)|DQ_L553_RT_SET_STATUS|DQ_L553_RT_TX_SIZE(2))

◆ DQ_L553_RT_RX_SYNC_NUM

#define DQ_L553_RT_RX_SYNC_NUM 3

◆ DQ_L553_RT_RX_TSCMD

#define DQ_L553_RT_RX_TSCMD (1L<<28)

◆ DQ_L553_RT_SA

#define DQ_L553_RT_SA	(	RT,
		SA
	)	(DQ_L553_BM_RT((RT))\|DQ_L553_BM_RT_SEL\|DQ_L553_BM_SADDR((SA))\|DQ_L553_BM_SADDR_SEL)

◆ DQ_L553_RT_SADDR

#define DQ_L553_RT_SADDR ( N ) (((N)&0x1f)<<0)

◆ DQ_L553_RT_SADDR_SEL

#define DQ_L553_RT_SADDR_SEL (1L<<5)

◆ DQ_L553_RT_SET_BLK1

#define DQ_L553_RT_SET_BLK1 (1L<<13)

◆ DQ_L553_RT_SET_STATUS

#define DQ_L553_RT_SET_STATUS (1L<<12)

◆ DQ_L553_RT_STATMASK

#define DQ_L553_RT_STATMASK (7L<<12)

◆ DQ_L553_RT_STS0

#define DQ_L553_RT_STS0 (1L<<12)

◆ DQ_L553_RT_STS1

#define DQ_L553_RT_STS1 (2L<<12)

◆ DQ_L553_RT_STS2

#define DQ_L553_RT_STS2 (3L<<12)

◆ DQ_L553_RT_TX

#define DQ_L553_RT_TX	(	RT,
		SA,
		SIZE
	)	(DQ_L553_RT_RT(RT)\|DQ_L553_RT_RT_SEL\|DQ_L553_RT_SADDR(SA)\|DQ_L553_RT_SADDR_SEL\|DQ_L553_RT_TX_SIZE(SIZE))

◆ DQ_L553_RT_TX_A

#define DQ_L553_RT_TX_A (1L<<2)

◆ DQ_L553_RT_TX_B

#define DQ_L553_RT_TX_B (1L<<3)

◆ DQ_L553_RT_TX_BLK

#define DQ_L553_RT_TX_BLK	(	RT,
		SA,
		SIZE,
		BLK
	)	(DQ_L553_RT_RT(RT)\|DQ_L553_RT_RT_SEL\|DQ_L553_RT_SADDR(SA)\|DQ_L553_RT_SADDR_SEL\|DQ_L553_RT_TX_SIZE(SIZE)\|((BLK)?DQ_L553_RT_SET_BLK1:0))

◆ DQ_L553_RT_TX_CMDSTS

#define DQ_L553_RT_TX_CMDSTS (1L<<21)

◆ DQ_L553_RT_TX_SIZE

#define DQ_L553_RT_TX_SIZE ( N ) (((N)&0x1f)<<16)

◆ DQ_L553_RT_TX_STS

#define DQ_L553_RT_TX_STS ( RT ) (DQ_L553_RT_RT(RT)|DQ_L553_RT_RT_SEL|DQ_L553_RT_SADDR(DQ_L553_RT_TX_STS_NUM)|DQ_L553_RT_SET_STATUS|DQ_L553_RT_TX_SIZE(2))

◆ DQ_L553_RT_TX_STS_NUM

#define DQ_L553_RT_TX_STS_NUM 0

◆ DQ_L553_RT_TX_TSCMD

#define DQ_L553_RT_TX_TSCMD (1L<<22)

◆ DQ_L553_RT_TX_VECTOR

#define DQ_L553_RT_TX_VECTOR ( RT ) (DQ_L553_RT_RT(RT)|DQ_L553_RT_RT_SEL|DQ_L553_RT_SADDR(DQ_L553_RT_TX_VECTOR_NUM)|DQ_L553_RT_SET_STATUS|DQ_L553_RT_TX_SIZE(2))

◆ DQ_L553_RT_TX_VECTOR_NUM

#define DQ_L553_RT_TX_VECTOR_NUM 1

◆ DQ_L553_RTLISTSZ

#define DQ_L553_RTLISTSZ 360

◆ DQ_L553_RTS_BERRORS

#define DQ_L553_RTS_BERRORS (1L<<4)

◆ DQ_L553_RTS_BLK

#define DQ_L553_RTS_BLK ( C ) (((C)&1)<<DQ_L553_RTS_BLK1_SHR)

◆ DQ_L553_RTS_BLK1_SHR

#define DQ_L553_RTS_BLK1_SHR 13

◆ DQ_L553_RTS_BMDATA

#define DQ_L553_RTS_BMDATA (1L<<2)

◆ DQ_L553_RTS_CFG0

#define DQ_L553_RTS_CFG0 (1L<<0)

◆ DQ_L553_RTS_CFG1

#define DQ_L553_RTS_CFG1 (1L<<1)

◆ DQ_L553_RTS_CH

#define DQ_L553_RTS_CH ( CH ) (((CH)&1)<<DQ_L553_RTS_CHAN_NUM_SHR)

◆ DQ_L553_RTS_CHAN_NUM

#define DQ_L553_RTS_CHAN_NUM (1L<<12)

◆ DQ_L553_RTS_CHAN_NUM_SHR

#define DQ_L553_RTS_CHAN_NUM_SHR 12

◆ DQ_L553_RTS_CHSTAT

#define DQ_L553_RTS_CHSTAT (1L<<3)

◆ DQ_L553_RTS_DATAREADY

#define DQ_L553_RTS_DATAREADY (1L<<0)

◆ DQ_L553_RTS_DATASENT

#define DQ_L553_RTS_DATASENT (1L<<1)

◆ DQ_L553_RTS_MODECMD

#define DQ_L553_RTS_MODECMD (1L<<3)

◆ DQ_L553_RTS_RQ_MASK

#define DQ_L553_RTS_RQ_MASK 0x3f

◆ DQ_L553_RTS_RT

#define DQ_L553_RTS_RT ( N ) (((N)&0x1f)<<DQ_L553_RTS_RT_SHR)

◆ DQ_L553_RTS_RT_BLK1

#define DQ_L553_RTS_RT_BLK1 (1L<<13)

◆ DQ_L553_RTS_RT_CTL

#define DQ_L553_RTS_RT_CTL (1L<<15)

◆ DQ_L553_RTS_RT_CTL_SHR

#define DQ_L553_RTS_RT_CTL_SHR 15

◆ DQ_L553_RTS_RT_SHR

#define DQ_L553_RTS_RT_SHR 6

◆ DQ_L553_RTS_RT_STS

#define DQ_L553_RTS_RT_STS (1L<<15)

◆ DQ_L553_RTS_RT_STS_SHR

#define DQ_L553_RTS_RT_STS_SHR 15

◆ DQ_L553_RTS_RTEN

#define DQ_L553_RTS_RTEN (1L<<3)

◆ DQ_L553_RTS_RX_BLK

#define DQ_L553_RTS_RX_BLK (1L<<4)

◆ DQ_L553_RTS_SA_SHR

#define DQ_L553_RTS_SA_SHR 0

◆ DQ_L553_RTS_SADDR

#define DQ_L553_RTS_SADDR ( N ) (((N)&0x1f)<<DQ_L553_RTS_SA_SHR)

◆ DQ_L553_RTS_STATUS

#define DQ_L553_RTS_STATUS (1L<<11)

◆ DQ_L553_RTS_STATUS_SHR

#define DQ_L553_RTS_STATUS_SHR 11

◆ DQ_L553_RTS_STS0

#define DQ_L553_RTS_STS0 (1L<<0)

◆ DQ_L553_RTS_STS1

#define DQ_L553_RTS_STS1 (1L<<1)

◆ DQ_L553_RTS_STS2

#define DQ_L553_RTS_STS2 (1L<<2)

◆ DQ_L553_RTS_TX_BLK

#define DQ_L553_RTS_TX_BLK (1L<<2)

◆ DQ_L553_RTS_XCODE

#define DQ_L553_RTS_XCODE (1L<<14)

◆ DQ_L553_RTVAL_AND_WRITE

#define DQ_L553_RTVAL_AND_WRITE (2L<<16)

◆ DQ_L553_RTVAL_CLEARALL

#define DQ_L553_RTVAL_CLEARALL (1L<<0)

◆ DQ_L553_RTVAL_OR_WRITE

#define DQ_L553_RTVAL_OR_WRITE (1L<<16)

◆ DQ_L553_RTVAL_WRITE

#define DQ_L553_RTVAL_WRITE 0

◆ DQ_L553_RXFIFOSIZE

#define DQ_L553_RXFIFOSIZE 1024

◆ DQ_L553_SA_MASK

#define DQ_L553_SA_MASK 0x1f

◆ DQ_L553_SCHEDDATASZ

#define DQ_L553_SCHEDDATASZ 256

◆ DQ_L553_SCHEDSIZE

#define DQ_L553_SCHEDSIZE 256

◆ DQ_L553_SET_RT_ENABLE

#define DQ_L553_SET_RT_ENABLE (1L<<2)

◆ DQ_L553_SET_RT_RTIMING

#define DQ_L553_SET_RT_RTIMING (1L<<4)

◆ DQ_L553_SET_RX_BLOCK

#define DQ_L553_SET_RX_BLOCK (1L<<1)

◆ DQ_L553_SET_TX_BLOCK

#define DQ_L553_SET_TX_BLOCK (1L<<0)

◆ DQ_L553_SET_VALID_ENTRY

#define DQ_L553_SET_VALID_ENTRY (1L<<3)

◆ DQ_L553_STATUS_DATA

#define DQ_L553_STATUS_DATA	(	CH,
		RT,
		BLK,
		RQ
	)	(DQ_L553_RTS_RT_STS\|DQ_L553_RTS_RT(RT)\|DQ_L553_RTS_BLK(BLK)\|(((CH)&1)<<DQ_L553_RTS_CHAN_NUM_SHR)\|RQ)

◆ DQ_L553_STATUS_STSF

#define DQ_L553_STATUS_STSF	(	CH,
		RT,
		STS
	)	(DQ_L553_RTS_RT_STS\|DQ_L553_RTS_STATUS\|DQ_L553_RTS_RT(RT)\|DQ_L553_RTS_CH(CH)\|STS)

◆ DQ_L553_STORE_FLAGS

#define DQ_L553_STORE_FLAGS (1L<<18)

◆ DQ_L553_STORE_TS

#define DQ_L553_STORE_TS (1L<<17)

◆ DQ_L553_SUBADDR

#define DQ_L553_SUBADDR 32

◆ DQ_L553_TERMADDR

#define DQ_L553_TERMADDR 32

◆ DQ_L553_TRANSFORMER

#define DQ_L553_TRANSFORMER (2L<<0)

◆ DQ_L553_TXFIFOSIZE

#define DQ_L553_TXFIFOSIZE 256

◆ DQ_L601_FIFOSZ

#define DQ_L601_FIFOSZ (256)

◆ DQ_L604_FIFOSZ

#define DQ_L604_FIFOSZ 1024

◆ DQ_L651_NAMELEN

#define DQ_L651_NAMELEN (32)

◆ DQ_L801_FIFOSZ

#define DQ_L801_FIFOSZ 256

◆ DQ_L802_FIFOSZ

#define DQ_L802_FIFOSZ 256

◆ DQ_L90x_BASE

#define DQ_L90x_BASE 66000000

◆ DQ_L90x_CHAN

#define DQ_L90x_CHAN 2

◆ DQ_L90x_INFOSZ

#define DQ_L90x_INFOSZ DQ_MAX_INFO_SIZE

◆ DQ_L90x_NAMELEN

#define DQ_L90x_NAMELEN 32

◆ DQ_L91x_NAMELEN

#define DQ_L91x_NAMELEN (32)

◆ DQ_LAYER_CALDACS

#define DQ_LAYER_CALDACS 4

◆ DQ_LAYER_CHAN

#define DQ_LAYER_CHAN 4

◆ DQ_LAYER_NAMELEN

#define DQ_LAYER_NAMELEN 20

◆ DQ_LCR651_CLK_100MHZ

#define DQ_LCR651_CLK_100MHZ (0L<<2)

◆ DQ_LCR651_CLK_160MHZ

#define DQ_LCR651_CLK_160MHZ (1L<<2)

◆ DQ_LCR651_DB

#define DQ_LCR651_DB (1L<<1)

◆ DQ_LCR651_DCEN

#define DQ_LCR651_DCEN (1L<<0)

◆ DQ_LCR651_LED

#define DQ_LCR651_LED (1L<<1)

◆ DQ_LCR651_RXT

#define DQ_LCR651_RXT (1L<<4)

◆ DQ_LCR651_STS_ICF

#define DQ_LCR651_STS_ICF (1L<<2)

◆ DQ_LCR651_STS_ICIV

#define DQ_LCR651_STS_ICIV (1L<<0)

◆ DQ_LDIAG_ADC_GND

#define DQ_LDIAG_ADC_GND (1)

◆ DQ_LDIAG_ADC_GND_2

#define DQ_LDIAG_ADC_GND_2 (3)

◆ DQ_LDIAG_ADC_GND_3

#define DQ_LDIAG_ADC_GND_3 (5)

◆ DQ_LDIAG_ADC_GND_4

#define DQ_LDIAG_ADC_GND_4 (9)

◆ DQ_LDIAG_ADC_GND_5

#define DQ_LDIAG_ADC_GND_5 (10)

◆ DQ_LDIAG_ADC_GND_6

#define DQ_LDIAG_ADC_GND_6 (11)

◆ DQ_LDIAG_ADC_GND_7

#define DQ_LDIAG_ADC_GND_7 (12)

◆ DQ_LDIAG_ADC_GND_8

#define DQ_LDIAG_ADC_GND_8 (14)

◆ DQ_LDIAG_ADC_TEMP1

#define DQ_LDIAG_ADC_TEMP1 (13)

◆ DQ_LDIAG_ADC_TEMP2

#define DQ_LDIAG_ADC_TEMP2 (15)

◆ DQ_LDIAG_ADC_V_1_2

#define DQ_LDIAG_ADC_V_1_2 (8)

◆ DQ_LDIAG_ADC_V_1_5

#define DQ_LDIAG_ADC_V_1_5 (7)

◆ DQ_LDIAG_ADC_V_24

#define DQ_LDIAG_ADC_V_24 (4)

◆ DQ_LDIAG_ADC_V_2_5

#define DQ_LDIAG_ADC_V_2_5 (0)

◆ DQ_LDIAG_ADC_V_3_3

#define DQ_LDIAG_ADC_V_3_3 (2)

◆ DQ_LDIAG_ADC_V_IN

#define DQ_LDIAG_ADC_V_IN (6)

◆ DQ_LDIAG_CVT_GND

#define DQ_LDIAG_CVT_GND ( N ) ((N-0x800000)*0.000000149)

◆ DQ_LDIAG_CVT_TEMP1

#define DQ_LDIAG_CVT_TEMP1 ( N ) ((N-0x800000)/644)

◆ DQ_LDIAG_CVT_TEMP2

#define DQ_LDIAG_CVT_TEMP2 ( N ) ((N-0x800000)/644)

◆ DQ_LDIAG_CVT_V_1_2

#define DQ_LDIAG_CVT_V_1_2 ( N ) (((N-0x800000)*0.000000149)*11)

◆ DQ_LDIAG_CVT_V_1_5

#define DQ_LDIAG_CVT_V_1_5 ( N ) (((N-0x800000)*0.000000149)*11)

◆ DQ_LDIAG_CVT_V_24

#define DQ_LDIAG_CVT_V_24 ( N ) (((N-0x800000)*0.000000149)*11)

◆ DQ_LDIAG_CVT_V_2_5

#define DQ_LDIAG_CVT_V_2_5 ( N ) (((N-0x800000)*0.000000149)*11)

◆ DQ_LDIAG_CVT_V_3_3

#define DQ_LDIAG_CVT_V_3_3 ( N ) (((N-0x800000)*0.000000149)*11)

◆ DQ_LDIAG_CVT_V_IN

#define DQ_LDIAG_CVT_V_IN ( N ) (((N-0x800000)*0.000000149)*23.1)

◆ DQ_LN_100ms_TIMESTAMP

#define DQ_LN_100ms_TIMESTAMP (6600000-1)

◆ DQ_LN_100us_TIMESTAMP

#define DQ_LN_100us_TIMESTAMP (6600-1)

◆ DQ_LN_10ms_TIMESTAMP

#define DQ_LN_10ms_TIMESTAMP (660000-1)

◆ DQ_LN_10us_TIMESTAMP

#define DQ_LN_10us_TIMESTAMP (660-1)

◆ DQ_LN_1ms_TIMESTAMP

#define DQ_LN_1ms_TIMESTAMP (66000-1)

◆ DQ_LN_1s_TIMESTAMP

#define DQ_LN_1s_TIMESTAMP (66000000-1)

◆ DQ_LN_1us_TIMESTAMP

#define DQ_LN_1us_TIMESTAMP (66-1)

◆ DQ_LN_ACTIVE

#define DQ_LN_ACTIVE (1L<<1)

◆ DQ_LN_BURST

#define DQ_LN_BURST (1L<<19)

◆ DQ_LN_CALGAIN

#define DQ_LN_CALGAIN (1L<<1)

◆ DQ_LN_CALOFFS

#define DQ_LN_CALOFFS (1L<<2)

◆ DQ_LN_CLCKSRC0

#define DQ_LN_CLCKSRC0 (1L<<2)

◆ DQ_LN_CLCKSRC1

#define DQ_LN_CLCKSRC1 (1L<<3)

◆ DQ_LN_CLKID_CLIN

#define DQ_LN_CLKID_CLIN (1L<<1)

◆ DQ_LN_CLKID_CLOUT

#define DQ_LN_CLKID_CLOUT (1L<<0)

◆ DQ_LN_CLKID_CVIN

#define DQ_LN_CLKID_CVIN (1L<<3)

◆ DQ_LN_CLKID_CVOUT

#define DQ_LN_CLKID_CVOUT (1L<<2)

◆ DQ_LN_CLKID_DUTY0

#define DQ_LN_CLKID_DUTY0 (1L<<6)

◆ DQ_LN_CLKID_DUTY1

#define DQ_LN_CLKID_DUTY1 (1L<<7)

◆ DQ_LN_CLKID_TMR0

#define DQ_LN_CLKID_TMR0 (1L<<4)

◆ DQ_LN_CLKID_TMR1

#define DQ_LN_CLKID_TMR1 (1L<<5)

◆ DQ_LN_CVCKSRC0

#define DQ_LN_CVCKSRC0 (1L<<4)

◆ DQ_LN_CVCKSRC1

#define DQ_LN_CVCKSRC1 (1L<<5)

◆ DQ_LN_DATASZ16

#define DQ_LN_DATASZ16 (2L)

◆ DQ_LN_DATASZ24

#define DQ_LN_DATASZ24 (3L)

◆ DQ_LN_DATASZ32

#define DQ_LN_DATASZ32 (4L)

◆ DQ_LN_DATASZ8

#define DQ_LN_DATASZ8 (1L)

◆ DQ_LN_ENABLED

#define DQ_LN_ENABLED (1L<<0)

◆ DQ_LN_GETRAW

#define DQ_LN_GETRAW (1L<<12)

◆ DQ_LN_INTSRC

#define DQ_LN_INTSRC (1<<0)

◆ DQ_LN_IRQEN

#define DQ_LN_IRQEN (1L<<10)

◆ DQ_LN_MAPPED

#define DQ_LN_MAPPED (1L<<15)

◆ DQ_LN_MAX_CLOCKS

#define DQ_LN_MAX_CLOCKS (4)

◆ DQ_LN_MAX_DIOX

#define DQ_LN_MAX_DIOX (4)

◆ DQ_LN_MAX_SYNCX

#define DQ_LN_MAX_SYNCX (4)

◆ DQ_LN_MAX_TRIGS

#define DQ_LN_MAX_TRIGS (4)

◆ DQ_LN_NO_TIMESTAMP_RESET

#define DQ_LN_NO_TIMESTAMP_RESET (1L<<21)

◆ DQ_LN_PTRIGEDGE0

#define DQ_LN_PTRIGEDGE0 (1L<<8)

◆ DQ_LN_PTRIGEDGE1

#define DQ_LN_PTRIGEDGE1 (1L<<9)

◆ DQ_LN_RAW32

#define DQ_LN_RAW32 (1L<<18)

◆ DQ_LN_RECYCLE

#define DQ_LN_RECYCLE (1L<<13)

◆ DQ_LN_STREAMING

#define DQ_LN_STREAMING (1L<<14)

◆ DQ_LN_STRIGEDGE0

#define DQ_LN_STRIGEDGE0 (1L<<6)

◆ DQ_LN_STRIGEDGE1

#define DQ_LN_STRIGEDGE1 (1L<<7)

◆ DQ_LN_TMREN

#define DQ_LN_TMREN (1L<<11)

◆ DQ_LN_VMAPPED

#define DQ_LN_VMAPPED (1L<<20)

◆ DQ_LNCL_CHANGAIN

#define DQ_LNCL_CHANGAIN	(	C,
		G
	)	((C)\|DQ_LNCL_GAIN(G))

◆ DQ_LNCL_CLK

#define DQ_LNCL_CLK (1UL<<24)

◆ DQ_LNCL_CTR

#define DQ_LNCL_CTR (1UL<<23)

◆ DQ_LNCL_DIFF

#define DQ_LNCL_DIFF (1UL<<15)

◆ DQ_LNCL_DIO

#define DQ_LNCL_DIO (1UL<<18)

◆ DQ_LNCL_GAIN

#define DQ_LNCL_GAIN ( G ) (((G) & 0xf)<<8)

◆ DQ_LNCL_GETCHAN

#define DQ_LNCL_GETCHAN ( E ) ((E) & 0xff)

◆ DQ_LNCL_GETGAIN

#define DQ_LNCL_GETGAIN ( E ) (((E) & 0xf00)>>8)

◆ DQ_LNCL_INOUT

#define DQ_LNCL_INOUT (1UL<<30)

◆ DQ_LNCL_IRQ

#define DQ_LNCL_IRQ (1UL<<27)

◆ DQ_LNCL_LAST

#define DQ_LNCL_LAST (0)

◆ DQ_LNCL_NEXT

#define DQ_LNCL_NEXT (1UL<<31)

◆ DQ_LNCL_NOWAIT

#define DQ_LNCL_NOWAIT (1UL<<26)

◆ DQ_LNCL_READSTATUS

#define DQ_LNCL_READSTATUS (0xfe)

◆ DQ_LNCL_RSVD0

#define DQ_LNCL_RSVD0 (1UL<<16)

◆ DQ_LNCL_RSVD1

#define DQ_LNCL_RSVD1 (1UL<<17)

◆ DQ_LNCL_SKIP

#define DQ_LNCL_SKIP (1UL<<25)

◆ DQ_LNCL_SLOW

#define DQ_LNCL_SLOW (1UL<<19)

◆ DQ_LNCL_SS0

#define DQ_LNCL_SS0 (1UL<<28)

◆ DQ_LNCL_SS1

#define DQ_LNCL_SS1 (1UL<<29)

◆ DQ_LNCL_TIMESTAMP

#define DQ_LNCL_TIMESTAMP (0xff)

◆ DQ_LNCL_TSRQ

#define DQ_LNCL_TSRQ (1UL<<20)

◆ DQ_LNCL_UPDALL

#define DQ_LNCL_UPDALL (1UL<<21)

◆ DQ_LNCL_WRITE

#define DQ_LNCL_WRITE (1UL<<22)

◆ DQ_LSR416_CLKIN_TRIG

#define DQ_LSR416_CLKIN_TRIG (22)

◆ DQ_LSR416_CLOUT

#define DQ_LSR416_CLOUT (20)

◆ DQ_LSR416_VCCIS

#define DQ_LSR416_VCCIS (23)

◆ DQ_LT1608_GETVAL

#define DQ_LT1608_GETVAL ( V ) (V)

◆ DQ_LT1608_GETVALS

#define DQ_LT1608_GETVALS ( V ) ((V&0xffff)^0x8000)

◆ DQ_LT2440_110S

#define DQ_LT2440_110S 110000

◆ DQ_LT2440_13_7S

#define DQ_LT2440_13_7S 13750

◆ DQ_LT2440_1760S

#define DQ_LT2440_1760S 1760000

◆ DQ_LT2440_220S

#define DQ_LT2440_220S 220000

◆ DQ_LT2440_27_5S

#define DQ_LT2440_27_5S 27500

◆ DQ_LT2440_3520S

#define DQ_LT2440_3520S 3520000

◆ DQ_LT2440_440S

#define DQ_LT2440_440S 440000

◆ DQ_LT2440_55S

#define DQ_LT2440_55S 55000

◆ DQ_LT2440_6_9S

#define DQ_LT2440_6_9S 6875

◆ DQ_LT2440_880S

#define DQ_LT2440_880S 880000

◆ DQ_LT2440_FF01

#define DQ_LT2440_FF01 ( V ) (V&3)

◆ DQ_LT2440_GETVAL

#define DQ_LT2440_GETVAL ( V ) (((V>>5)&0xffffff)^0x800000)

◆ DQ_LT2440_ISOVRRANGE

#define DQ_LT2440_ISOVRRANGE ( V ) (((V&(1L<<28))&&(V&(1L<<29)))?1:0)

◆ DQ_LT2440_ISUNDRANGE

#define DQ_LT2440_ISUNDRANGE ( V ) ((V&((1L<<28)|(1L<<29)))?0:1)

◆ DQ_LT2440_SPDS

#define DQ_LT2440_SPDS ( N ) (3000000 >> (N-1))

◆ DQ_LT2440_XTRABITS

#define DQ_LT2440_XTRABITS ( V ) ((V>>2)&7)

◆ DQ_LT2448_GETVAL

#define DQ_LT2448_GETVAL ( V ) (((V>>5)&0xffffff)^0x800000)

◆ DQ_LTC1661_VAL

#define DQ_LTC1661_VAL ( V ) ((V & 0x3ff)<<2)

◆ DQ_MAN_CTR

#define DQ_MAN_CTR 0x00

◆ DQ_MAN_FCNTI

#define DQ_MAN_FCNTI 0x1C

◆ DQ_MAN_FCNTO

#define DQ_MAN_FCNTO 0x20

◆ DQ_MAN_FDTI

#define DQ_MAN_FDTI 0x14

◆ DQ_MAN_FDTO

#define DQ_MAN_FDTO 0x18

◆ DQ_MAN_IFWR

#define DQ_MAN_IFWR 0x0C

◆ DQ_MAN_MSGSIZE

#define DQ_MAN_MSGSIZE 256

◆ DQ_MAN_OFWR

#define DQ_MAN_OFWR 0x10

◆ DQ_MAN_STR

#define DQ_MAN_STR 0x00

◆ DQ_MASKDEVN

#define DQ_MASKDEVN (0x1F)

◆ DQ_MASKSS

#define DQ_MASKSS (0x7)

◆ DQ_MAX_ETH_SIZE

#define DQ_MAX_ETH_SIZE (576)

◆ DQ_MAX_ETH_SIZE_100

#define DQ_MAX_ETH_SIZE_100 (1518)

◆ DQ_MAX_INFO_ITEMS

#define DQ_MAX_INFO_ITEMS (100)

◆ DQ_MAX_INFO_SIZE

#define DQ_MAX_INFO_SIZE (2048)

◆ DQ_MAX_UDP_SIZE_100

#define DQ_MAX_UDP_SIZE_100 (1472)

◆ DQ_MAXDEVN

#define DQ_MAXDEVN (0x20)

◆ DQ_MAXDEVPHYS

#define DQ_MAXDEVPHYS (0x10)

◆ DQ_MAXSS

#define DQ_MAXSS (8)

◆ DQ_OFFSETD201

#define DQ_OFFSETD201 (1500000000UL)

◆ DQ_OFFSETD201_10

#define DQ_OFFSETD201_10 (1000000000UL)

◆ DQ_OFFSETD205

#define DQ_OFFSETD205 (1000000000UL)

◆ DQ_ONESTEP201

#define DQ_ONESTEP201 (45776UL)

◆ DQ_ONESTEP201_10

#define DQ_ONESTEP201_10 (30518UL)

◆ DQ_ONESTEP205

#define DQ_ONESTEP205 (7629UL)

◆ DQ_ONEVOLTINNV

#define DQ_ONEVOLTINNV (1000000000)

◆ DQ_PC104_AEN

#define DQ_PC104_AEN (1L<<10)

◆ DQ_PC104_ASSERT_RESET

#define DQ_PC104_ASSERT_RESET (1L<<0)

◆ DQ_PC104_ASSIGN_IRQA

#define DQ_PC104_ASSIGN_IRQA ( N ) ((N)&0x1ff)

◆ DQ_PC104_ASSIGN_IRQB

#define DQ_PC104_ASSIGN_IRQB ( N ) (((N)&0x1ff)<<16)

◆ DQ_PC104_BA

#define DQ_PC104_BA ( N ) ((N)&0xfffff)

◆ DQ_PC104_BA0

#define DQ_PC104_BA0 (0x2008)

◆ DQ_PC104_BA1

#define DQ_PC104_BA1 (0x200C)

◆ DQ_PC104_BA_ACCESS_16

#define DQ_PC104_BA_ACCESS_16 (1L<<25)

◆ DQ_PC104_BA_AEN_A17

#define DQ_PC104_BA_AEN_A17 (1L<<26)

◆ DQ_PC104_BA_ALL

#define DQ_PC104_BA_ALL (0xff000000)

◆ DQ_PC104_BA_IOCHKRDY

#define DQ_PC104_BA_IOCHKRDY (1L<<29)

◆ DQ_PC104_BA_IOCS16

#define DQ_PC104_BA_IOCS16 (1L<<28)

◆ DQ_PC104_BA_IOSPACE

#define DQ_PC104_BA_IOSPACE (0L<<30)

◆ DQ_PC104_BA_MEMCS16

#define DQ_PC104_BA_MEMCS16 (1L<<27)

◆ DQ_PC104_BA_MEMIO

#define DQ_PC104_BA_MEMIO (1L<<30)

◆ DQ_PC104_BA_SELECT

#define DQ_PC104_BA_SELECT (1L<<31)

◆ DQ_PC104_BALE

#define DQ_PC104_BALE (1L<<11)

◆ DQ_PC104_BAN

#define DQ_PC104_BAN ( N ) (((N)&0x1f)<<20)

◆ DQ_PC104_BASE

#define DQ_PC104_BASE (66000000)

◆ DQ_PC104_BCLK

#define DQ_PC104_BCLK (1L<<9)

◆ DQ_PC104_BCMD0

#define DQ_PC104_BCMD0 (0x2038)

◆ DQ_PC104_BCMD1

#define DQ_PC104_BCMD1 (0x203C)

◆ DQ_PC104_BE

#define DQ_PC104_BE (1L<<2)

◆ DQ_PC104_BLKMEM0

#define DQ_PC104_BLKMEM0 (0xF000)

◆ DQ_PC104_BLKMEM0i

#define DQ_PC104_BLKMEM0i ((DQ_PC104_BLKMEM0-0x8000)>>2)

◆ DQ_PC104_BLKMEM1

#define DQ_PC104_BLKMEM1 (0xF800)

◆ DQ_PC104_BLKMEM1i

#define DQ_PC104_BLKMEM1i ((DQ_PC104_BLKMEM1-0x8000)>>2)

◆ DQ_PC104_BLKSCRATCH

#define DQ_PC104_BLKSCRATCH (0xFFC0)

◆ DQ_PC104_BLKSCRATCHi

#define DQ_PC104_BLKSCRATCHi ((DQ_PC104_BLKSCRATCH-0x8000)>>2)

◆ DQ_PC104_BUSCLOCK_0

#define DQ_PC104_BUSCLOCK_0 (0)

◆ DQ_PC104_BUSCLOCK_5_5MHz

#define DQ_PC104_BUSCLOCK_5_5MHz (1L<<4)

◆ DQ_PC104_BUSCLOCK_6_6MHz

#define DQ_PC104_BUSCLOCK_6_6MHz (2L<<4)

◆ DQ_PC104_BUSCLOCK_8MHz

#define DQ_PC104_BUSCLOCK_8MHz (3L<<4)

◆ DQ_PC104_CALDACS

#define DQ_PC104_CALDACS (2)

◆ DQ_PC104_CDO_ACC16BIT

#define DQ_PC104_CDO_ACC16BIT (0L<<27)

◆ DQ_PC104_CDO_ACC8BIT

#define DQ_PC104_CDO_ACC8BIT (1L<<27)

◆ DQ_PC104_CDO_ADDRESS

#define DQ_PC104_CDO_ADDRESS ( N ) ((N)&0xffffff)

◆ DQ_PC104_CDO_DIR

#define DQ_PC104_CDO_DIR (1L<<25)

◆ DQ_PC104_CDO_DNAADDR

#define DQ_PC104_CDO_DNAADDR ( N ) ((N)&0xffff)

◆ DQ_PC104_CDO_DNAADDRi

#define DQ_PC104_CDO_DNAADDRi ( N ) ((((N)-0x8000)>>2)&0x1fff)

◆ DQ_PC104_CDO_ENDIRQ

#define DQ_PC104_CDO_ENDIRQ (1L<<28)

◆ DQ_PC104_CDO_IMMDATA

#define DQ_PC104_CDO_IMMDATA (1L<<26)

◆ DQ_PC104_CDO_IOSPCSEL

#define DQ_PC104_CDO_IOSPCSEL (0L<<24)

◆ DQ_PC104_CDO_MEMSPCSEL

#define DQ_PC104_CDO_MEMSPCSEL (1L<<24)

◆ DQ_PC104_CDO_READ

#define DQ_PC104_CDO_READ (0L<<25)

◆ DQ_PC104_CDO_TRANSIZE

#define DQ_PC104_CDO_TRANSIZE ( N ) ((((N)-1)&0xfff)<<16)

◆ DQ_PC104_CDO_WRITE

#define DQ_PC104_CDO_WRITE (1L<<25)

◆ DQ_PC104_CFG

#define DQ_PC104_CFG (0x2000)

◆ DQ_PC104_CHAN

#define DQ_PC104_CHAN (2)

◆ DQ_PC104_CHNUM

#define DQ_PC104_CHNUM (0x1)

◆ DQ_PC104_CHTYPE

#define DQ_PC104_CHTYPE (0xE)

◆ DQ_PC104_CL_CLK

#define DQ_PC104_CL_CLK (1L<<29)

◆ DQ_PC104_CL_IRQA

#define DQ_PC104_CL_IRQA (2)

◆ DQ_PC104_CL_IRQB

#define DQ_PC104_CL_IRQB (3)

◆ DQ_PC104_CL_IRQEN

#define DQ_PC104_CL_IRQEN (1L<<3)

◆ DQ_PC104_CL_SW

#define DQ_PC104_CL_SW (0)

◆ DQ_PC104_CL_TIMER

#define DQ_PC104_CL_TIMER (1)

◆ DQ_PC104_CONFIGURE_BUS

#define DQ_PC104_CONFIGURE_BUS (7)

◆ DQ_PC104_CONFIGURE_INTCLK

#define DQ_PC104_CONFIGURE_INTCLK (8)

◆ DQ_PC104_DACK

#define DQ_PC104_DACK (1L<<13)

◆ DQ_PC104_DC12_1

#define DQ_PC104_DC12_1 (1L<<1)

◆ DQ_PC104_DC12_2

#define DQ_PC104_DC12_2 (1L<<2)

◆ DQ_PC104_DC12_3

#define DQ_PC104_DC12_3 (1L<<3)

◆ DQ_PC104_DC12_4

#define DQ_PC104_DC12_4 (1L<<5)

◆ DQ_PC104_DC12_5

#define DQ_PC104_DC12_5 (1L<<6)

◆ DQ_PC104_DC12N_1

#define DQ_PC104_DC12N_1 (1L<<4)

◆ DQ_PC104_DC12N_2

#define DQ_PC104_DC12N_2 (1L<<7)

◆ DQ_PC104_DC5N

#define DQ_PC104_DC5N (1L<<0)

◆ DQ_PC104_DP0

#define DQ_PC104_DP0 (0x8000)

◆ DQ_PC104_IER_AE

#define DQ_PC104_IER_AE (1L<<9)

◆ DQ_PC104_IER_IRQA

#define DQ_PC104_IER_IRQA (1L<<0)

◆ DQ_PC104_IER_IRQB

#define DQ_PC104_IER_IRQB (1L<<1)

◆ DQ_PC104_IER_RBD

#define DQ_PC104_IER_RBD (1L<<6)

◆ DQ_PC104_IER_RIOD

#define DQ_PC104_IER_RIOD (1L<<4)

◆ DQ_PC104_IER_RMD

#define DQ_PC104_IER_RMD (1L<<2)

◆ DQ_PC104_IER_TO

#define DQ_PC104_IER_TO (1L<<8)

◆ DQ_PC104_IER_WBD

#define DQ_PC104_IER_WBD (1L<<7)

◆ DQ_PC104_IER_WIOD

#define DQ_PC104_IER_WIOD (1L<<5)

◆ DQ_PC104_IER_WMD

#define DQ_PC104_IER_WMD (1L<<3)

◆ DQ_PC104_INFOSZ

#define DQ_PC104_INFOSZ (DQ_MAX_INFO_SIZE)

◆ DQ_PC104_IOR

#define DQ_PC104_IOR (1L<<4)

◆ DQ_PC104_IORADDR

#define DQ_PC104_IORADDR (0x2024)

◆ DQ_PC104_IORD

#define DQ_PC104_IORD (0x2024)

◆ DQ_PC104_IOW

#define DQ_PC104_IOW (1L<<5)

◆ DQ_PC104_IOWADDR

#define DQ_PC104_IOWADDR (0x2030)

◆ DQ_PC104_IOWR

#define DQ_PC104_IOWR (0x2034)

◆ DQ_PC104_IRQ10S

#define DQ_PC104_IRQ10S (1L<<5)

◆ DQ_PC104_IRQ11S

#define DQ_PC104_IRQ11S (1L<<6)

◆ DQ_PC104_IRQ12S

#define DQ_PC104_IRQ12S (1L<<7)

◆ DQ_PC104_IRQ14_15S

#define DQ_PC104_IRQ14_15S (1L<<8)

◆ DQ_PC104_IRQ3S

#define DQ_PC104_IRQ3S (1L<<0)

◆ DQ_PC104_IRQ4S

#define DQ_PC104_IRQ4S (1L<<1)

◆ DQ_PC104_IRQ5S

#define DQ_PC104_IRQ5S (1L<<2)

◆ DQ_PC104_IRQ6S

#define DQ_PC104_IRQ6S (1L<<3)

◆ DQ_PC104_IRQ7_9S

#define DQ_PC104_IRQ7_9S (1L<<4)

◆ DQ_PC104_IRQA

#define DQ_PC104_IRQA (0x2010)

◆ DQ_PC104_IRQB

#define DQ_PC104_IRQB (0x2014)

◆ DQ_PC104_IRQN

#define DQ_PC104_IRQN (1L<<6)

◆ DQ_PC104_IRQP

#define DQ_PC104_IRQP (0L<<6)

◆ DQ_PC104_IRQPINS

#define DQ_PC104_IRQPINS (0x201C)

◆ DQ_PC104_ISR_DEFAULT

#define DQ_PC104_ISR_DEFAULT (0)

◆ DQ_PC104_ISR_SIMA_ASCBA

#define DQ_PC104_ISR_SIMA_ASCBA (4)

◆ DQ_PC104_ISR_SIMA_ASCBB

#define DQ_PC104_ISR_SIMA_ASCBB (5)

◆ DQ_PC104_ISR_SIMA_ASCBC

#define DQ_PC104_ISR_SIMA_ASCBC (6)

◆ DQ_PC104_ISR_SIMA_ICB

#define DQ_PC104_ISR_SIMA_ICB (1)

◆ DQ_PC104_ISR_SIMA_RSB

#define DQ_PC104_ISR_SIMA_RSB (2)

◆ DQ_PC104_LCR_DPEN

#define DQ_PC104_LCR_DPEN (1L<<2)

◆ DQ_PC104_LCR_LED

#define DQ_PC104_LCR_LED (1L<<1)

◆ DQ_PC104_LNEN

#define DQ_PC104_LNEN (0x2018)

◆ DQ_PC104_MAXCLFRQ

#define DQ_PC104_MAXCLFRQ (2000)

◆ DQ_PC104_MAXCVFRQ

#define DQ_PC104_MAXCVFRQ (2000)

◆ DQ_PC104_MAXWAIT

#define DQ_PC104_MAXWAIT (20)

◆ DQ_PC104_MAXWAIT_BUF

#define DQ_PC104_MAXWAIT_BUF (5)

◆ DQ_PC104_MEMR

#define DQ_PC104_MEMR (1L<<0)

◆ DQ_PC104_MEMRD

#define DQ_PC104_MEMRD (0x2020)

◆ DQ_PC104_MEMW

#define DQ_PC104_MEMW (1L<<1)

◆ DQ_PC104_MEMWR

#define DQ_PC104_MEMWR (0x202C)

◆ DQ_PC104_MRADDR

#define DQ_PC104_MRADDR (0x2020)

◆ DQ_PC104_MWADDR

#define DQ_PC104_MWADDR (0x2028)

◆ DQ_PC104_NAMELEN

#define DQ_PC104_NAMELEN (32)

◆ DQ_PC104_OSC

#define DQ_PC104_OSC (1L<<8)

◆ DQ_PC104_OSC_14MHz

#define DQ_PC104_OSC_14MHz (1L<<3)

◆ DQ_PC104_READBUS

#define DQ_PC104_READBUS (1)

◆ DQ_PC104_READMEM

#define DQ_PC104_READMEM (3)

◆ DQ_PC104_READSTATUS

#define DQ_PC104_READSTATUS (6)

◆ DQ_PC104_REFRESH

#define DQ_PC104_REFRESH (1L<<6)

◆ DQ_PC104_SCRIPT_MASK

#define DQ_PC104_SCRIPT_MASK (0xfffffff)

◆ DQ_PC104_SCRIPTDATA_MASK

#define DQ_PC104_SCRIPTDATA_MASK (0xffff0fff)

◆ DQ_PC104_SET_CUSTOM_PARAM

#define DQ_PC104_SET_CUSTOM_PARAM (2)

◆ DQ_PC104_SET_CUSTOM_PROC

#define DQ_PC104_SET_CUSTOM_PROC (1)

◆ DQ_PC104_SHBE

#define DQ_PC104_SHBE (1L<<12)

◆ DQ_PC104_SIMA_ACK

#define DQ_PC104_SIMA_ACK (0x7ffe)

◆ DQ_PC104_SIMA_BCM

#define DQ_PC104_SIMA_BCM (0x444)

◆ DQ_PC104_SIMA_CLO_ENTRIES

#define DQ_PC104_SIMA_CLO_ENTRIES (32)

◆ DQ_PC104_SIMA_DCNT

#define DQ_PC104_SIMA_DCNT (0x446)

◆ DQ_PC104_SIMA_ECNT

#define DQ_PC104_SIMA_ECNT (0x448)

◆ DQ_PC104_SIMA_ERRVLD

#define DQ_PC104_SIMA_ERRVLD (0x450)

◆ DQ_PC104_SIMA_FRAME

#define DQ_PC104_SIMA_FRAME (0x440)

◆ DQ_PC104_SIMA_FRMSZ_RD

#define DQ_PC104_SIMA_FRMSZ_RD (1)

◆ DQ_PC104_SIMA_FRMSZ_WR

#define DQ_PC104_SIMA_FRMSZ_WR (2)

◆ DQ_PC104_SIMA_MCTRL

#define DQ_PC104_SIMA_MCTRL (0x900)

◆ DQ_PC104_SIMA_MCTRL_STAT

#define DQ_PC104_SIMA_MCTRL_STAT (0x90E)

◆ DQ_PC104_SIMA_MSLOT

#define DQ_PC104_SIMA_MSLOT (0x442)

◆ DQ_PC104_SMEMR

#define DQ_PC104_SMEMR (1L<<2)

◆ DQ_PC104_SMEMW

#define DQ_PC104_SMEMW (1L<<3)

◆ DQ_PC104_SPACESIZE_MASK

#define DQ_PC104_SPACESIZE_MASK (DQ_PC104_CDO_ACC8BIT|DQ_PC104_CDO_MEMSPCSEL)

◆ DQ_PC104_STS

#define DQ_PC104_STS (0x2004)

◆ DQ_PC104_STS_BRD

#define DQ_PC104_STS_BRD (1L<<4)

◆ DQ_PC104_STS_BTB

#define DQ_PC104_STS_BTB (1L<<31)

◆ DQ_PC104_STS_BWD

#define DQ_PC104_STS_BWD (1L<<5)

◆ DQ_PC104_STS_IO16TO

#define DQ_PC104_STS_IO16TO (1L<<17)

◆ DQ_PC104_STS_IOCHK

#define DQ_PC104_STS_IOCHK (1L<<30)

◆ DQ_PC104_STS_IORD

#define DQ_PC104_STS_IORD (1L<<2)

◆ DQ_PC104_STS_IOWD

#define DQ_PC104_STS_IOWD (1L<<3)

◆ DQ_PC104_STS_IRQ10S

#define DQ_PC104_STS_IRQ10S (1L<<11)

◆ DQ_PC104_STS_IRQ11S

#define DQ_PC104_STS_IRQ11S (1L<<12)

◆ DQ_PC104_STS_IRQ12S

#define DQ_PC104_STS_IRQ12S (1L<<13)

◆ DQ_PC104_STS_IRQ14_15S

#define DQ_PC104_STS_IRQ14_15S (1L<<14)

◆ DQ_PC104_STS_IRQ3S

#define DQ_PC104_STS_IRQ3S (1L<<6)

◆ DQ_PC104_STS_IRQ3S_SH

#define DQ_PC104_STS_IRQ3S_SH (6)

◆ DQ_PC104_STS_IRQ4S

#define DQ_PC104_STS_IRQ4S (1L<<7)

◆ DQ_PC104_STS_IRQ5S

#define DQ_PC104_STS_IRQ5S (1L<<8)

◆ DQ_PC104_STS_IRQ6S

#define DQ_PC104_STS_IRQ6S (1L<<9)

◆ DQ_PC104_STS_IRQ7_9S

#define DQ_PC104_STS_IRQ7_9S (1L<<10)

◆ DQ_PC104_STS_M16TO

#define DQ_PC104_STS_M16TO (1L<<16)

◆ DQ_PC104_STS_MIO8TO

#define DQ_PC104_STS_MIO8TO (1L<<15)

◆ DQ_PC104_STS_MRD

#define DQ_PC104_STS_MRD (1L<<0)

◆ DQ_PC104_STS_MWD

#define DQ_PC104_STS_MWD (1L<<1)

◆ DQ_PC104_STS_STAE

#define DQ_PC104_STS_STAE (1L<<19)

◆ DQ_PC104_STS_STTO

#define DQ_PC104_STS_STTO (1L<<18)

◆ DQ_PC104_TC

#define DQ_PC104_TC (1L<<7)

◆ DQ_PC104_VMAP_SIMA_BUFF

#define DQ_PC104_VMAP_SIMA_BUFF ( CHAN ) (((CHAN)&0xff) - 0x10)

◆ DQ_PC104_VMAP_SIMA_CARD

#define DQ_PC104_VMAP_SIMA_CARD ( CHAN ) ((CHAN)>>15)

◆ DQ_PC104_VMAP_SIMA_CTRL

#define DQ_PC104_VMAP_SIMA_CTRL (0x0)

◆ DQ_PC104_VMAP_SIMA_GET_BRD

#define DQ_PC104_VMAP_SIMA_GET_BRD ( N ) (((N)&0x8000)>>15)

◆ DQ_PC104_VMAP_SIMA_R90E

#define DQ_PC104_VMAP_SIMA_R90E (0x40)

◆ DQ_PC104_VMAP_SIMA_SLOT

#define DQ_PC104_VMAP_SIMA_SLOT	(	BRD,
		SLOT
	)	((((BRD)&1)<<15)\|(((SLOT)&0xFF)+0x10))

◆ DQ_PC104_VMAP_SIMA_STS

#define DQ_PC104_VMAP_SIMA_STS (0x0)

◆ DQ_PC104_WE

#define DQ_PC104_WE (1L<<1)

◆ DQ_PC104_WRITEBUS

#define DQ_PC104_WRITEBUS (2)

◆ DQ_PC104_WRITEMEM

#define DQ_PC104_WRITEMEM (4)

◆ DQ_PC104_WRITESCRIPT

#define DQ_PC104_WRITESCRIPT (5)

◆ DQ_PC91X_ADC_EOC

#define DQ_PC91X_ADC_EOC (1L<<18)

◆ DQ_PC91X_ADC_MSB

#define DQ_PC91X_ADC_MSB (1L<<15)

◆ DQ_PC91X_ADC_SIG

#define DQ_PC91X_ADC_SIG (1L<<16)

◆ DQ_PC91X_AI_SPAN

#define DQ_PC91X_AI_SPAN (2.5)

◆ DQ_PC91X_CH_DCDC_INPUT_V

#define DQ_PC91X_CH_DCDC_INPUT_V (3)

◆ DQ_PC91X_CH_EXT_V

#define DQ_PC91X_CH_EXT_V (0)

◆ DQ_PC91X_CH_INPUT_I

#define DQ_PC91X_CH_INPUT_I (1)

◆ DQ_PC91X_CH_INT_V

#define DQ_PC91X_CH_INT_V (2)

◆ DQ_PC91X_CH_THERM

#define DQ_PC91X_CH_THERM (4)

◆ DQ_PC91X_DEF_GAIN_CAL

#define DQ_PC91X_DEF_GAIN_CAL (0x8000)

◆ DQ_PC91X_DEF_OFFSET_CAL

#define DQ_PC91X_DEF_OFFSET_CAL (0)

◆ DQ_PC91X_I_SCALER_EXT

#define DQ_PC91X_I_SCALER_EXT (83.5)

◆ DQ_PC91X_I_SCALER_INT

#define DQ_PC91X_I_SCALER_INT (61.5)

◆ DQ_PC91X_I_SCALER_TH

#define DQ_PC91X_I_SCALER_TH (165.0)

◆ DQ_PC91X_MAX_GAIN_CAL_DEV

#define DQ_PC91X_MAX_GAIN_CAL_DEV (3277)

◆ DQ_PC91X_MAX_OFFSET_CAL_DEV

#define DQ_PC91X_MAX_OFFSET_CAL_DEV (0x1000)

◆ DQ_PC91X_MIN_ADC_WAIT

#define DQ_PC91X_MIN_ADC_WAIT (160)

◆ DQ_PC91X_OFFSET

#define DQ_PC91X_OFFSET (DQ_PC91X_AI_SPAN/2.0)

◆ DQ_PC91X_STEP

#define DQ_PC91X_STEP (DQ_PC91X_AI_SPAN/(double)0xffff)

◆ DQ_PC91X_T_OFFSET

#define DQ_PC91X_T_OFFSET (273.0)

◆ DQ_PC91X_T_SLOPE

#define DQ_PC91X_T_SLOPE (2.45)

◆ DQ_PC91X_V_SCALER

#define DQ_PC91X_V_SCALER (42.667)

◆ DQ_PC_91x_BASE

#define DQ_PC_91x_BASE (66000000)

◆ DQ_PC_91X_CFG_AUTO

#define DQ_PC_91X_CFG_AUTO (1L<<27)

◆ DQ_PC_91X_CFG_EJIO

#define DQ_PC_91X_CFG_EJIO (1L<<31)

◆ DQ_PC_91x_CL_MASK

#define DQ_PC_91x_CL_MASK (0x7)

◆ DQ_PC_91x_ICHAN

#define DQ_PC_91x_ICHAN (5)

◆ DQ_PC_91x_INFOSZ

#define DQ_PC_91x_INFOSZ (DQ_MAX_INFO_SIZE)

◆ DQ_PC_91x_OCHAN

#define DQ_PC_91x_OCHAN (2)

◆ DQ_PL601_CHNLNUM_MASK

#define DQ_PL601_CHNLNUM_MASK (0x0f)

◆ DQ_PL601_CHNLTYPE_CR0

#define DQ_PL601_CHNLTYPE_CR0 (0x40)

◆ DQ_PL601_CHNLTYPE_CR1

#define DQ_PL601_CHNLTYPE_CR1 (0x50)

◆ DQ_PL601_CHNLTYPE_CRH

#define DQ_PL601_CHNLTYPE_CRH (0x20)

◆ DQ_PL601_CHNLTYPE_CRL

#define DQ_PL601_CHNLTYPE_CRL (0x30)

◆ DQ_PL601_CHNLTYPE_MASK

#define DQ_PL601_CHNLTYPE_MASK (0xf0)

◆ DQ_PL601_CHNLTYPE_STATUS

#define DQ_PL601_CHNLTYPE_STATUS (0x10)

◆ DQ_PL601_SMAUTO

#define DQ_PL601_SMAUTO (0L)

◆ DQ_PL601_SMHARD

#define DQ_PL601_SMHARD (1L)

◆ DQ_PL601_SMSOFT

#define DQ_PL601_SMSOFT (2L)

◆ DQ_PL601_SW16

#define DQ_PL601_SW16 (2L)

◆ DQ_PL601_SW32

#define DQ_PL601_SW32 (4L)

◆ DQ_PL601_SW8

#define DQ_PL601_SW8 (1L)

◆ DQ_PL604_CHNLMASK

#define DQ_PL604_CHNLMASK (0xf0)

◆ DQ_PL604_MSGNORM

#define DQ_PL604_MSGNORM (0)

◆ DQ_PL801_CHNLMASK

#define DQ_PL801_CHNLMASK (0xf0)

◆ DQ_PL801_MSGNORM

#define DQ_PL801_MSGNORM (0)

◆ DQ_PL801_SW16

#define DQ_PL801_SW16 (2L)

◆ DQ_PL801_SW32

#define DQ_PL801_SW32 (4L)

◆ DQ_PL801_SW8

#define DQ_PL801_SW8 (1L)

◆ DQ_PL802_CHNLMASK

#define DQ_PL802_CHNLMASK (0xf0)

◆ DQ_PL802_MSGNORM

#define DQ_PL802_MSGNORM (0)

◆ DQ_PL802_SW16

#define DQ_PL802_SW16 (2L)

◆ DQ_PL802_SW32

#define DQ_PL802_SW32 (4L)

◆ DQ_PL802_SW8

#define DQ_PL802_SW8 (1L)

◆ DQ_PL_601_BASE

#define DQ_PL_601_BASE (BUS_FREQUENCY)

◆ DQ_PL_601_BASE_DOUBLE

#define DQ_PL_601_BASE_DOUBLE (BUS_FREQUENCY<<1)

◆ DQ_PL_601_CHAN

#define DQ_PL_601_CHAN (8)

◆ DQ_PL_601_CHANSVC

#define DQ_PL_601_CHANSVC (8)

◆ DQ_PL_601_FIFO_GET_DATA

#define DQ_PL_601_FIFO_GET_DATA (DQ_FIFO_GET_DATA)

◆ DQ_PL_601_INFOSZ

#define DQ_PL_601_INFOSZ (DQ_MAX_INFO_SIZE)

◆ DQ_PL_601_MAXCLFRQ

#define DQ_PL_601_MAXCLFRQ (50000)

◆ DQ_PL_601_MAXCVFRQ

#define DQ_PL_601_MAXCVFRQ (50000)

◆ DQ_PL_601_MODECONT

#define DQ_PL_601_MODECONT (3L << 16)

◆ DQ_PL_601_MODEFIFO

#define DQ_PL_601_MODEFIFO (2L << 16)

◆ DQ_PL_601_MODESCAN

#define DQ_PL_601_MODESCAN (0L << 16)

◆ DQ_PL_601_NAMELEN

#define DQ_PL_601_NAMELEN 16

◆ DQ_PL_601_TSCOPY

#define DQ_PL_601_TSCOPY (1L << 18)

◆ DQ_PL_604_BASE

#define DQ_PL_604_BASE BUS_FREQUENCY

◆ DQ_PL_604_CHAN

#define DQ_PL_604_CHAN 4

◆ DQ_PL_604_CHANSVC

#define DQ_PL_604_CHANSVC 4

◆ DQ_PL_604_INFOSZ

#define DQ_PL_604_INFOSZ DQ_MAX_INFO_SIZE

◆ DQ_PL_604_MAXCLFRQ

#define DQ_PL_604_MAXCLFRQ 50000

◆ DQ_PL_604_MAXCVFRQ

#define DQ_PL_604_MAXCVFRQ 50000

◆ DQ_PL_604_NAMELEN

#define DQ_PL_604_NAMELEN 16

◆ DQ_PL_604_PLL

#define DQ_PL_604_PLL 16500000

◆ DQ_PL_801_BASE

#define DQ_PL_801_BASE BUS_FREQUENCY

◆ DQ_PL_801_CHAN

#define DQ_PL_801_CHAN 4

◆ DQ_PL_801_CHANSVC

#define DQ_PL_801_CHANSVC 4

◆ DQ_PL_801_FIFO_GET_DATA

#define DQ_PL_801_FIFO_GET_DATA DQ_FIFO_GET_DATA

◆ DQ_PL_801_INFOSZ

#define DQ_PL_801_INFOSZ DQ_MAX_INFO_SIZE

◆ DQ_PL_801_MAXCLFRQ

#define DQ_PL_801_MAXCLFRQ 50000

◆ DQ_PL_801_MAXCVFRQ

#define DQ_PL_801_MAXCVFRQ 50000

◆ DQ_PL_801_MODECONT

#define DQ_PL_801_MODECONT (3L << 16)

◆ DQ_PL_801_MODEFIFO

#define DQ_PL_801_MODEFIFO (2L << 16)

◆ DQ_PL_801_MODESCAN

#define DQ_PL_801_MODESCAN (0L << 16)

◆ DQ_PL_801_NAMELEN

#define DQ_PL_801_NAMELEN 16

◆ DQ_PL_801_TSCOPY

#define DQ_PL_801_TSCOPY (1L << 18)

◆ DQ_PL_802_BASE

#define DQ_PL_802_BASE BUS_FREQUENCY

◆ DQ_PL_802_CHAN

#define DQ_PL_802_CHAN 4

◆ DQ_PL_802_CHANSVC

#define DQ_PL_802_CHANSVC 4

◆ DQ_PL_802_FIFO_GET_DATA

#define DQ_PL_802_FIFO_GET_DATA DQ_FIFO_GET_DATA

◆ DQ_PL_802_INFOSZ

#define DQ_PL_802_INFOSZ DQ_MAX_INFO_SIZE

◆ DQ_PL_802_MAXCLFRQ

#define DQ_PL_802_MAXCLFRQ 50000

◆ DQ_PL_802_MAXCVFRQ

#define DQ_PL_802_MAXCVFRQ 50000

◆ DQ_PL_802_MODECONT

#define DQ_PL_802_MODECONT (3L << 16)

◆ DQ_PL_802_MODEFIFO

#define DQ_PL_802_MODEFIFO (2L << 16)

◆ DQ_PL_802_MODESCAN

#define DQ_PL_802_MODESCAN (0L << 16)

◆ DQ_PL_802_NAMELEN

#define DQ_PL_802_NAMELEN 16

◆ DQ_PL_802_TSCOPY

#define DQ_PL_802_TSCOPY (1L << 18)

◆ DQ_PLGVT1

#define DQ_PLGVT1 0xBABAFACB /* DqVT first or not last packet id */

◆ DQ_PLGVTL

#define DQ_PLGVTL 0xBABAFACC /* DqVT last or only packet id */

◆ DQ_PPC8347_FLASH_ADDRESS

#define DQ_PPC8347_FLASH_ADDRESS (0xFE000000)

◆ DQ_PPC8347_FLASH_FIRMWARE_OFFSET

#define DQ_PPC8347_FLASH_FIRMWARE_OFFSET (0x01800000)

◆ DQ_PPC8347_FLASH_SIZE

#define DQ_PPC8347_FLASH_SIZE (0x02000000)

◆ DQ_PPC8347_UPUSER_SEC

#define DQ_PPC8347_UPUSER_SEC (192) /* start user sector MPC8347 */

◆ DQ_PPC_FLASH_ADDRESS

#define DQ_PPC_FLASH_ADDRESS (0xFFC00000)

◆ DQ_PPC_FLASH_FIRMWARE_OFFSET

#define DQ_PPC_FLASH_FIRMWARE_OFFSET (0x00010000)

◆ DQ_PPC_FLASH_SIZE

#define DQ_PPC_FLASH_SIZE (0x00400000)

◆ DQ_PPC_UPUSER_SEC

#define DQ_PPC_UPUSER_SEC (8) /* start user sector PPC5200 */

◆ DQ_PROLOG

#define DQ_PROLOG 0xBABAFACA /* DqTS id */

◆ DQ_READCOMM

#define DQ_READCOMM (1)

◆ DQ_SETPASS_CLEAR

#define DQ_SETPASS_CLEAR (1L << 4)

◆ DQ_SETPASS_SETSU

#define DQ_SETPASS_SETSU (1L << 2)

◆ DQ_SETPASS_SETUSR

#define DQ_SETPASS_SETUSR (1L << 3)

◆ DQ_SETPASS_SUPASS

#define DQ_SETPASS_SUPASS (1L << 0)

◆ DQ_SETPASS_USRPASS

#define DQ_SETPASS_USRPASS (1L << 1)

◆ DQ_SIMA_RDBLK0

#define DQ_SIMA_RDBLK0 (0x8000)

◆ DQ_SIMA_RDBLK0i

#define DQ_SIMA_RDBLK0i (DQ_SIMA_RDBLK0>>2)

◆ DQ_SIMA_RDBLK1

#define DQ_SIMA_RDBLK1 (0x9000)

◆ DQ_SIMA_RDBLK1i

#define DQ_SIMA_RDBLK1i (DQ_SIMA_RDBLK1>>2)

◆ DQ_SIMA_RX_BUFSEL

#define DQ_SIMA_RX_BUFSEL (0)

◆ DQ_SIMA_TX_BUFSEL

#define DQ_SIMA_TX_BUFSEL (1)

◆ DQ_SIMA_WRBLK0

#define DQ_SIMA_WRBLK0 (0xA000)

◆ DQ_SIMA_WRBLK0i

#define DQ_SIMA_WRBLK0i (DQ_SIMA_WRBLK0>>2)

◆ DQ_SIMA_WRBLK1

#define DQ_SIMA_WRBLK1 (0xB000)

◆ DQ_SIMA_WRBLK1i

#define DQ_SIMA_WRBLK1i (DQ_SIMA_WRBLK1>>2)

◆ DQ_SIMA_WRRDBLK

#define DQ_SIMA_WRRDBLK	(	N,
		W
	)	((((N)>0)?0x8000:0x9000)+(((W)>0)?0x2000:0))

◆ DQ_SIMA_WRRDBLKi

#define DQ_SIMA_WRRDBLKi	(	N,
		W
	)	(((DQ_SIMA_WRRDBLK((N),(W))-0x8000)>>2)&0x1fff)

◆ DQ_SL501_BAUD_1000000

#define DQ_SL501_BAUD_1000000 (14L)

◆ DQ_SL501_BAUD_115200

#define DQ_SL501_BAUD_115200 (10L)

◆ DQ_SL501_BAUD_1200

#define DQ_SL501_BAUD_1200 (3L)

◆ DQ_SL501_BAUD_128000

#define DQ_SL501_BAUD_128000 (11L)

◆ DQ_SL501_BAUD_19200

#define DQ_SL501_BAUD_19200 (7L)

◆ DQ_SL501_BAUD_2400

#define DQ_SL501_BAUD_2400 (4L)

◆ DQ_SL501_BAUD_250000

#define DQ_SL501_BAUD_250000 (12L)

◆ DQ_SL501_BAUD_256000

#define DQ_SL501_BAUD_256000 (13L)

◆ DQ_SL501_BAUD_300

#define DQ_SL501_BAUD_300 (1L)

◆ DQ_SL501_BAUD_38400

#define DQ_SL501_BAUD_38400 (8L)

◆ DQ_SL501_BAUD_4800

#define DQ_SL501_BAUD_4800 (5L)

◆ DQ_SL501_BAUD_56000

#define DQ_SL501_BAUD_56000 (9L)

◆ DQ_SL501_BAUD_57600

#define DQ_SL501_BAUD_57600 (0L)

◆ DQ_SL501_BAUD_600

#define DQ_SL501_BAUD_600 (2L)

◆ DQ_SL501_BAUD_9600

#define DQ_SL501_BAUD_9600 (6L)

◆ DQ_SL501_BAUD_CUST

#define DQ_SL501_BAUD_CUST (15L)

◆ DQ_SL501_BAUD_DEFAULT

#define DQ_SL501_BAUD_DEFAULT (DQ_SL501_BAUD_57600)

◆ DQ_SL501_BAUD_PLL_SH

#define DQ_SL501_BAUD_PLL_SH (21 + DQ_CL_OFS)

◆ DQ_SL501_BAUD_SH

#define DQ_SL501_BAUD_SH (12 + DQ_CL_OFS)

◆ DQ_SL501_BREAK

#define DQ_SL501_BREAK (1L)

◆ DQ_SL501_BREAK_SH

#define DQ_SL501_BREAK_SH (17 + DQ_CL_OFS)

◆ DQ_SL501_DELAYMODE_DISABLED

#define DQ_SL501_DELAYMODE_DISABLED (0)

◆ DQ_SL501_DELAYMODE_INTERNAL

#define DQ_SL501_DELAYMODE_INTERNAL (1)

◆ DQ_SL501_DELAYMODE_SYNC02

#define DQ_SL501_DELAYMODE_SYNC02 (3)

◆ DQ_SL501_DELAYMODE_TMR01

#define DQ_SL501_DELAYMODE_TMR01 (2)

◆ DQ_SL501_DTS

#define DQ_SL501_DTS (1L)

◆ DQ_SL501_DTS_SH

#define DQ_SL501_DTS_SH (11 + DQ_CL_OFS)

◆ DQ_SL501_ERROR

#define DQ_SL501_ERROR (1L)

◆ DQ_SL501_ERROR_SH

#define DQ_SL501_ERROR_SH (16 + DQ_CL_OFS)

◆ DQ_SL501_FRAMEDELAY_DISABLED

#define DQ_SL501_FRAMEDELAY_DISABLED (0)

◆ DQ_SL501_FRAMEDELAY_FIXEDLEN

#define DQ_SL501_FRAMEDELAY_FIXEDLEN (1)

◆ DQ_SL501_FRAMEDELAY_REPEAT

#define DQ_SL501_FRAMEDELAY_REPEAT (0x10)

◆ DQ_SL501_FRAMEDELAY_VMAP_LEN

#define DQ_SL501_FRAMEDELAY_VMAP_LEN (2)

◆ DQ_SL501_FRAMEDELAY_ZERO_CHAR

#define DQ_SL501_FRAMEDELAY_ZERO_CHAR (3)

◆ DQ_SL501_FSTE_SH

#define DQ_SL501_FSTE_SH (18 + DQ_CL_OFS)

◆ DQ_SL501_MIXED_PARITY

#define DQ_SL501_MIXED_PARITY (1L<<9)

◆ DQ_SL501_MODE_232

#define DQ_SL501_MODE_232 (0L)

◆ DQ_SL501_MODE_485F

#define DQ_SL501_MODE_485F (1L)

◆ DQ_SL501_MODE_485H

#define DQ_SL501_MODE_485H (2L)

◆ DQ_SL501_MODE_SH

#define DQ_SL501_MODE_SH (0 + DQ_CL_OFS)

◆ DQ_SL501_MSG_BREAK

#define DQ_SL501_MSG_BREAK (1)

◆ DQ_SL501_MSG_ERR_FRM

#define DQ_SL501_MSG_ERR_FRM (2)

◆ DQ_SL501_MSG_ERR_PAR

#define DQ_SL501_MSG_ERR_PAR (3)

◆ DQ_SL501_MSG_ERR_TO

#define DQ_SL501_MSG_ERR_TO (4)

◆ DQ_SL501_MSG_NORM

#define DQ_SL501_MSG_NORM (0)

◆ DQ_SL501_OPER_LOOP

#define DQ_SL501_OPER_LOOP (1L)

◆ DQ_SL501_OPER_NORM

#define DQ_SL501_OPER_NORM (0L)

◆ DQ_SL501_OPER_SH

#define DQ_SL501_OPER_SH (9 + DQ_CL_OFS)

◆ DQ_SL501_PARITY9

#define DQ_SL501_PARITY9 (1L<<8)

◆ DQ_SL501_PARITY9_DISABLE

#define DQ_SL501_PARITY9_DISABLE (DQ_SL501_FRAMEDELAY_DISABLED)

◆ DQ_SL501_PARITY9_ENABLED

#define DQ_SL501_PARITY9_ENABLED (4)

◆ DQ_SL501_PARITY_EVEN

#define DQ_SL501_PARITY_EVEN (1L)

◆ DQ_SL501_PARITY_MARK

#define DQ_SL501_PARITY_MARK (4L)

◆ DQ_SL501_PARITY_NONE

#define DQ_SL501_PARITY_NONE (0L)

◆ DQ_SL501_PARITY_ODD

#define DQ_SL501_PARITY_ODD (2L)

◆ DQ_SL501_PARITY_SH

#define DQ_SL501_PARITY_SH (2 + DQ_CL_OFS)

◆ DQ_SL501_PARITY_SPACE

#define DQ_SL501_PARITY_SPACE (3L)

◆ DQ_SL501_RTS

#define DQ_SL501_RTS (1L)

◆ DQ_SL501_RTS_SH

#define DQ_SL501_RTS_SH (10 + DQ_CL_OFS)

◆ DQ_SL501_RXTE_SH

#define DQ_SL501_RXTE_SH (19 + DQ_CL_OFS)

◆ DQ_SL501_STOP_1

#define DQ_SL501_STOP_1 (0L)

◆ DQ_SL501_STOP_1_5

#define DQ_SL501_STOP_1_5 (1L)

◆ DQ_SL501_STOP_2

#define DQ_SL501_STOP_2 (2L)

◆ DQ_SL501_STOP_SH

#define DQ_SL501_STOP_SH (5 + DQ_CL_OFS)

◆ DQ_SL501_TERM_FS

#define DQ_SL501_TERM_FS (1L)

◆ DQ_SL501_TERM_RX

#define DQ_SL501_TERM_RX (1L)

◆ DQ_SL501_TERM_TX

#define DQ_SL501_TERM_TX (1L)

◆ DQ_SL501_TXTE_SH

#define DQ_SL501_TXTE_SH (20 + DQ_CL_OFS)

◆ DQ_SL501_VMAP_STAT

#define DQ_SL501_VMAP_STAT (1L<<9)

◆ DQ_SL501_WIDTH_5

#define DQ_SL501_WIDTH_5 (3L)

◆ DQ_SL501_WIDTH_6

#define DQ_SL501_WIDTH_6 (2L)

◆ DQ_SL501_WIDTH_7

#define DQ_SL501_WIDTH_7 (1L)

◆ DQ_SL501_WIDTH_8

#define DQ_SL501_WIDTH_8 (0L)

◆ DQ_SL501_WIDTH_SH

#define DQ_SL501_WIDTH_SH (7 + DQ_CL_OFS)

◆ DQ_SL553_ABS_MEM_ADDR

#define DQ_SL553_ABS_MEM_ADDR	(	MODE,
		BLK,
		CH,
		RT,
		SA
	)	((((MODE)&1)<<18)\|(((BLK)&1)<<17)\|(((CH)&1)<<16)\|(((RT)&0x1f)<<11)\|(((SA)&0x1f)<<6))

◆ DQ_SL553_BC_BC_STATUS

#define DQ_SL553_BC_BC_STATUS (3L<<12)

◆ DQ_SL553_BC_BUSMON

#define DQ_SL553_BC_BUSMON (4L<<12)

◆ DQ_SL553_BC_DATA

#define DQ_SL553_BC_DATA (1L<<12)

◆ DQ_SL553_BC_GET_CHAN

#define DQ_SL553_BC_GET_CHAN ( N ) (((N)>>12)&0x1)

◆ DQ_SL553_BC_GET_IDX

#define DQ_SL553_BC_GET_IDX ( N ) (((N))&0xff)

◆ DQ_SL553_BC_GET_MN

#define DQ_SL553_BC_GET_MN ( N ) (((N)>>8)&0xf)

◆ DQ_SL553_BC_GET_MNBLK

#define DQ_SL553_BC_GET_MNBLK ( N ) (((N)>>7)&0x1)

◆ DQ_SL553_BC_GET_TYPE

#define DQ_SL553_BC_GET_TYPE ( N ) (((N)>>13)&0x7)

◆ DQ_SL553_BC_MJ_DESC

#define DQ_SL553_BC_MJ_DESC (6L<<12)

◆ DQ_SL553_BC_MN_DESC

#define DQ_SL553_BC_MN_DESC (5L<<12)

◆ DQ_SL553_BC_STATUS

#define DQ_SL553_BC_STATUS (2L<<12)

◆ DQ_SL553_BC_STATUS_BC

#define DQ_SL553_BC_STATUS_BC 1

◆ DQ_SL553_BC_STATUS_BCPOS

#define DQ_SL553_BC_STATUS_BCPOS 6

◆ DQ_SL553_BC_STATUS_ERR

#define DQ_SL553_BC_STATUS_ERR 4

◆ DQ_SL553_BC_STATUS_ISRC

#define DQ_SL553_BC_STATUS_ISRC 3

◆ DQ_SL553_BC_STATUS_MJ

#define DQ_SL553_BC_STATUS_MJ 2

◆ DQ_SL553_BC_STATUS_PORT

#define DQ_SL553_BC_STATUS_PORT 5

◆ DQ_SL553_BC_STATUS_RQ

#define DQ_SL553_BC_STATUS_RQ	(	STS_TYPE,
		INDEX
	)	((DQ_SL553_BC_STATUS)\|(((STS_TYPE)&0xf)<<8)\|((INDEX)&0xff))

◆ DQ_SL553_BC_TYPE

#define DQ_SL553_BC_TYPE (0x7<<12)

◆ DQ_SL553_BC_VMAP

#define DQ_SL553_BC_VMAP	(	CH,
		TYPE,
		MN,
		BLK,
		IDX
	)	((((TYPE)&0x7)<<13)\|(((CH)&1)<<12)\|(((MN)&0xf)<<8)\|(((BLK)&0x1)<<7)\|((IDX)&0x7f))

◆ DQ_SL553_BC_VMAP_BUSMON

#define DQ_SL553_BC_VMAP_BUSMON (4L)

◆ DQ_SL553_BC_VMAP_CONTROL

#define DQ_SL553_BC_VMAP_CONTROL (2L)

◆ DQ_SL553_BC_VMAP_DATA

#define DQ_SL553_BC_VMAP_DATA (1L)

◆ DQ_SL553_BC_VMAP_MJ_DESC

#define DQ_SL553_BC_VMAP_MJ_DESC (6L)

◆ DQ_SL553_BC_VMAP_MN_DESC

#define DQ_SL553_BC_VMAP_MN_DESC (5L)

◆ DQ_SL553_BC_VMAP_STATUS

#define DQ_SL553_BC_VMAP_STATUS (2L)

◆ DQ_SL553_MEMVAL_RT

#define DQ_SL553_MEMVAL_RT (SL553_MEMVAL_TXEN|SL553_MEMVAL_RXEN)

◆ DQ_SL553_RTS_CFG0_BSRD

#define DQ_SL553_RTS_CFG0_BSRD (1L<<2)

◆ DQ_SL553_RTS_CFG0_BSY

#define DQ_SL553_RTS_CFG0_BSY (1L<<3)

◆ DQ_SL553_RTS_CFG0_DBCE

#define DQ_SL553_RTS_CFG0_DBCE (1L<<0)

◆ DQ_SL553_RTS_CFG0_RSTD

#define DQ_SL553_RTS_CFG0_RSTD (1L<<6)

◆ DQ_SL553_RTS_CFG0_SF

#define DQ_SL553_RTS_CFG0_SF (1L<<4)

◆ DQ_SL553_RTS_CFG0_SR

#define DQ_SL553_RTS_CFG0_SR (1L<<1)

◆ DQ_SL553_RTS_CFG0_TF

#define DQ_SL553_RTS_CFG0_TF (1L<<5)

◆ DQ_SL553_RTS_CFG1

#define DQ_SL553_RTS_CFG1	(	HI,
		LO
	)	(((HI)<<16)\|((LOW)&0xffff))

◆ DQ_SS0IN

#define DQ_SS0IN (0)

◆ DQ_SS0OUT

#define DQ_SS0OUT (1)

◆ DQ_SS1IN

#define DQ_SS1IN (2)

◆ DQ_SS1OUT

#define DQ_SS1OUT (3)

◆ DQ_SS2IN

#define DQ_SS2IN (4)

◆ DQ_SS2OUT

#define DQ_SS2OUT (5)

◆ DQ_SS3IN

#define DQ_SS3IN (6)

◆ DQ_SS3OUT

#define DQ_SS3OUT (7)

◆ DQ_SS_DIR

#define DQ_SS_DIR	(	ss,
		dir
	)	(((ss) << 1) \| (dir))

◆ DQ_STR_BUSY

#define DQ_STR_BUSY 30

◆ DQ_STR_CR0GE

#define DQ_STR_CR0GE 28

◆ DQ_STR_CR0L

#define DQ_STR_CR0L 29

◆ DQ_STR_CR1

#define DQ_STR_CR1 27

◆ DQ_STR_CRH

#define DQ_STR_CRH 16

◆ DQ_STR_CRL

#define DQ_STR_CRL 15

◆ DQ_STR_EN

#define DQ_STR_EN 31

◆ DQ_STR_GHL

#define DQ_STR_GHL 20

◆ DQ_STR_GLH

#define DQ_STR_GLH 19

◆ DQ_STR_GT

#define DQ_STR_GT 8

◆ DQ_STR_GT0

#define DQ_STR_GT0 25

◆ DQ_STR_GT1

#define DQ_STR_GT1 23

◆ DQ_STR_IFE

#define DQ_STR_IFE 14

◆ DQ_STR_IFF

#define DQ_STR_IFF 12

◆ DQ_STR_IFH

#define DQ_STR_IFH 13

◆ DQ_STR_IHL

#define DQ_STR_IHL 22

◆ DQ_STR_ILH

#define DQ_STR_ILH 21

◆ DQ_STR_IN0

#define DQ_STR_IN0 26

◆ DQ_STR_IN1

#define DQ_STR_IN1 24

◆ DQ_STR_IRQ

#define DQ_STR_IRQ 17

◆ DQ_STR_OFE

#define DQ_STR_OFE 11

◆ DQ_STR_OFF

#define DQ_STR_OFF 9

◆ DQ_STR_OFH

#define DQ_STR_OFH 10

◆ DQ_STR_OU

#define DQ_STR_OU 18

◆ DQ_SYNC_0

#define DQ_SYNC_0 (8)

◆ DQ_SYNC_1

#define DQ_SYNC_1 (16)

◆ DQ_SYNC_BUTTON

#define DQ_SYNC_BUTTON (32)

◆ DQ_SYNC_CLOCK

#define DQ_SYNC_CLOCK (0)

◆ DQ_SYNC_DEVN

#define DQ_SYNC_DEVN (0xD)

◆ DQ_SYNC_DRIVER

#define DQ_SYNC_DRIVER (2)

◆ DQ_SYNC_EXTERNAL

#define DQ_SYNC_EXTERNAL (4)

◆ DQ_SYNC_INPUT

#define DQ_SYNC_INPUT (1)

◆ DQ_SYNC_NOT_CONN

#define DQ_SYNC_NOT_CONN (0)

◆ DQ_SYNC_PLL

#define DQ_SYNC_PLL (1)

◆ DQ_SYNC_PLL_IMMEDIATE

#define DQ_SYNC_PLL_IMMEDIATE (3)

◆ DQ_SYNC_PPC

#define DQ_SYNC_PPC (0)

◆ DQ_SYNC_PPC2

#define DQ_SYNC_PPC2 (2)

◆ DQ_SYNC_TRIGGER

#define DQ_SYNC_TRIGGER (1)

◆ DQ_TBR_EN

#define DQ_TBR_EN 31

◆ DQ_TRIGGER_ONCE

#define DQ_TRIGGER_ONCE (1L<< 3)

◆ DQ_TRIGGER_RESET

#define DQ_TRIGGER_RESET (1L<< 2)

◆ DQ_TRIGGER_SET

#define DQ_TRIGGER_SET (1L<< 4)

◆ DQ_TRIGGER_SET_OR

#define DQ_TRIGGER_SET_OR (1L<< 5)

◆ DQ_TRIGGER_START

#define DQ_TRIGGER_START (1L<< 0)

◆ DQ_TRIGGER_STOP

#define DQ_TRIGGER_STOP (1L<< 1)

◆ DQ_UBOOT_ENTRY_ROM

#define DQ_UBOOT_ENTRY_ROM (0xFFF00100)

◆ DQ_UNUSED

#define DQ_UNUSED (0)

◆ DQ_UNUSED_FOR_THIS_CMD

#define DQ_UNUSED_FOR_THIS_CMD (0)

◆ DQ_VDD_DMAPID_IN

#define DQ_VDD_DMAPID_IN DQ_DMAP_LASTID_IN

◆ DQ_VDD_DMAPID_OUT

#define DQ_VDD_DMAPID_OUT DQ_DMAP_LASTID_OUT

◆ DQ_VDD_SS

#define DQ_VDD_SS (2)

◆ DQ_VMAP_FIFO_RQSIZE

#define DQ_VMAP_FIFO_RQSIZE (1L<<2)

◆ DQ_VMAP_FIFO_STATUS

#define DQ_VMAP_FIFO_STATUS (1L<<0)

◆ DQ_VMAP_SPEC_CHANNEL

#define DQ_VMAP_SPEC_CHANNEL (1L<<1)

◆ DQ_WD_CLEAR_DISABLED

#define DQ_WD_CLEAR_DISABLED (0)

◆ DQ_WD_CLEAR_ON_CONSOLE

#define DQ_WD_CLEAR_ON_CONSOLE (1L<<0)

◆ DQ_WD_CLEAR_ON_OSTASK

#define DQ_WD_CLEAR_ON_OSTASK (1L<<3)

◆ DQ_WD_CLEAR_ON_RECEIVE

#define DQ_WD_CLEAR_ON_RECEIVE (1L<<1)

◆ DQ_WD_CLEAR_ON_TRANSMIT

#define DQ_WD_CLEAR_ON_TRANSMIT (1L<<2)

◆ DQ_WD_CLEAR_RESET

#define DQ_WD_CLEAR_RESET (1L<<14)

◆ DQ_WD_CLEAR_STATUS

#define DQ_WD_CLEAR_STATUS (1L<<15)

◆ DQ_WRITECOMM

#define DQ_WRITECOMM (2)

◆ DqAdv401ConfigEvents_PARAMSZ

#define DqAdv401ConfigEvents_PARAMSZ 2

◆ DqAdv501ConfigEvents_PARAMSZ

#define DqAdv501ConfigEvents_PARAMSZ (7)

◆ DqAdv553ConfigEvents_PARAMSZ

#define DqAdv553ConfigEvents_PARAMSZ 7

◆ DqAdv601ConfigEvents_PARAMSZ

#define DqAdv601ConfigEvents_PARAMSZ 7

◆ DQAI211_ALARMCTRLSET

#define DQAI211_ALARMCTRLSET (1L<<4)

◆ DQAI211_ANAFILTSET

#define DQAI211_ANAFILTSET (1L<<7)

◆ DQAI211_AVGFACTORSET

#define DQAI211_AVGFACTORSET (1L<<4)

◆ DQAI211_BIASDRIVESET

#define DQAI211_BIASDRIVESET (1L<<0)

◆ DQAI211_BIASONOFFSET

#define DQAI211_BIASONOFFSET (1L<<1)

◆ DQAI211_CFGCH_DEFAULTSET

#define DQAI211_CFGCH_DEFAULTSET (1L<<11)

◆ DQAI211_CFGLAYER_DEFAULTSET

#define DQAI211_CFGLAYER_DEFAULTSET (1L<<0)

◆ DQAI211_CLKDIVSET

#define DQAI211_CLKDIVSET (1L<<2)

◆ DQAI211_CLKSRCSET

#define DQAI211_CLKSRCSET (1L<<1)

◆ DQAI211_COMPHISET

#define DQAI211_COMPHISET (1L<<2)

◆ DQAI211_COMPLOSET

#define DQAI211_COMPLOSET (1L<<3)

◆ DQAI211_DC_DC_OFF

#define DQAI211_DC_DC_OFF (1L<<7)

◆ DQAI211_DC_DC_ON

#define DQAI211_DC_DC_ON (1L<<6)

◆ DQAI211_DECFACTORSET

#define DQAI211_DECFACTORSET (1L<<8)

◆ DQAI211_FIR_BY_DECFACTOR

#define DQAI211_FIR_BY_DECFACTOR (1L<<5)

◆ DQAI211_FMTRSET

#define DQAI211_FMTRSET (1L<<3)

◆ DQAI211_HPFSET

#define DQAI211_HPFSET (1L<<5)

◆ DQAI211_MAINENBSET

#define DQAI211_MAINENBSET (1L<<8)

◆ DQAI211_OFFSETSET

#define DQAI211_OFFSETSET (1L<<6)

◆ DQAI211_SECENBSSET

#define DQAI211_SECENBSSET (1L<<9)

◆ DQAI211_SECNSET

#define DQAI211_SECNSET (1L<<10)

◆ DQAXMAP_CLEAR

#define DQAXMAP_CLEAR 1

◆ DQAXMAP_ENABLE

#define DQAXMAP_ENABLE 5

◆ DQAXMAP_NOREPLY

#define DQAXMAP_NOREPLY (1L<<31)

◆ DQAXMAP_SET_SLOT

#define DQAXMAP_SET_SLOT 4

◆ DQAXMAP_SET_TIMING

#define DQAXMAP_SET_TIMING 3

◆ DQAXMAP_TEST

#define DQAXMAP_TEST 2

◆ DQCFG_501

#define DQCFG_501	(	OPER,
		MODE,
		BAUD,
		WIDTH,
		STOP,
		PARITY
	)	(OPER << DQ_SL501_OPER_SH \| MODE << DQ_SL501_MODE_SH \| BAUD << DQ_SL501_BAUD_SH \| WIDTH << DQ_SL501_WIDTH_SH \| STOP << DQ_SL501_STOP_SH \| PARITY << DQ_SL501_PARITY_SH)

◆ DQDIO432_ADCSPDSET

#define DQDIO432_ADCSPDSET (1L<<2)

◆ DQDIO432_CFGSET

#define DQDIO432_CFGSET (1L<<0)

◆ DQDIO432_DISCFGSET

#define DQDIO432_DISCFGSET (1L<<1)

◆ DQDIO432_DISDIVSET

#define DQDIO432_DISDIVSET (1L<<6)

◆ DQDIO432_GETPARAM_GET

#define DQDIO432_GETPARAM_GET 0

◆ DQDIO432_GETPARAM_PWM

#define DQDIO432_GETPARAM_PWM 1

◆ DQDIO432_PORT0OCMSET

#define DQDIO432_PORT0OCMSET (1L<<3)

◆ DQDIO432_PORT0UCMSET

#define DQDIO432_PORT0UCMSET (1L<<4)

◆ DQDIO432_PWM_DISABLED

#define DQDIO432_PWM_DISABLED 0

◆ DQDIO432_PWM_MODE

#define DQDIO432_PWM_MODE 4

◆ DQDIO432_PWM_SOFTBOTH

#define DQDIO432_PWM_SOFTBOTH 3

◆ DQDIO432_PWM_SOFTSTART

#define DQDIO432_PWM_SOFTSTART 1

◆ DQDIO432_PWM_SOFTSTOP

#define DQDIO432_PWM_SOFTSTOP 2

◆ DQDIO432_RDCNTSET

#define DQDIO432_RDCNTSET (1L<<5)

◆ DQDIO432_SETPARAM_PWM

#define DQDIO432_SETPARAM_PWM 1

◆ DQDIO432_SETPARAM_SET

#define DQDIO432_SETPARAM_SET 0

◆ DQDIO448_ADCDLYSET

#define DQDIO448_ADCDLYSET (1L<<1)

◆ DQDIO448_CFGSET

#define DQDIO448_CFGSET (1L<<0)

◆ DQDIO448_GETPARAM_GET

#define DQDIO448_GETPARAM_GET 0

◆ DQDIO448_SETPARAM_SET

#define DQDIO448_SETPARAM_SET 0

◆ DQDIO462_ADCCFG0SET

#define DQDIO462_ADCCFG0SET (1L<<7)

◆ DQDIO462_ADCCFG1SET

#define DQDIO462_ADCCFG1SET (1L<<8)

◆ DQDIO462_ADCCFG2SET

#define DQDIO462_ADCCFG2SET (1L<<9)

◆ DQDIO462_ADCCFG3SET

#define DQDIO462_ADCCFG3SET (1L<<10)

◆ DQDIO462_ADCCFG4SET

#define DQDIO462_ADCCFG4SET (1L<<11)

◆ DQDIO462_CFGSET

#define DQDIO462_CFGSET (1L<<0)

◆ DQDIO462_DCDCCFGSET

#define DQDIO462_DCDCCFGSET (1L<<12)

◆ DQDIO462_DCDCXSET

#define DQDIO462_DCDCXSET (1L<<13)

◆ DQDIO462_GETPARAM_GET

#define DQDIO462_GETPARAM_GET (0x10)

◆ DQDIO462_PORTOCMSET

#define DQDIO462_PORTOCMSET (1L<<3)

◆ DQDIO462_PORTUCMSET

#define DQDIO462_PORTUCMSET (1L<<4)

◆ DQDIO462_RDCNTSET

#define DQDIO462_RDCNTSET (1L<<5)

◆ DQDIO462_SETPARAM_LIMITS

#define DQDIO462_SETPARAM_LIMITS (0x11)

◆ DQDIO462_SETPARAM_SET

#define DQDIO462_SETPARAM_SET (0x10)

◆ DQERR_ACCESS

#define DQERR_ACCESS 0x90070000 /* password is not cleared - access denied */

◆ DQERR_BITS

#define DQERR_BITS 0x0FFF0000 /* error/status bits or value extracted from here */

◆ DQERR_CLEAR_REPLY_MASK

#define DQERR_CLEAR_REPLY_MASK 0xffff; /* only packet length */

◆ DQERR_DIAG

#define DQERR_DIAG 0x90090000 /* Command not allowed on diagnostics port */

◆ DQERR_EXEC

#define DQERR_EXEC 0x90010000 /* exception on command execution */

◆ DQERR_GENFAIL

#define DQERR_GENFAIL 0xF0000000 /* general error/status mask */

◆ DQERR_INVREQ

#define DQERR_INVREQ 0x90050000 /* Invalid request number (RDFIFO) */

◆ DQERR_KEEP_PKT

#define DQERR_KEEP_PKT 0xA4000000 /* keep reply packet */

◆ DQERR_LOCKED

#define DQERR_LOCKED 0x90080000 /* cube is locked */

◆ DQERR_MASK

#define DQERR_MASK 0xFFFF0000

◆ DQERR_MOREDATA

#define DQERR_MOREDATA 0x90030000 /* more data is available */

◆ DQERR_MULTFAIL

#define DQERR_MULTFAIL 0x80000000 /* high bit - multiple bits indicate error/status */

◆ DQERR_NIBMASK

#define DQERR_NIBMASK 0xF0000000 /* general error/status mask */

◆ DQERR_NIMP

#define DQERR_NIMP 0x90060000 /* DQ not implemented or unknown command */

◆ DQERR_NOMORE

#define DQERR_NOMORE 0x90020000 /* no more data is available */

◆ DQERR_NOSEND

#define DQERR_NOSEND 0xA1000000 /* do not return packet */

◆ DQERR_OPS

#define DQERR_OPS 0x90070000 /* IOM is in operation state */

◆ DQERR_OVRFLW

#define DQERR_OVRFLW 0x80010000 /* Data extraction too slow - data overflow */

◆ DQERR_PARAM

#define DQERR_PARAM 0x90080000 /* Device cannot complete request with specified parameters */

◆ DQERR_PENDING

#define DQERR_PENDING 0xA2000000 /* do not return packet, do not free buffer */

◆ DQERR_RCV

#define DQERR_RCV 0x90090000 /* packet receive error */

◆ DQERR_SINGFAIL

#define DQERR_SINGFAIL 0x90000000 /* low bit in first nybble - single error/status */

◆ DQERR_SND

#define DQERR_SND 0x900A0000 /* packet send error */

◆ DQERR_STARTED

#define DQERR_STARTED 0x80020000 /* Start trigger is received */

◆ DQERR_STOPPED

#define DQERR_STOPPED 0x80040000 /* Stop trigger is received */

◆ DQERR_TOOOLD

#define DQERR_TOOOLD 0x90040000 /* request is too old (RDFIFO) */

◆ DQERR_WRONGID

#define DQERR_WRONGID 0x900A0000 /* Wrong VMap or DMap ID */

◆ DQEVENT553_CONTROL_BC

#define DQEVENT553_CONTROL_BC (0x100EL)

◆ DQEVENT553_READ_BCCB

#define DQEVENT553_READ_BCCB (0x100CL)

◆ DQEVENT553_READ_MD

#define DQEVENT553_READ_MD (0x100AL)

◆ DQEVENT553_READ_RT

#define DQEVENT553_READ_RT (0x1005L)

◆ DQEVENT553_STATUS_BC

#define DQEVENT553_STATUS_BC (0x100DL)

◆ DQEVENT553_WRITE_BCCB

#define DQEVENT553_WRITE_BCCB (0x100BL)

◆ DQEVENT553_WRITE_MD

#define DQEVENT553_WRITE_MD (0x1009L)

◆ DQEVENT553_WRITE_RT

#define DQEVENT553_WRITE_RT (0x1006L)

◆ DQEVENT601_CONTROL_CTR

#define DQEVENT601_CONTROL_CTR (0x1008L)

◆ DQEVENT601_READ_CTR

#define DQEVENT601_READ_CTR (0x1005L)

◆ DQEVENT601_STATUS_CTR

#define DQEVENT601_STATUS_CTR (0x1007L)

◆ DQEVENT601_WRITE_CTR

#define DQEVENT601_WRITE_CTR (0x1006L)

◆ DQEVENT_DISPATCH

#define DQEVENT_DISPATCH 2

◆ DQEVENT_ENABLE

#define DQEVENT_ENABLE 3

◆ DQEVENT_INTERNAL

#define DQEVENT_INTERNAL 4

◆ DQEVENT_LAYER

#define DQEVENT_LAYER 0x1000

◆ DQEVENT_NOREPLY

#define DQEVENT_NOREPLY (1L<<31)

◆ DQEVENT_SETUP

#define DQEVENT_SETUP 1

◆ DQFIFOHSZ

#define DQFIFOHSZ (4)

◆ DQHSZ

#define DQHSZ sizeof (DQPKT)

◆ DQIOCTL_AO333_CALIBRATE

#define DQIOCTL_AO333_CALIBRATE (0x08)

◆ DQIOCTL_AO333_CALIBRATE_RESULT

#define DQIOCTL_AO333_CALIBRATE_RESULT (0x09)

◆ DQIOCTL_CVTCHNL

#define DQIOCTL_CVTCHNL (1)

◆ DQIOCTL_DIO_READ_DI_ONLY

#define DQIOCTL_DIO_READ_DI_ONLY (0x0b)

◆ DQIOCTL_DIO_SIGROUTING

#define DQIOCTL_DIO_SIGROUTING (0x0a)

◆ DQIOCTL_DL_CTRL

#define DQIOCTL_DL_CTRL (0x16)

◆ DQIOCTL_DLCFG

#define DQIOCTL_DLCFG (0x12)

◆ DQIOCTL_DLOGGER

#define DQIOCTL_DLOGGER (0x10)

◆ DQIOCTL_DLTRIGGER

#define DQIOCTL_DLTRIGGER (0x11)

◆ DQIOCTL_EXT_DEVICE

#define DQIOCTL_EXT_DEVICE (0x2601)

◆ DQIOCTL_GET211_CFGAMG

#define DQIOCTL_GET211_CFGAMG (0x10)

◆ DQIOCTL_GET_DATA

#define DQIOCTL_GET_DATA (0x15)

◆ DQIOCTL_GETPARAM

#define DQIOCTL_GETPARAM (3)

◆ DQIOCTL_HW_CPUTEST

#define DQIOCTL_HW_CPUTEST (0x40)

◆ DQIOCTL_HW_CPUTEST_ABORT

#define DQIOCTL_HW_CPUTEST_ABORT (0x42)

◆ DQIOCTL_HW_CPUTEST_GET_RESULT

#define DQIOCTL_HW_CPUTEST_GET_RESULT (0x44)

◆ DQIOCTL_HW_CPUTEST_GET_STATUS

#define DQIOCTL_HW_CPUTEST_GET_STATUS (0x43)

◆ DQIOCTL_HW_CPUTEST_START

#define DQIOCTL_HW_CPUTEST_START (0x41)

◆ DQIOCTL_HW_IOMTEST

#define DQIOCTL_HW_IOMTEST (0x80)

◆ DQIOCTL_HW_NWTEST

#define DQIOCTL_HW_NWTEST (0x45)

◆ DQIOCTL_PROGRESS

#define DQIOCTL_PROGRESS (0x14)

◆ DQIOCTL_SD_CTRL

#define DQIOCTL_SD_CTRL (0x13)

◆ DQIOCTL_SET211CHANNEL

#define DQIOCTL_SET211CHANNEL (0x08)

◆ DQIOCTL_SET211LAYER

#define DQIOCTL_SET211LAYER (0x09)

◆ DQIOCTL_SET550CFG

#define DQIOCTL_SET550CFG (0x08)

◆ DQIOCTL_SETFILTER

#define DQIOCTL_SETFILTER (4)

◆ DQIOCTL_SETPARAM

#define DQIOCTL_SETPARAM (2)

◆ DQIOCTL_SIGROUTING

#define DQIOCTL_SIGROUTING (5)

◆ DQIOCTL_VDD_CONFIG [1/2]

#define DQIOCTL_VDD_CONFIG (0x23)

◆ DQIOCTL_VDD_CONFIG [2/2]

#define DQIOCTL_VDD_CONFIG (0x23)

◆ DQIOCTL_VDD_FINISHTRL [1/2]

#define DQIOCTL_VDD_FINISHTRL (0x22)

◆ DQIOCTL_VDD_FINISHTRL [2/2]

#define DQIOCTL_VDD_FINISHTRL (0x22)

◆ DQIOCTL_VDD_SETTMRSRC [1/2]

#define DQIOCTL_VDD_SETTMRSRC (0x24)

◆ DQIOCTL_VDD_SETTMRSRC [2/2]

#define DQIOCTL_VDD_SETTMRSRC (0x24)

◆ DQIOCTL_VDD_SETTRL [1/2]

#define DQIOCTL_VDD_SETTRL (0x21)

◆ DQIOCTL_VDD_SETTRL [2/2]

#define DQIOCTL_VDD_SETTRL (0x21)

◆ DQL_ADDMODE_DOUBLE_PRECISION

#define DQL_ADDMODE_DOUBLE_PRECISION (1L<<14)

◆ DQL_AO301_SYNC_WRITE

#define DQL_AO301_SYNC_WRITE (0xC1000000)

◆ DQL_CHAN448_ADCCHAN

#define DQL_CHAN448_ADCCHAN 0x40

◆ DQL_CHAN448_CHDF

#define DQL_CHAN448_CHDF ( N ) (((N)&0x1f)|0x40)

◆ DQL_CHAN448_CHSE

#define DQL_CHAN448_CHSE ( N ) (((N)&0x3f)|0x40)

◆ DQL_CHAN448_GNDDI

#define DQL_CHAN448_GNDDI 0x5B

◆ DQL_CHAN448_GNDPIN

#define DQL_CHAN448_GNDPIN 0x32

◆ DQL_CHAN448_GNDPINDI

#define DQL_CHAN448_GNDPINDI 0x59

◆ DQL_CHAN448_PWR0

#define DQL_CHAN448_PWR0 0x30

◆ DQL_CHAN448_PWR1

#define DQL_CHAN448_PWR1 0x31

◆ DQL_CHAN448_STATUS

#define DQL_CHAN448_STATUS 0x34

◆ DQL_CHAN448_TCJC

#define DQL_CHAN448_TCJC 0x58

◆ DQL_CHAN448_VREF25

#define DQL_CHAN448_VREF25 0x33

◆ DQL_CHAN448_VREF25DI

#define DQL_CHAN448_VREF25DI 0x5A

◆ DQL_DIO416_ADCCFG0

#define DQL_DIO416_ADCCFG0 (0x201C)

◆ DQL_DIO416_ADCCFG1

#define DQL_DIO416_ADCCFG1 (0x2020)

◆ DQL_DIO416_ADCDATA0

#define DQL_DIO416_ADCDATA0 (0x201C)

◆ DQL_DIO416_ADCDATA1

#define DQL_DIO416_ADCDATA1 (0x2020)

◆ DQL_DIO416_ADCE

#define DQL_DIO416_ADCE (0x20FC)

◆ DQL_DIO416_ADCS

#define DQL_DIO416_ADCS (0x20C0)

◆ DQL_DIO416_ADCSPD

#define DQL_DIO416_ADCSPD (0x200C)

◆ DQL_DIO416_ADCSTS

#define DQL_DIO416_ADCSTS (0x200C)

◆ DQL_DIO416_CFG

#define DQL_DIO416_CFG (0x2000)

◆ DQL_DIO416_DISCFG

#define DQL_DIO416_DISCFG (0x2008)

◆ DQL_DIO416_DISDIV

#define DQL_DIO416_DISDIV (0x2024)

◆ DQL_DIO416_DISSTS

#define DQL_DIO416_DISSTS (0x2008)

◆ DQL_DIO416_DOUTACT

#define DQL_DIO416_DOUTACT (0x2028)

◆ DQL_DIO416_OCLE

#define DQL_DIO416_OCLE (0x207C)

◆ DQL_DIO416_OCLS

#define DQL_DIO416_OCLS (0x2040)

◆ DQL_DIO416_PORT0OCM

#define DQL_DIO416_PORT0OCM (0x2010)

◆ DQL_DIO416_PORT0OCS

#define DQL_DIO416_PORT0OCS (0x2010)

◆ DQL_DIO416_PORT0OUT

#define DQL_DIO416_PORT0OUT (0x2004)

◆ DQL_DIO416_PORT0UCM

#define DQL_DIO416_PORT0UCM (0x2014)

◆ DQL_DIO416_PORT0UCS

#define DQL_DIO416_PORT0UCS (0x2014)

◆ DQL_DIO416_RDCNT

#define DQL_DIO416_RDCNT (0x2018)

◆ DQL_DIO416_UCLE

#define DQL_DIO416_UCLE (0x20BC)

◆ DQL_DIO416_UCLS

#define DQL_DIO416_UCLS (0x2080)

◆ DQL_DIO416E

#define DQL_DIO416E (0x20FC)

◆ DQL_DIO416S

#define DQL_DIO416S (0x2000)

◆ DQL_DIO432_ADCDATAE

#define DQL_DIO432_ADCDATAE (0xBC)

◆ DQL_DIO432_ADCDATAS

#define DQL_DIO432_ADCDATAS (0x80)

◆ DQL_DIO432_BASEE

#define DQL_DIO432_BASEE (0x20FC)

◆ DQL_DIO432_BASES

#define DQL_DIO432_BASES (0x2000)

◆ DQL_DIO432_BLK0

#define DQL_DIO432_BLK0 (0x100)

◆ DQL_DIO432_BLK0E

#define DQL_DIO432_BLK0E (0x22FC)

◆ DQL_DIO432_BLK0S

#define DQL_DIO432_BLK0S (0x2100)

◆ DQL_DIO432_BLK1

#define DQL_DIO432_BLK1 (0x300)

◆ DQL_DIO432_BLK1E

#define DQL_DIO432_BLK1E (0x24FC)

◆ DQL_DIO432_BLK1S

#define DQL_DIO432_BLK1S (0x2300)

◆ DQL_DIO432_BLK2

#define DQL_DIO432_BLK2 (0x500)

◆ DQL_DIO432_BLK2E

#define DQL_DIO432_BLK2E (0x25FC)

◆ DQL_DIO432_BLK2S

#define DQL_DIO432_BLK2S (0x2500)

◆ DQL_DIO432_BLK3

#define DQL_DIO432_BLK3 (0x600)

◆ DQL_DIO432_BLK3E

#define DQL_DIO432_BLK3E (0x26FC)

◆ DQL_DIO432_BLK3S

#define DQL_DIO432_BLK3S (0x2600)

◆ DQL_DIO432_CLKDIV

#define DQL_DIO432_CLKDIV (0x2708)

◆ DQL_DIO432_DIN

#define DQL_DIO432_DIN (0x2000)

◆ DQL_DIO432_DIO_OFFSET

#define DQL_DIO432_DIO_OFFSET ( CH ) (((CH&0x1F)<(DQ_DIO432_CHAN/2))?DQL_DIO432_BLK0:DQL_DIO432_BLK1)

◆ DQL_DIO432_DIOCFGE

#define DQL_DIO432_DIOCFGE (0x28FC)

◆ DQL_DIO432_DIOCFGS

#define DQL_DIO432_DIOCFGS (0x2880)

◆ DQL_DIO432_DIODIVE

#define DQL_DIO432_DIODIVE (0x287C)

◆ DQL_DIO432_DIODIVS

#define DQL_DIO432_DIODIVS (0x2800)

◆ DQL_DIO432_DIOE

#define DQL_DIO432_DIOE (0x297C)

◆ DQL_DIO432_DIOS

#define DQL_DIO432_DIOS (0x2700)

◆ DQL_DIO432_DIOUSRE

#define DQL_DIO432_DIOUSRE (0x297C)

◆ DQL_DIO432_DIOUSRS

#define DQL_DIO432_DIOUSRS (0x2900)

◆ DQL_DIO432_DOUT

#define DQL_DIO432_DOUT (0x2004)

◆ DQL_DIO432_IIN_CH_IDX

#define DQL_DIO432_IIN_CH_IDX ( N ) (((N&0xF) < 8L) ? (((N&0xF) << 3)+4L) : ((N&0xF)<<3))

◆ DQL_DIO432_IIN_CH_MAP

#define DQL_DIO432_IIN_CH_MAP ( N ) (DQL_DIO432_BASES | DQL_DIO432_DIO_OFFSET(N) | DQL_DIO416_ADCS | DQL_DIO432_IIN_CH_IDX(N))

◆ DQL_DIO432_OCL_CH_MAP

#define DQL_DIO432_OCL_CH_MAP ( N ) (DQL_DIO432_BASES | DQL_DIO432_DIO_OFFSET(N) | DQL_DIO416_OCLS | ((N&0xF) <<2))

◆ DQL_DIO432_OFFSET0

#define DQL_DIO432_OFFSET0 (DQL_DIO432_BLK0)

◆ DQL_DIO432_OFFSET1

#define DQL_DIO432_OFFSET1 (DQL_DIO432_BLK1)

◆ DQL_DIO432_PWMDIV

#define DQL_DIO432_PWMDIV (0x270C)

◆ DQL_DIO432_UCL_CH_MAP

#define DQL_DIO432_UCL_CH_MAP ( N ) (DQL_DIO432_BASES | DQL_DIO432_DIO_OFFSET(N) | DQL_DIO416_UCLS | ((N&0xF) <<2))

◆ DQL_DIO432_USERCFG

#define DQL_DIO432_USERCFG (0x08)

◆ DQL_DIO432_USERDATA

#define DQL_DIO432_USERDATA (0x0C)

◆ DQL_DIO432_VIN_CH_MAP

#define DQL_DIO432_VIN_CH_MAP ( N ) (DQL_DIO432_BASES | DQL_DIO432_VIN_OFFSET(N) | DQL_DIO432_ADCDATAS | ((N&0xF) <<2))

◆ DQL_DIO432_VIN_OFFSET

#define DQL_DIO432_VIN_OFFSET ( CH ) (((CH&0x1F)<(DQ_DIO432_CHAN/2))?DQL_DIO432_BLK2:DQL_DIO432_BLK3)

◆ DQL_DIO432_VINCFG

#define DQL_DIO432_VINCFG (0x00)

◆ DQL_DIO432_VINCFG_24BIT

#define DQL_DIO432_VINCFG_24BIT (30)

◆ DQL_DIO432_VINCFG_ADCFE

#define DQL_DIO432_VINCFG_ADCFE (29)

◆ DQL_DIO432_VINCFG_ASL1BIT

#define DQL_DIO432_VINCFG_ASL1BIT (28)

◆ DQL_DIO432_VINCFG_DILSB

#define DQL_DIO432_VINCFG_DILSB (0)

◆ DQL_DIO432_VINCFG_DIMSB

#define DQL_DIO432_VINCFG_DIMSB (15)

◆ DQL_DIO432_VINCFG_DIVLSB

#define DQL_DIO432_VINCFG_DIVLSB (20)

◆ DQL_DIO432_VINCFG_DIVMSB

#define DQL_DIO432_VINCFG_DIVMSB (27)

◆ DQL_DIO432_VINCFG_SPEEDLSB

#define DQL_DIO432_VINCFG_SPEEDLSB (16)

◆ DQL_DIO432_VINCFG_SPEEDMSB

#define DQL_DIO432_VINCFG_SPEEDMSB (19)

◆ DQL_DIO432_VINCFG_UONLY

#define DQL_DIO432_VINCFG_UONLY (31)

◆ DQL_DIO432_VINSTS

#define DQL_DIO432_VINSTS (0x04)

◆ DQL_EXT_DEV_CMDMASK

#define DQL_EXT_DEV_CMDMASK (0x7)

◆ DQL_EXT_DEV_CMDMASK_SHFT

#define DQL_EXT_DEV_CMDMASK_SHFT (21)

◆ DQL_EXT_DEV_DATAMASK

#define DQL_EXT_DEV_DATAMASK (0xfffff)

◆ DQL_EXT_DEV_DATAMASK_SHFT

#define DQL_EXT_DEV_DATAMASK_SHFT (1)

◆ DQL_EXT_DEV_PREAMBLE

#define DQL_EXT_DEV_PREAMBLE (0xa3<<24)

◆ DQL_EXT_DEV_RETURN_PREABLE

#define DQL_EXT_DEV_RETURN_PREABLE (0xa0000000)

◆ DQL_EXT_DEV_RETURN_PREABLE_MASK

#define DQL_EXT_DEV_RETURN_PREABLE_MASK (0xe0000000)

◆ DQL_FE207_AGND

#define DQL_FE207_AGND (32)

◆ DQL_FE207_CJC

#define DQL_FE207_CJC (33)

◆ DQL_FE207_REF

#define DQL_FE207_REF (34)

◆ DQL_FE208_PPG

#define DQL_FE208_PPG (0x10)

◆ DQL_FE208_PSPG

#define DQL_FE208_PSPG (0x20)

◆ DQL_FE208_PSSM

#define DQL_FE208_PSSM (0x30)

◆ DQL_FE208_SCUR

#define DQL_FE208_SCUR (0x40)

◆ DQL_FE208_SPSM

#define DQL_FE208_SPSM (0x0)

◆ DQL_IOCTL104_BLOCKWRRD

#define DQL_IOCTL104_BLOCKWRRD (0xC)

◆ DQL_IOCTL104_CUSTOMPROC

#define DQL_IOCTL104_CUSTOMPROC (0xE)

◆ DQL_IOCTL104_MEMIOWRRD

#define DQL_IOCTL104_MEMIOWRRD (0xA)

◆ DQL_IOCTL104_MEMORYWRRD

#define DQL_IOCTL104_MEMORYWRRD (0xD)

◆ DQL_IOCTL104_SETCFG

#define DQL_IOCTL104_SETCFG (0x8)

◆ DQL_IOCTL104_SETDCDC

#define DQL_IOCTL104_SETDCDC (0x9)

◆ DQL_IOCTL104_START

#define DQL_IOCTL104_START (0xB)

◆ DQL_IOCTL2000_GETPASS

#define DQL_IOCTL2000_GETPASS (10L)

◆ DQL_IOCTL2000_SETPASS

#define DQL_IOCTL2000_SETPASS (11L)

◆ DQL_IOCTL208_READ_5k

#define DQL_IOCTL208_READ_5k (19)

◆ DQL_IOCTL208_READ_5kB

#define DQL_IOCTL208_READ_5kB (21)

◆ DQL_IOCTL208_READ_AGND

#define DQL_IOCTL208_READ_AGND (13)

◆ DQL_IOCTL208_READ_PP

#define DQL_IOCTL208_READ_PP (11)

◆ DQL_IOCTL208_READ_PS

#define DQL_IOCTL208_READ_PS (12)

◆ DQL_IOCTL208_READ_PSM

#define DQL_IOCTL208_READ_PSM (20)

◆ DQL_IOCTL208_READ_Ra

#define DQL_IOCTL208_READ_Ra (17)

◆ DQL_IOCTL208_READ_Rb

#define DQL_IOCTL208_READ_Rb (18)

◆ DQL_IOCTL208_READ_REF

#define DQL_IOCTL208_READ_REF (14)

◆ DQL_IOCTL208_READ_Rs

#define DQL_IOCTL208_READ_Rs (15)

◆ DQL_IOCTL208_READ_Rx

#define DQL_IOCTL208_READ_Rx (16)

◆ DQL_IOCTL208_READ_SS

#define DQL_IOCTL208_READ_SS (10)

◆ DQL_IOCTL208_SET_EXC_A

#define DQL_IOCTL208_SET_EXC_A (2)

◆ DQL_IOCTL208_SET_EXC_B

#define DQL_IOCTL208_SET_EXC_B (3)

◆ DQL_IOCTL208_SET_EXC_CH

#define DQL_IOCTL208_SET_EXC_CH (4)

◆ DQL_IOCTL208_SET_Ra

#define DQL_IOCTL208_SET_Ra (5)

◆ DQL_IOCTL208_SET_Rb

#define DQL_IOCTL208_SET_Rb (6)

◆ DQL_IOCTL208_SET_SSPERCHAN

#define DQL_IOCTL208_SET_SSPERCHAN (1)

◆ DQL_IOCTL224_MEASSHUNT

#define DQL_IOCTL224_MEASSHUNT (0xB)

◆ DQL_IOCTL224_SETAVG

#define DQL_IOCTL224_SETAVG (0xC)

◆ DQL_IOCTL224_SETCFG

#define DQL_IOCTL224_SETCFG (0x8)

◆ DQL_IOCTL224_SETEXC

#define DQL_IOCTL224_SETEXC (0x9)

◆ DQL_IOCTL224_SETSHUNT

#define DQL_IOCTL224_SETSHUNT (0xA)

◆ DQL_IOCTL254_DIO

#define DQL_IOCTL254_DIO (0xD)

◆ DQL_IOCTL254_GETEXC

#define DQL_IOCTL254_GETEXC (0xA)

◆ DQL_IOCTL254_GETWF

#define DQL_IOCTL254_GETWF (0xE)

◆ DQL_IOCTL254_SETCFG

#define DQL_IOCTL254_SETCFG (0x8)

◆ DQL_IOCTL254_SETEXC

#define DQL_IOCTL254_SETEXC (0x9)

◆ DQL_IOCTL254_SETEXT

#define DQL_IOCTL254_SETEXT (0xF)

◆ DQL_IOCTL254_SETWF

#define DQL_IOCTL254_SETWF (0xC)

◆ DQL_IOCTL254_START

#define DQL_IOCTL254_START (0xB)

◆ DQL_IOCTL255_DIO

#define DQL_IOCTL255_DIO (0xD)

◆ DQL_IOCTL255_GETEXC

#define DQL_IOCTL255_GETEXC (0xA)

◆ DQL_IOCTL255_GETWF

#define DQL_IOCTL255_GETWF (0xE)

◆ DQL_IOCTL255_SETCFG

#define DQL_IOCTL255_SETCFG (0x8)

◆ DQL_IOCTL255_SETEXC

#define DQL_IOCTL255_SETEXC (0x9)

◆ DQL_IOCTL255_SETEXT

#define DQL_IOCTL255_SETEXT (0xF)

◆ DQL_IOCTL255_SETWF

#define DQL_IOCTL255_SETWF (0xC)

◆ DQL_IOCTL255_START

#define DQL_IOCTL255_START (0xB)

◆ DQL_IOCTL301_CTRLWF

#define DQL_IOCTL301_CTRLWF (11L)

◆ DQL_IOCTL301_WRITEWF

#define DQL_IOCTL301_WRITEWF (10L)

◆ DQL_IOCTL358_CTRLWF

#define DQL_IOCTL358_CTRLWF (11L)

◆ DQL_IOCTL358_RW_XEEPROM

#define DQL_IOCTL358_RW_XEEPROM (0x0f)

◆ DQL_IOCTL358_WRITEWF

#define DQL_IOCTL358_WRITEWF (10L)

◆ DQL_IOCTL3XX_READ_TEST

#define DQL_IOCTL3XX_READ_TEST (12L)

◆ DQL_IOCTL401_CFG_DI_CHANGE

#define DQL_IOCTL401_CFG_DI_CHANGE (1L)

◆ DQL_IOCTL401_WAIT_DI_CHANGE

#define DQL_IOCTL401_WAIT_DI_CHANGE (2L)

◆ DQL_IOCTL403_CFG_DI_CHANGE

#define DQL_IOCTL403_CFG_DI_CHANGE (11L)

◆ DQL_IOCTL403_WAIT_DI_CHANGE

#define DQL_IOCTL403_WAIT_DI_CHANGE (12L)

◆ DQL_IOCTL432_SETDCDC

#define DQL_IOCTL432_SETDCDC (0x8)

◆ DQL_IOCTL448_SET_DBREGS

#define DQL_IOCTL448_SET_DBREGS (0x7)

◆ DQL_IOCTL448_SET_LEVELS

#define DQL_IOCTL448_SET_LEVELS (0x6)

◆ DQL_IOCTL500_SET_MSG_LEN

#define DQL_IOCTL500_SET_MSG_LEN 3

◆ DQL_IOCTL500_SET_MSG_TERM

#define DQL_IOCTL500_SET_MSG_TERM 2

◆ DQL_IOCTL500_SET_MSG_TIMER

#define DQL_IOCTL500_SET_MSG_TIMER 1

◆ DQL_IOCTL501_BREAK

#define DQL_IOCTL501_BREAK (0x0CL)

◆ DQL_IOCTL501_CHANGE

#define DQL_IOCTL501_CHANGE (0x0DL)

◆ DQL_IOCTL501_CHANGE_FINCLEAR

#define DQL_IOCTL501_CHANGE_FINCLEAR (0x1)

◆ DQL_IOCTL501_CHANGE_FINFOUT

#define DQL_IOCTL501_CHANGE_FINFOUT (0x3)

◆ DQL_IOCTL501_CHANGE_FOUTCLEAR

#define DQL_IOCTL501_CHANGE_FOUTCLEAR (0x2)

◆ DQL_IOCTL501_CHANGE_PARITY

#define DQL_IOCTL501_CHANGE_PARITY (0x8)

◆ DQL_IOCTL501_CHANGE_PAUSE

#define DQL_IOCTL501_CHANGE_PAUSE (0x9)

◆ DQL_IOCTL501_CHANGE_RESUME

#define DQL_IOCTL501_CHANGE_RESUME (0xA)

◆ DQL_IOCTL501_CHANGE_SETCHCFG

#define DQL_IOCTL501_CHANGE_SETCHCFG (0x4)

◆ DQL_IOCTL501_READ_CFIFO

#define DQL_IOCTL501_READ_CFIFO (0x1001L)

◆ DQL_IOCTL501_READ_CHNL

#define DQL_IOCTL501_READ_CHNL (0x07L)

◆ DQL_IOCTL501_SET_TL

#define DQL_IOCTL501_SET_TL (0x06L)

◆ DQL_IOCTL501_SET_TS

#define DQL_IOCTL501_SET_TS (0x05L)

◆ DQL_IOCTL501_SETBASECLOCK

#define DQL_IOCTL501_SETBASECLOCK (0x0CL)

◆ DQL_IOCTL501_SETBAUD

#define DQL_IOCTL501_SETBAUD (0x01L)

◆ DQL_IOCTL501_SETCHARDLY

#define DQL_IOCTL501_SETCHARDLY (0x0DL)

◆ DQL_IOCTL501_SETCHNL_CFG

#define DQL_IOCTL501_SETCHNL_CFG (0x09L)

◆ DQL_IOCTL501_SETFRAMEDLY

#define DQL_IOCTL501_SETFRAMEDLY (0x0EL)

◆ DQL_IOCTL501_SETRXWM

#define DQL_IOCTL501_SETRXWM (0x03L)

◆ DQL_IOCTL501_SETRXWM_DIRECT

#define DQL_IOCTL501_SETRXWM_DIRECT (0x07L)

◆ DQL_IOCTL501_SETTIMEOUT

#define DQL_IOCTL501_SETTIMEOUT (0x04L)

◆ DQL_IOCTL501_SETTXWM

#define DQL_IOCTL501_SETTXWM (0x02L)

◆ DQL_IOCTL501_START

#define DQL_IOCTL501_START (0x0AL)

◆ DQL_IOCTL501_STATUS

#define DQL_IOCTL501_STATUS (0x0FL)

◆ DQL_IOCTL501_STOP

#define DQL_IOCTL501_STOP (0x0BL)

◆ DQL_IOCTL501_WRITE_CHNL

#define DQL_IOCTL501_WRITE_CHNL (0x08L)

◆ DQL_IOCTL503_READ_CHNL

#define DQL_IOCTL503_READ_CHNL (0x5)

◆ DQL_IOCTL503_RESET_CHNL

#define DQL_IOCTL503_RESET_CHNL (0x4)

◆ DQL_IOCTL503_SET_MASK

#define DQL_IOCTL503_SET_MASK (0x1)

◆ DQL_IOCTL503_SET_OPER_MODE

#define DQL_IOCTL503_SET_OPER_MODE (0x3)

◆ DQL_IOCTL503_SET_RATE

#define DQL_IOCTL503_SET_RATE (0x2)

◆ DQL_IOCTL503_SETCHNL_CFG

#define DQL_IOCTL503_SETCHNL_CFG (0x7)

◆ DQL_IOCTL503_SETRXWM

#define DQL_IOCTL503_SETRXWM (0x5)

◆ DQL_IOCTL503_SETTXWM

#define DQL_IOCTL503_SETTXWM (0x4)

◆ DQL_IOCTL503_START

#define DQL_IOCTL503_START (0x8)

◆ DQL_IOCTL503_STATUS

#define DQL_IOCTL503_STATUS (0x0FL)

◆ DQL_IOCTL503_STOP

#define DQL_IOCTL503_STOP (0x9)

◆ DQL_IOCTL503_WRITE_CHNL

#define DQL_IOCTL503_WRITE_CHNL (0x6)

◆ DQL_IOCTL553_BC_CFG

#define DQL_IOCTL553_BC_CFG (0x1004L)

◆ DQL_IOCTL553_BIT

#define DQL_IOCTL553_BIT (0x0BL)

◆ DQL_IOCTL553_BM_CFG

#define DQL_IOCTL553_BM_CFG (0x1002L)

◆ DQL_IOCTL553_CONTROL

#define DQL_IOCTL553_CONTROL (0x08L)

◆ DQL_IOCTL553_CONTROL_BC

#define DQL_IOCTL553_CONTROL_BC (0x100EL)

◆ DQL_IOCTL553_DEBUG_GOTO

#define DQL_IOCTL553_DEBUG_GOTO 7

◆ DQL_IOCTL553_DEBUG_START

#define DQL_IOCTL553_DEBUG_START 3

◆ DQL_IOCTL553_DEBUG_STEP_MJ

#define DQL_IOCTL553_DEBUG_STEP_MJ 5

◆ DQL_IOCTL553_DEBUG_STEP_MN

#define DQL_IOCTL553_DEBUG_STEP_MN 6

◆ DQL_IOCTL553_DEBUG_STOP

#define DQL_IOCTL553_DEBUG_STOP 4

◆ DQL_IOCTL553_FILTER

#define DQL_IOCTL553_FILTER (0x0DL)

◆ DQL_IOCTL553_MAJORD

#define DQL_IOCTL553_MAJORD 1

◆ DQL_IOCTL553_MINORD

#define DQL_IOCTL553_MINORD 2

◆ DQL_IOCTL553_MJ_SWAP

#define DQL_IOCTL553_MJ_SWAP 1

◆ DQL_IOCTL553_MJMN_CLEAR

#define DQL_IOCTL553_MJMN_CLEAR 8

◆ DQL_IOCTL553_MN_SWAP

#define DQL_IOCTL553_MN_SWAP 2

◆ DQL_IOCTL553_MNBLOCK0

#define DQL_IOCTL553_MNBLOCK0 1

◆ DQL_IOCTL553_MNBLOCK1

#define DQL_IOCTL553_MNBLOCK1 2

◆ DQL_IOCTL553_READ_BCCB

#define DQL_IOCTL553_READ_BCCB (0x100CL)

◆ DQL_IOCTL553_READ_FIFO

#define DQL_IOCTL553_READ_FIFO (0x05L)

◆ DQL_IOCTL553_READ_MD

#define DQL_IOCTL553_READ_MD (0x100AL)

◆ DQL_IOCTL553_READ_RAM

#define DQL_IOCTL553_READ_RAM (0x1007L)

◆ DQL_IOCTL553_READ_RT

#define DQL_IOCTL553_READ_RT (0x1005L)

◆ DQL_IOCTL553_RESERVED

#define DQL_IOCTL553_RESERVED (0x0CL)

◆ DQL_IOCTL553_RT_CFG

#define DQL_IOCTL553_RT_CFG (0x1003L)

◆ DQL_IOCTL553_RT_VALID

#define DQL_IOCTL553_RT_VALID (0x100FL)

◆ DQL_IOCTL553_SETCLK

#define DQL_IOCTL553_SETCLK (0x0EL)

◆ DQL_IOCTL553_SETMODE

#define DQL_IOCTL553_SETMODE (0x01L)

◆ DQL_IOCTL553_SETPARAM_READABS

#define DQL_IOCTL553_SETPARAM_READABS 3

◆ DQL_IOCTL553_SETPARAM_READREG

#define DQL_IOCTL553_SETPARAM_READREG 1

◆ DQL_IOCTL553_SETPARAM_WRITEABS

#define DQL_IOCTL553_SETPARAM_WRITEABS 4

◆ DQL_IOCTL553_SETPARAM_WRITEREG

#define DQL_IOCTL553_SETPARAM_WRITEREG 2

◆ DQL_IOCTL553_SETRXWM

#define DQL_IOCTL553_SETRXWM (0x03L)

◆ DQL_IOCTL553_SETTIMEOUT

#define DQL_IOCTL553_SETTIMEOUT (0x04L)

◆ DQL_IOCTL553_SETTXWM

#define DQL_IOCTL553_SETTXWM (0x02L)

◆ DQL_IOCTL553_START

#define DQL_IOCTL553_START (0x0AL)

◆ DQL_IOCTL553_STATUS

#define DQL_IOCTL553_STATUS (0x0FL)

◆ DQL_IOCTL553_STATUS_BC

#define DQL_IOCTL553_STATUS_BC (0x100DL)

◆ DQL_IOCTL553_TRIGGER

#define DQL_IOCTL553_TRIGGER (0x07L)

◆ DQL_IOCTL553_WRITE_BCCB

#define DQL_IOCTL553_WRITE_BCCB (0x100BL)

◆ DQL_IOCTL553_WRITE_FIFO

#define DQL_IOCTL553_WRITE_FIFO (0x06L)

◆ DQL_IOCTL553_WRITE_MD

#define DQL_IOCTL553_WRITE_MD (0x1009L)

◆ DQL_IOCTL553_WRITE_RAM

#define DQL_IOCTL553_WRITE_RAM (0x1008L)

◆ DQL_IOCTL553_WRITE_RT

#define DQL_IOCTL553_WRITE_RT (0x1006L)

◆ DQL_IOCTL555_CHANGE_FINFOUT

#define DQL_IOCTL555_CHANGE_FINFOUT (0x3)

◆ DQL_IOCTL566_CHANGE

#define DQL_IOCTL566_CHANGE (0x21L)

◆ DQL_IOCTL566_CHANGE_FINCLEAR

#define DQL_IOCTL566_CHANGE_FINCLEAR (0x1)

◆ DQL_IOCTL566_CHANGE_FOUTCLEAR

#define DQL_IOCTL566_CHANGE_FOUTCLEAR (0x2)

◆ DQL_IOCTL566_CHANGE_PAUSE

#define DQL_IOCTL566_CHANGE_PAUSE (0x9)

◆ DQL_IOCTL566_CHANGE_RESUME

#define DQL_IOCTL566_CHANGE_RESUME (0xA)

◆ DQL_IOCTL566_FILTER

#define DQL_IOCTL566_FILTER (0x0DL)

◆ DQL_IOCTL566_READ_CHNL

#define DQL_IOCTL566_READ_CHNL (0x07L)

◆ DQL_IOCTL566_READ_FIFO

#define DQL_IOCTL566_READ_FIFO (0x05L)

◆ DQL_IOCTL566_SCHED

#define DQL_IOCTL566_SCHED (0x0CL)

◆ DQL_IOCTL566_SETCFG

#define DQL_IOCTL566_SETCFG (0x01L)

◆ DQL_IOCTL566_SETCHNL_CFG

#define DQL_IOCTL566_SETCHNL_CFG (0x1001L)

◆ DQL_IOCTL566_SETCHNL_MODE

#define DQL_IOCTL566_SETCHNL_MODE (0x09L)

◆ DQL_IOCTL566_SETCLK

#define DQL_IOCTL566_SETCLK (0x0EL)

◆ DQL_IOCTL566_SETRXWM

#define DQL_IOCTL566_SETRXWM (0x03L)

◆ DQL_IOCTL566_SETTIMEOUT

#define DQL_IOCTL566_SETTIMEOUT (0x04L)

◆ DQL_IOCTL566_SETTXWM

#define DQL_IOCTL566_SETTXWM (0x02L)

◆ DQL_IOCTL566_START

#define DQL_IOCTL566_START (0x0AL)

◆ DQL_IOCTL566_STATUS

#define DQL_IOCTL566_STATUS (0x0FL)

◆ DQL_IOCTL566_STOP

#define DQL_IOCTL566_STOP (0x0BL)

◆ DQL_IOCTL566_WRITE_CHNL

#define DQL_IOCTL566_WRITE_CHNL (0x08L)

◆ DQL_IOCTL566_WRITE_FIFO

#define DQL_IOCTL566_WRITE_FIFO (0x06L)

◆ DQL_IOCTL601_ADDITIONAL

#define DQL_IOCTL601_ADDITIONAL (12L)

◆ DQL_IOCTL601_CTR_CLR

#define DQL_IOCTL601_CTR_CLR (10L)

◆ DQL_IOCTL601_CTR_DIS

#define DQL_IOCTL601_CTR_DIS (5L)

◆ DQL_IOCTL601_CTR_EN

#define DQL_IOCTL601_CTR_EN (4L)

◆ DQL_IOCTL601_DISALL

#define DQL_IOCTL601_DISALL (7L)

◆ DQL_IOCTL601_ENALL

#define DQL_IOCTL601_ENALL (6L)

◆ DQL_IOCTL601_GET_REG

#define DQL_IOCTL601_GET_REG (3L)

◆ DQL_IOCTL601_READCHNL

#define DQL_IOCTL601_READCHNL (8L)

◆ DQL_IOCTL601_SET_REG

#define DQL_IOCTL601_SET_REG (2L)

◆ DQL_IOCTL601_SET_WM

#define DQL_IOCTL601_SET_WM (11L)

◆ DQL_IOCTL601_SETCHNL_CFG

#define DQL_IOCTL601_SETCHNL_CFG (1L)

◆ DQL_IOCTL601_START

#define DQL_IOCTL601_START (0x0AL)

◆ DQL_IOCTL601_STOP

#define DQL_IOCTL601_STOP (0x0BL)

◆ DQL_IOCTL601_WRITECHNL

#define DQL_IOCTL601_WRITECHNL (9L)

◆ DQL_IOCTL604_CTR_CLR

#define DQL_IOCTL604_CTR_CLR (9L)

◆ DQL_IOCTL604_CTR_DIS

#define DQL_IOCTL604_CTR_DIS (5L)

◆ DQL_IOCTL604_CTR_EN

#define DQL_IOCTL604_CTR_EN (4L)

◆ DQL_IOCTL604_DISALL

#define DQL_IOCTL604_DISALL (7L)

◆ DQL_IOCTL604_ENALL

#define DQL_IOCTL604_ENALL (6L)

◆ DQL_IOCTL604_GET_DIN

#define DQL_IOCTL604_GET_DIN (11L)

◆ DQL_IOCTL604_GET_DOUT

#define DQL_IOCTL604_GET_DOUT (12L)

◆ DQL_IOCTL604_GET_REG

#define DQL_IOCTL604_GET_REG (3L)

◆ DQL_IOCTL604_READCHNL

#define DQL_IOCTL604_READCHNL (8L)

◆ DQL_IOCTL604_SET_DOUT

#define DQL_IOCTL604_SET_DOUT (13L)

◆ DQL_IOCTL604_SET_REG

#define DQL_IOCTL604_SET_REG (2L)

◆ DQL_IOCTL604_SET_WM

#define DQL_IOCTL604_SET_WM (10L)

◆ DQL_IOCTL604_SETCHNL_CFG

#define DQL_IOCTL604_SETCHNL_CFG (1L)

◆ DQL_IOCTL651_GET_FWCFG

#define DQL_IOCTL651_GET_FWCFG (3L)

◆ DQL_IOCTL651_GET_FWCLK_MAX

#define DQL_IOCTL651_GET_FWCLK_MAX (8L)

◆ DQL_IOCTL651_GET_FWCLK_MIN

#define DQL_IOCTL651_GET_FWCLK_MIN (7L)

◆ DQL_IOCTL651_GET_FWCNT

#define DQL_IOCTL651_GET_FWCNT (11L)

◆ DQL_IOCTL651_GET_FWCRH

#define DQL_IOCTL651_GET_FWCRH (9L)

◆ DQL_IOCTL651_GET_FWCRP

#define DQL_IOCTL651_GET_FWCRP (10L)

◆ DQL_IOCTL651_GET_FWDC

#define DQL_IOCTL651_GET_FWDC (5L)

◆ DQL_IOCTL651_GET_FWDIV

#define DQL_IOCTL651_GET_FWDIV (6L)

◆ DQL_IOCTL651_GET_LCR

#define DQL_IOCTL651_GET_LCR (1L)

◆ DQL_IOCTL651_GET_STS

#define DQL_IOCTL651_GET_STS (2L)

◆ DQL_IOCTL651_SET_DW

#define DQL_IOCTL651_SET_DW (4L)

◆ DQL_IOCTL651_SET_FWCFG

#define DQL_IOCTL651_SET_FWCFG (3L)

◆ DQL_IOCTL651_SET_FWCLK_MAX

#define DQL_IOCTL651_SET_FWCLK_MAX (8L)

◆ DQL_IOCTL651_SET_FWCLK_MIN

#define DQL_IOCTL651_SET_FWCLK_MIN (7L)

◆ DQL_IOCTL651_SET_FWDC

#define DQL_IOCTL651_SET_FWDC (5L)

◆ DQL_IOCTL651_SET_FWDIV

#define DQL_IOCTL651_SET_FWDIV (6L)

◆ DQL_IOCTL651_SET_LCR

#define DQL_IOCTL651_SET_LCR (1L)

◆ DQL_IOCTL801_GET_LCR

#define DQL_IOCTL801_GET_LCR (5L)

◆ DQL_IOCTL801_GET_REG

#define DQL_IOCTL801_GET_REG (3L)

◆ DQL_IOCTL801_SET_LCR

#define DQL_IOCTL801_SET_LCR (4L)

◆ DQL_IOCTL801_SET_REG

#define DQL_IOCTL801_SET_REG (2L)

◆ DQL_IOCTL801_SET_WM

#define DQL_IOCTL801_SET_WM (11L)

◆ DQL_IOCTL801_SETCHNL_CFG

#define DQL_IOCTL801_SETCHNL_CFG (1L)

◆ DQL_IOCTL801_START

#define DQL_IOCTL801_START (0x0AL)

◆ DQL_IOCTL802_GET_LCR

#define DQL_IOCTL802_GET_LCR (5L)

◆ DQL_IOCTL802_GET_REG

#define DQL_IOCTL802_GET_REG (3L)

◆ DQL_IOCTL802_SET_LCR

#define DQL_IOCTL802_SET_LCR (4L)

◆ DQL_IOCTL802_SET_REG

#define DQL_IOCTL802_SET_REG (2L)

◆ DQL_IOCTL802_SET_WM

#define DQL_IOCTL802_SET_WM (11L)

◆ DQL_IOCTL802_SETCHNL_CFG

#define DQL_IOCTL802_SETCHNL_CFG (1L)

◆ DQL_IOCTL802_START

#define DQL_IOCTL802_START (0x0AL)

◆ DQL_IS_DIO432

#define DQL_IS_DIO432 ( N ) ((N == 0x432)||(N == 0x433))

◆ DQL_ISTR208_18BIT

#define DQL_ISTR208_18BIT (1L<<5)

◆ DQL_ISTR208_ADCEN

#define DQL_ISTR208_ADCEN (1L<<1)

◆ DQL_ISTR208_GEN0

#define DQL_ISTR208_GEN0 (1L<<8)

◆ DQL_ISTR208_GEN1

#define DQL_ISTR208_GEN1 (1L<<9)

◆ DQL_ISTR208_GEN2

#define DQL_ISTR208_GEN2 (1L<<10)

◆ DQL_ISTR208_GEN3

#define DQL_ISTR208_GEN3 (1L<<11)

◆ DQL_ISTR208_GEN4

#define DQL_ISTR208_GEN4 (1L<<12)

◆ DQL_ISTR208_GEN5

#define DQL_ISTR208_GEN5 (1L<<13)

◆ DQL_ISTR208_GEN6

#define DQL_ISTR208_GEN6 (1L<<14)

◆ DQL_ISTR208_GEN7

#define DQL_ISTR208_GEN7 (1L<<15)

◆ DQL_ISTR208_LED

#define DQL_ISTR208_LED (1L<<2)

◆ DQL_ISTR208_PD

#define DQL_ISTR208_PD (1L<<4)

◆ DQL_ISTR208_RESET

#define DQL_ISTR208_RESET (1L<<3)

◆ DQL_ISTR208_RSV0

#define DQL_ISTR208_RSV0 (1L<<0)

◆ DQL_ISTR301_DIO0DEF

#define DQL_ISTR301_DIO0DEF (0L<<5)

◆ DQL_ISTR301_DIO0GPIN

#define DQL_ISTR301_DIO0GPIN (2L<<5)

◆ DQL_ISTR301_DIO0GPOUT

#define DQL_ISTR301_DIO0GPOUT (3L<<5)

◆ DQL_ISTR301_DIO0INT0

#define DQL_ISTR301_DIO0INT0 (0L<<0)

◆ DQL_ISTR301_DIO0INT1

#define DQL_ISTR301_DIO0INT1 (1L<<0)

◆ DQL_ISTR301_DIO0INV

#define DQL_ISTR301_DIO0INV (1L<<7)

◆ DQL_ISTR301_DIO0MODE

#define DQL_ISTR301_DIO0MODE (5)

◆ DQL_ISTR301_DIO0OUT

#define DQL_ISTR301_DIO0OUT (1L<<5)

◆ DQL_ISTR301_DIO0SRC

#define DQL_ISTR301_DIO0SRC (0)

◆ DQL_ISTR301_DIO0SRC2

#define DQL_ISTR301_DIO0SRC2 (2L<<0)

◆ DQL_ISTR301_DIO0SRC3

#define DQL_ISTR301_DIO0SRC3 (3L<<0)

◆ DQL_ISTR301_DIO0VAL

#define DQL_ISTR301_DIO0VAL (1L<<4)

◆ DQL_ISTR301_DIO1DEF

#define DQL_ISTR301_DIO1DEF (0L<<13)

◆ DQL_ISTR301_DIO1GPIN

#define DQL_ISTR301_DIO1GPIN (2L<<13)

◆ DQL_ISTR301_DIO1GPOUT

#define DQL_ISTR301_DIO1GPOUT (3L<<13)

◆ DQL_ISTR301_DIO1INT0

#define DQL_ISTR301_DIO1INT0 (0L<<8)

◆ DQL_ISTR301_DIO1INT1

#define DQL_ISTR301_DIO1INT1 (1L<<8)

◆ DQL_ISTR301_DIO1INV

#define DQL_ISTR301_DIO1INV (1L<<15)

◆ DQL_ISTR301_DIO1MODE

#define DQL_ISTR301_DIO1MODE (13)

◆ DQL_ISTR301_DIO1OUT

#define DQL_ISTR301_DIO1OUT (1L<<13)

◆ DQL_ISTR301_DIO1SRC

#define DQL_ISTR301_DIO1SRC (8)

◆ DQL_ISTR301_DIO1SRC2

#define DQL_ISTR301_DIO1SRC2 (2L<<8)

◆ DQL_ISTR301_DIO1SRC3

#define DQL_ISTR301_DIO1SRC3 (3L<<8)

◆ DQL_ISTR301_DIO1VAL

#define DQL_ISTR301_DIO1VAL (1L<<12)

◆ DQL_ISTR301_DIO2DEF

#define DQL_ISTR301_DIO2DEF (0L<<21)

◆ DQL_ISTR301_DIO2GPIN

#define DQL_ISTR301_DIO2GPIN (2L<<21)

◆ DQL_ISTR301_DIO2GPOUT

#define DQL_ISTR301_DIO2GPOUT (3L<<21)

◆ DQL_ISTR301_DIO2INT0

#define DQL_ISTR301_DIO2INT0 (0L<<16)

◆ DQL_ISTR301_DIO2INT1

#define DQL_ISTR301_DIO2INT1 (1L<<16)

◆ DQL_ISTR301_DIO2INV

#define DQL_ISTR301_DIO2INV (1L<<23)

◆ DQL_ISTR301_DIO2MODE

#define DQL_ISTR301_DIO2MODE (21)

◆ DQL_ISTR301_DIO2OUT

#define DQL_ISTR301_DIO2OUT (1L<<21)

◆ DQL_ISTR301_DIO2SRC

#define DQL_ISTR301_DIO2SRC (16)

◆ DQL_ISTR301_DIO2SRC2

#define DQL_ISTR301_DIO2SRC2 (2L<<16)

◆ DQL_ISTR301_DIO2SRC3

#define DQL_ISTR301_DIO2SRC3 (3L<<16)

◆ DQL_ISTR301_DIO2VAL

#define DQL_ISTR301_DIO2VAL (1L<<20)

◆ DQL_L553_MJ_SIZE

#define DQL_L553_MJ_SIZE 256

◆ DQL_L553_MN_SIZE

#define DQL_L553_MN_SIZE 128

◆ DQL_LCR504_LED

#define DQL_LCR504_LED (1L<<1)

◆ DQL_LCR553_LED

#define DQL_LCR553_LED 2

◆ DQL_LCR566_LED

#define DQL_LCR566_LED 2

◆ DQL_LCR_462_DCEN

#define DQL_LCR_462_DCEN (1L<<0)

◆ DQL_LCR_462_LED

#define DQL_LCR_462_LED (1L<<1)

◆ DQMAXCHNLS

#define DQMAXCHNLS (32)

◆ DQMAXTRL

#define DQMAXTRL (DQ_MAXDEVN * DQ_MAXSS)

◆ DQMAXUDP

#define DQMAXUDP (530 - DQHSZ)

◆ DQMSG_501_SZ

#define DQMSG_501_SZ (DQ_MAX_MSG_SIZE - sizeof(DQMSG_501) - 2)

◆ DQNOERR_MASK

#define DQNOERR_MASK 0x0000FFFF

◆ DQPROLOGVER

#define DQPROLOGVER 0xBABAFAC2 /* request supported DQ version */

◆ DQSETLOCK_CHECK

#define DQSETLOCK_CHECK (2)

◆ DQSETLOCK_CHECKDIAG

#define DQSETLOCK_CHECKDIAG (3)

◆ DQSETLOCK_DIAG

#define DQSETLOCK_DIAG (4)

◆ DQSETLOCK_LOCK

#define DQSETLOCK_LOCK (0)

◆ DQSETLOCK_UNLOCK

#define DQSETLOCK_UNLOCK (1)

◆ DQTID_PUSH_DATA

#define DQTID_PUSH_DATA (0x80000001)

◆ EP1C12_FILE_SIZE

#define EP1C12_FILE_SIZE (209405)

◆ EP1C20_FILE_SIZE

#define EP1C20_FILE_SIZE (444951)

◆ EP1C3_FILE_SIZE

#define EP1C3_FILE_SIZE (78422)

◆ EP1C4_FILE_SIZE

#define EP1C4_FILE_SIZE (115564)

◆ EP1C6_FILE_SIZE

#define EP1C6_FILE_SIZE (145902)

◆ EP2C15_FILE_SIZE

#define EP2C15_FILE_SIZE (486562)

◆ EP2C20_FILE_SIZE

#define EP2C20_FILE_SIZE (486562)

◆ EP2C35_FILE_SIZE

#define EP2C35_FILE_SIZE (857332)

◆ EP2C50_FILE_SIZE

#define EP2C50_FILE_SIZE (1245424)

◆ EP2C5_FILE_SIZE

#define EP2C5_FILE_SIZE (152998)

◆ EP2C70_FILE_SIZE

#define EP2C70_FILE_SIZE (1789902)

◆ EP2C8_FILE_SIZE

#define EP2C8_FILE_SIZE (247974)

◆ ETH_HDR_SIZE

#define ETH_HDR_SIZE (14)

◆ EV501_ACC_DATA

#define EV501_ACC_DATA (1L<<1)

◆ EV501_FIFO_DATA

#define EV501_FIFO_DATA (1L<<0)

◆ EV601_HI_TO_LOW

#define EV601_HI_TO_LOW (2)

◆ EV601_LOW_TO_HI

#define EV601_LOW_TO_HI (1)

◆ EXC_V2R

#define EXC_V2R ( V ) ((uint16)(V * (65535.0/10.0))&0xffff)

◆ EXT_DEV_ADDRESS2

#define EXT_DEV_ADDRESS2 (0xA0000000)

◆ EXT_DEV_ADDRESS3

#define EXT_DEV_ADDRESS3 (0xA0100000)

◆ EXT_DEV_ADDRESS4

#define EXT_DEV_ADDRESS4 (0xA0200000)

◆ EXT_DEV_ADDRESS5

#define EXT_DEV_ADDRESS5 (0xA0300000)

◆ EXT_DEV_SIZE

#define EXT_DEV_SIZE (0x01000000)

◆ FPGA_IMAGE_MAX_SIZE

#define FPGA_IMAGE_MAX_SIZE (EP2C70_FILE_SIZE)

◆ GET_STS_FLAGS

#define GET_STS_FLAGS	(	DEV,
		SS,
		FG
	)	(((pDEVOBJ)(DEV))->status[(SS)&7][FG])

◆ HW_IOMTEST_BUS

#define HW_IOMTEST_BUS (0x1)

◆ ICR_SECFIFO_RD

#define ICR_SECFIFO_RD (16)

◆ ICR_SECFIFO_RD32

#define ICR_SECFIFO_RD32 (4)

◆ ICR_SECFIFO_WR

#define ICR_SECFIFO_WR (16)

◆ ICR_SECFIFO_WR32

#define ICR_SECFIFO_WR32 (4)

◆ IF_STS_FLAG

#define IF_STS_FLAG	(	DEV,
		SS,
		FG,
		FLAG
	)	(((pDEVOBJ)(DEV))->status[(SS)&7][FG] & (FLAG))

◆ INT_CM2_LOGIC_ADDRESS

#define INT_CM2_LOGIC_ADDRESS 0xA00E0000

◆ INT_DNR_POWER_ADDRESS

#define INT_DNR_POWER_ADDRESS 0xA00C0000

◆ INT_GIGE_LOGIC_ADDRESS

#define INT_GIGE_LOGIC_ADDRESS 0xA00E0000

◆ INT_GIGE_POWER_ADDRESS

#define INT_GIGE_POWER_ADDRESS 0xA00D0000

◆ IOM_BASE_ADDRESS

#define IOM_BASE_ADDRESS (0xA00E0000)

◆ IOM_BASE_IRQ

#define IOM_BASE_IRQ (2)

◆ IP_HDR_SIZE

#define IP_HDR_SIZE (20)

◆ L50x_FIFOSZ

#define L50x_FIFOSZ ( MODEL ) ((MODEL == 0x501)?(DQ_L501_FIFOSZ):(DQ_L508_FIFOSZ))

◆ L8000_CPUTMR_DISABLE

#define L8000_CPUTMR_DISABLE 5

◆ L8000_CPUTMR_MASTER

#define L8000_CPUTMR_MASTER 1

◆ L8000_CPUTMR_SLAVE

#define L8000_CPUTMR_SLAVE 2

◆ L8000_CPUTMR_START

#define L8000_CPUTMR_START 3

◆ L8000_CPUTMR_STOP

#define L8000_CPUTMR_STOP 4

◆ L8000_INFOSZ

#define L8000_INFOSZ DQ_MAX_INFO_SIZE

◆ L8000_MODEL

#define L8000_MODEL 0x8000

◆ L8000_OPTION

#define L8000_OPTION 0x1

◆ L8000_SERNUM

#define L8000_SERNUM 0x8021234

◆ L8000_TIMER

#define L8000_TIMER 0

◆ LM10p

#define LM10p (0.909)

◆ LM6p

#define LM6p (0.943)

◆ LNPRM_BYOFFS

#define LNPRM_BYOFFS 0xF0100000

◆ LNPRM_COMDLY

#define LNPRM_COMDLY 0x110

◆ LNPRM_DEVALL

#define LNPRM_DEVALL 0xFF

◆ LNPRM_DEVIOM

#define LNPRM_DEVIOM 0xFE

◆ LNPRM_DQREV

#define LNPRM_DQREV 0x208

◆ LNPRM_FWREV

#define LNPRM_FWREV 0x209

◆ LNPRM_IOMFRQ

#define LNPRM_IOMFRQ 0x105

◆ LNPRM_IOMMFG

#define LNPRM_IOMMFG 0x104

◆ LNPRM_IOMSN

#define LNPRM_IOMSN 0x103

◆ LNPRM_LNCAL

#define LNPRM_LNCAL 0x206

◆ LNPRM_LNEXP

#define LNPRM_LNEXP 0x207

◆ LNPRM_LNID

#define LNPRM_LNID 0x201

◆ LNPRM_LNMFG

#define LNPRM_LNMFG 0x205

◆ LNPRM_LNOPT

#define LNPRM_LNOPT 0x202

◆ LNPRM_LNSN

#define LNPRM_LNSN 0x203

◆ LNPRM_MODID

#define LNPRM_MODID 0x101

◆ LNPRM_MODOPT

#define LNPRM_MODOPT 0x102

◆ LNPRM_NOCHANGE

#define LNPRM_NOCHANGE 0xF0000000

◆ LNPRM_OPTIONS

#define LNPRM_OPTIONS 0x10A

◆ LNPRM_PERIOD

#define LNPRM_PERIOD 0x107

◆ LNPRM_RDONLY

#define LNPRM_RDONLY 0xF0000000

◆ LNPRM_TICK

#define LNPRM_TICK 0x106

◆ LNPRM_TIME

#define LNPRM_TIME 0x109

◆ LNPRM_TOTAL

#define LNPRM_TOTAL 0x204

◆ LNPRM_WDDLY

#define LNPRM_WDDLY 0x108

◆ LOGIC_PROG_DEV_LIST_SZ

#define LOGIC_PROG_DEV_LIST_SZ 16

◆ LP10p

#define LP10p (1.1)

◆ LP6p

#define LP6p (1.06)

◆ LPERR_ADDROUTRANGE

#define LPERR_ADDROUTRANGE /*0xFFFFFF99*/ (-103)

◆ LPERR_BADCRC

#define LPERR_BADCRC /*0xFFFFFF95*/ (-107)

◆ LPERR_BUSY

#define LPERR_BUSY /*0xFFFFFF9C*/ (-100)

◆ LPERR_CMDRD

#define LPERR_CMDRD /*0xFFFFFF9B*/ (-101)

◆ LPERR_CMDWR

#define LPERR_CMDWR /*0xFFFFFF9A*/ (-102)

◆ LPERR_EPCSOVERFULL

#define LPERR_EPCSOVERFULL /*0xFFFFFF96*/ (-106)

◆ LPERR_IMGVERSIZE

#define LPERR_IMGVERSIZE /*0xFFFFFF94*/ (-108)

◆ LPERR_IO1_12_NOT_EMPTY

#define LPERR_IO1_12_NOT_EMPTY /*0xFFFFFF8D*/ (-115)

◆ LPERR_IO2_EMPTY_NOREPROG

#define LPERR_IO2_EMPTY_NOREPROG /*0xFFFFFF92*/ (-110)

◆ LPERR_IO3_NOT_EMPTY

#define LPERR_IO3_NOT_EMPTY /*0xFFFFFF91*/ (-111)

◆ LPERR_IO_NOT_EMPTY

#define LPERR_IO_NOT_EMPTY /*0xFFFFFF8E*/ (-114)

◆ LPERR_MEMALOC

#define LPERR_MEMALOC /*0xFFFFFF97*/ (-105)

◆ LPERR_NOREPROG

#define LPERR_NOREPROG /*0xFFFFFF8F*/ (-113)

◆ LPERR_OK

#define LPERR_OK (1)

◆ LPERR_SUPASS

#define LPERR_SUPASS /*0xFFFFFF93*/ (-109)

◆ LPERR_UNABLECOMMSP

#define LPERR_UNABLECOMMSP /*0xFFFFFF98*/ (-104)

◆ LPERR_WRONG_CPU_MODEL

#define LPERR_WRONG_CPU_MODEL /*0xFFFFFF90*/ (-112)

◆ LUT553_ENTRIES

#define LUT553_ENTRIES 16

◆ MAXCHAN

#define MAXCHAN (64)

◆ MAXDMAPS

#define MAXDMAPS (DQ_MAXDEVN * DQ_MAXSS)

◆ MEMORY_553_DATA_0

#define MEMORY_553_DATA_0 1

◆ MEMORY_553_DATA_1

#define MEMORY_553_DATA_1 2

◆ MEMORY_553_DATA_READY

#define MEMORY_553_DATA_READY 3

◆ MEMORY_553_DATA_SENT

#define MEMORY_553_DATA_SENT 4

◆ MEMORY_553_DATA_XCNG

#define MEMORY_553_DATA_XCNG 5

◆ MEMORY_553_MAJOR

#define MEMORY_553_MAJOR 6

◆ MEMORY_553_MINOR

#define MEMORY_553_MINOR 7

◆ MEMORY_553_VALIDATION

#define MEMORY_553_VALIDATION 0

◆ MPC5200_GPT_100US_PS

#define MPC5200_GPT_100US_PS (6600)

◆ MPC5200_GPT_10US_PS

#define MPC5200_GPT_10US_PS (660)

◆ MPC5200_GPT_1US_PS

#define MPC5200_GPT_1US_PS (66)

◆ PC104_SIMA_BUFSIZE

#define PC104_SIMA_BUFSIZE (16384)

◆ PC104_SIMA_ICB_BUFS

#define PC104_SIMA_ICB_BUFS (4)

◆ PC104_SIMA_ICB_BUFSZ

#define PC104_SIMA_ICB_BUFSZ (768)

◆ PC104_SIMA_RSB_BUFS

#define PC104_SIMA_RSB_BUFS (24)

◆ PC104_SIMA_RSB_BUFSZ

#define PC104_SIMA_RSB_BUFSZ (64)

◆ QD604_DIN_604

#define QD604_DIN_604 0x2000

◆ QD604_DIN_604_INA0

#define QD604_DIN_604_INA0 0

◆ QD604_DIN_604_INA1

#define QD604_DIN_604_INA1 4

◆ QD604_DIN_604_INA2

#define QD604_DIN_604_INA2 8

◆ QD604_DIN_604_INA3

#define QD604_DIN_604_INA3 12

◆ QD604_DIN_604_INB0

#define QD604_DIN_604_INB0 1

◆ QD604_DIN_604_INB1

#define QD604_DIN_604_INB1 5

◆ QD604_DIN_604_INB2

#define QD604_DIN_604_INB2 9

◆ QD604_DIN_604_INB3

#define QD604_DIN_604_INB3 13

◆ QD604_DIN_604_INT0

#define QD604_DIN_604_INT0 3

◆ QD604_DIN_604_INT1

#define QD604_DIN_604_INT1 7

◆ QD604_DIN_604_INT2

#define QD604_DIN_604_INT2 11

◆ QD604_DIN_604_INT3

#define QD604_DIN_604_INT3 15

◆ QD604_DIN_604_INZ0

#define QD604_DIN_604_INZ0 2

◆ QD604_DIN_604_INZ1

#define QD604_DIN_604_INZ1 6

◆ QD604_DIN_604_INZ2

#define QD604_DIN_604_INZ2 10

◆ QD604_DIN_604_INZ3

#define QD604_DIN_604_INZ3 14

◆ QD604_DOUT_604

#define QD604_DOUT_604 0x2004

◆ QD604_DOUT_604_CLK0

#define QD604_DOUT_604_CLK0 1

◆ QD604_DOUT_604_CLK1

#define QD604_DOUT_604_CLK1 3

◆ QD604_DOUT_604_CLK2

#define QD604_DOUT_604_CLK2 5

◆ QD604_DOUT_604_CLK3

#define QD604_DOUT_604_CLK3 7

◆ QD604_DOUT_604_TRIG0

#define QD604_DOUT_604_TRIG0 0

◆ QD604_DOUT_604_TRIG1

#define QD604_DOUT_604_TRIG1 2

◆ QD604_DOUT_604_TRIG2

#define QD604_DOUT_604_TRIG2 4

◆ QD604_DOUT_604_TRIG3

#define QD604_DOUT_604_TRIG3 6

◆ QD604_QDU0E

#define QD604_QDU0E 0x21FC

◆ QD604_QDU0S

#define QD604_QDU0S 0x2100

◆ QD604_QDU1E

#define QD604_QDU1E 0x22FC

◆ QD604_QDU1S

#define QD604_QDU1S 0x2200

◆ QD604_QDU2E

#define QD604_QDU2E 0x23FC

◆ QD604_QDU2S

#define QD604_QDU2S 0x2300

◆ QD604_QDU3E

#define QD604_QDU3E 0x24FC

◆ QD604_QDU3S

#define QD604_QDU3S 0x2400

◆ QD604_QDU_CCR

#define QD604_QDU_CCR 0x08

◆ QD604_QDU_CCR_CM0

#define QD604_QDU_CCR_CM0 24

◆ QD604_QDU_CCR_CM1

#define QD604_QDU_CCR_CM1 25

◆ QD604_QDU_CCR_CM2

#define QD604_QDU_CCR_CM2 26

◆ QD604_QDU_CCR_CM3

#define QD604_QDU_CCR_CM3 27

◆ QD604_QDU_CCR_CRM0

#define QD604_QDU_CCR_CRM0 16

◆ QD604_QDU_CCR_CRM1

#define QD604_QDU_CCR_CRM1 17

◆ QD604_QDU_CCR_CRM2

#define QD604_QDU_CCR_CRM2 18

◆ QD604_QDU_CCR_EB0

#define QD604_QDU_CCR_EB0 12

◆ QD604_QDU_CCR_EB1

#define QD604_QDU_CCR_EB1 13

◆ QD604_QDU_CCR_EB2

#define QD604_QDU_CCR_EB2 14

◆ QD604_QDU_CCR_EC0

#define QD604_QDU_CCR_EC0 28

◆ QD604_QDU_CCR_EC1

#define QD604_QDU_CCR_EC1 29

◆ QD604_QDU_CCR_EC2

#define QD604_QDU_CCR_EC2 30

◆ QD604_QDU_CCR_EC3

#define QD604_QDU_CCR_EC3 31

◆ QD604_QDU_CCR_ENC

#define QD604_QDU_CCR_ENC 22

◆ QD604_QDU_CCR_ES

#define QD604_QDU_CCR_ES 15

◆ QD604_QDU_CCR_QED

#define QD604_QDU_CCR_QED 9

◆ QD604_QDU_CCR_QEM0

#define QD604_QDU_CCR_QEM0 10

◆ QD604_QDU_CCR_QEM1

#define QD604_QDU_CCR_QEM1 11

◆ QD604_QDU_CCR_QESWAP

#define QD604_QDU_CCR_QESWAP 8

◆ QD604_QDU_CCR_TBS0

#define QD604_QDU_CCR_TBS0 19

◆ QD604_QDU_CCR_TBS1

#define QD604_QDU_CCR_TBS1 20

◆ QD604_QDU_CCR_TBS2

#define QD604_QDU_CCR_TBS2 21

◆ QD604_QDU_CCR_TRS

#define QD604_QDU_CCR_TRS 23

◆ QD604_QDU_CR

#define QD604_QDU_CR 0x0C

◆ QD604_QDU_CR0

#define QD604_QDU_CR0 0x24

◆ QD604_QDU_CR1

#define QD604_QDU_CR1 0x28

◆ QD604_QDU_CTR

#define QD604_QDU_CTR 0x04

◆ QD604_QDU_CTR_AIE

#define QD604_QDU_CTR_AIE 30

◆ QD604_QDU_CTR_BIE

#define QD604_QDU_CTR_BIE 29

◆ QD604_QDU_CTR_CLR

#define QD604_QDU_CTR_CLR 24

◆ QD604_QDU_CTR_COE

#define QD604_QDU_CTR_COE 19

◆ QD604_QDU_CTR_COM0

#define QD604_QDU_CTR_COM0 16

◆ QD604_QDU_CTR_COM1

#define QD604_QDU_CTR_COM1 17

◆ QD604_QDU_CTR_COM2

#define QD604_QDU_CTR_COM2 18

◆ QD604_QDU_CTR_DO0IE

#define QD604_QDU_CTR_DO0IE 26

◆ QD604_QDU_CTR_DO1IE

#define QD604_QDU_CTR_DO1IE 25

◆ QD604_QDU_CTR_EN

#define QD604_QDU_CTR_EN 31

◆ QD604_QDU_CTR_GTPE

#define QD604_QDU_CTR_GTPE 14

◆ QD604_QDU_CTR_GTSE

#define QD604_QDU_CTR_GTSE 15

◆ QD604_QDU_CTR_IFE

#define QD604_QDU_CTR_IFE 13

◆ QD604_QDU_CTR_TIE

#define QD604_QDU_CTR_TIE 27

◆ QD604_QDU_CTR_TOE

#define QD604_QDU_CTR_TOE 23

◆ QD604_QDU_CTR_TOM0

#define QD604_QDU_CTR_TOM0 20

◆ QD604_QDU_CTR_TOM1

#define QD604_QDU_CTR_TOM1 21

◆ QD604_QDU_CTR_TOM2

#define QD604_QDU_CTR_TOM2 22

◆ QD604_QDU_CTR_TSM0

#define QD604_QDU_CTR_TSM0 11

◆ QD604_QDU_CTR_TSM1

#define QD604_QDU_CTR_TSM1 12

◆ QD604_QDU_CTR_ZIE

#define QD604_QDU_CTR_ZIE 28

◆ QD604_QDU_FCNTI

#define QD604_QDU_FCNTI 0x3C

◆ QD604_QDU_FDTI

#define QD604_QDU_FDTI 0x44

◆ QD604_QDU_ICR

#define QD604_QDU_ICR 0x4C

◆ QD604_QDU_IDBA

#define QD604_QDU_IDBA 0x14

◆ QD604_QDU_IDBB

#define QD604_QDU_IDBB 0x18

◆ QD604_QDU_IDBT

#define QD604_QDU_IDBT 0x20

◆ QD604_QDU_IDBZ

#define QD604_QDU_IDBZ 0x1C

◆ QD604_QDU_IER

#define QD604_QDU_IER 0x48

◆ QD604_QDU_IFWR

#define QD604_QDU_IFWR 0x40

◆ QD604_QDU_INC

#define QD604_QDU_INC 0x38

◆ QD604_QDU_IR_CPT

#define QD604_QDU_IR_CPT 31

◆ QD604_QDU_IR_CR01

#define QD604_QDU_IR_CR01 29

◆ QD604_QDU_IR_CR0L

#define QD604_QDU_IR_CR0L 30

◆ QD604_QDU_IR_CR1

#define QD604_QDU_IR_CR1 28

◆ QD604_QDU_IR_DIR

#define QD604_QDU_IR_DIR 16

◆ QD604_QDU_IR_HLA

#define QD604_QDU_IR_HLA 26

◆ QD604_QDU_IR_HLB

#define QD604_QDU_IR_HLB 24

◆ QD604_QDU_IR_HLZ

#define QD604_QDU_IR_HLZ 22

◆ QD604_QDU_IR_IFE

#define QD604_QDU_IR_IFE 21

◆ QD604_QDU_IR_IFF

#define QD604_QDU_IR_IFF 19

◆ QD604_QDU_IR_IFH

#define QD604_QDU_IR_IFH 20

◆ QD604_QDU_IR_LHA

#define QD604_QDU_IR_LHA 27

◆ QD604_QDU_IR_LHB

#define QD604_QDU_IR_LHB 25

◆ QD604_QDU_IR_LHZ

#define QD604_QDU_IR_LHZ 23

◆ QD604_QDU_IR_QE

#define QD604_QDU_IR_QE 17

◆ QD604_QDU_IR_TE

#define QD604_QDU_IR_TE 18

◆ QD604_QDU_ISR

#define QD604_QDU_ISR 0x4C

◆ QD604_QDU_LR

#define QD604_QDU_LR 0x10

◆ QD604_QDU_OW

#define QD604_QDU_OW 0x34

◆ QD604_QDU_QED

#define QD604_QDU_QED 0x30

◆ QD604_QDU_STR

#define QD604_QDU_STR 0x00

◆ QD604_QDU_STR_AHL

#define QD604_QDU_STR_AHL 26

◆ QD604_QDU_STR_ALH

#define QD604_QDU_STR_ALH 25

◆ QD604_QDU_STR_BHL

#define QD604_QDU_STR_BHL 24

◆ QD604_QDU_STR_BLH

#define QD604_QDU_STR_BLH 23

◆ QD604_QDU_STR_BUSY

#define QD604_QDU_STR_BUSY 30

◆ QD604_QDU_STR_CR0L

#define QD604_QDU_STR_CR0L 29

◆ QD604_QDU_STR_CR1

#define QD604_QDU_STR_CR1 27

◆ QD604_QDU_STR_CROG

#define QD604_QDU_STR_CROG 28

◆ QD604_QDU_STR_CROL

#define QD604_QDU_STR_CROL 29

◆ QD604_QDU_STR_DIR

#define QD604_QDU_STR_DIR 11

◆ QD604_QDU_STR_EN

#define QD604_QDU_STR_EN 31

◆ QD604_QDU_STR_GTS

#define QD604_QDU_STR_GTS 12

◆ QD604_QDU_STR_IFE

#define QD604_QDU_STR_IFE 17

◆ QD604_QDU_STR_IFF

#define QD604_QDU_STR_IFF 15

◆ QD604_QDU_STR_IFH

#define QD604_QDU_STR_IFH 16

◆ QD604_QDU_STR_QE

#define QD604_QDU_STR_QE 13

◆ QD604_QDU_STR_RQ

#define QD604_QDU_STR_RQ 18

◆ QD604_QDU_STR_TE

#define QD604_QDU_STR_TE 14

◆ QD604_QDU_STR_THL

#define QD604_QDU_STR_THL 20

◆ QD604_QDU_STR_TLH

#define QD604_QDU_STR_TLH 19

◆ QD604_QDU_STR_TOOFAST

#define QD604_QDU_STR_TOOFAST 30

◆ QD604_QDU_STR_ZHL

#define QD604_QDU_STR_ZHL 22

◆ QD604_QDU_STR_ZLH

#define QD604_QDU_STR_ZLH 21

◆ QD604_QDU_TBR

#define QD604_QDU_TBR 0x2C

◆ QD604_QDU_TBR_EN

#define QD604_QDU_TBR_EN 31

◆ QDU_CM_CDN

#define QDU_CM_CDN 1

◆ QDU_CM_CDU

#define QDU_CM_CDU 0

◆ QDU_CM_DC

#define QDU_CM_DC 2

◆ QDU_CM_QE

#define QDU_CM_QE 3

◆ QDU_CM_RTCDN

#define QDU_CM_RTCDN 9

◆ QDU_CM_RTCDU

#define QDU_CM_RTCDU 8

◆ QDU_CM_RTDC

#define QDU_CM_RTDC 0xA

◆ QDU_CM_RTQE

#define QDU_CM_RTQE 0xB

◆ QDU_CM_TCDN

#define QDU_CM_TCDN 5

◆ QDU_CM_TCDU

#define QDU_CM_TCDU 4

◆ QDU_CM_TDC

#define QDU_CM_TDC 6

◆ QDU_CM_TQE

#define QDU_CM_TQE 7

◆ QDU_COM_1X

#define QDU_COM_1X 2

◆ QDU_COM_2X

#define QDU_COM_2X 3

◆ QDU_COM_4X

#define QDU_COM_4X 4

◆ QDU_COM_CR1E

#define QDU_COM_CR1E 1

◆ QDU_COM_CR1G

#define QDU_COM_CR1G 0

◆ QDU_COM_IE

#define QDU_COM_IE 5

◆ QDU_COM_N

#define QDU_COM_N 6

◆ QDU_CRM_CR01

#define QDU_CRM_CR01 1

◆ QDU_CRM_CR10

#define QDU_CRM_CR10 2

◆ QDU_CRM_LR

#define QDU_CRM_LR 0

◆ QDU_CRM_NR

#define QDU_CRM_NR 3

◆ QDU_CRM_OTR

#define QDU_CRM_OTR 4

◆ QDU_EB_NO

#define QDU_EB_NO 0

◆ QDU_EB_RE

#define QDU_EB_RE 1

◆ QDU_EB_RE_HH

#define QDU_EB_RE_HH 5

◆ QDU_EB_RE_HL

#define QDU_EB_RE_HL 4

◆ QDU_EB_RE_LH

#define QDU_EB_RE_LH 3

◆ QDU_EB_RE_LL

#define QDU_EB_RE_LL 2

◆ QDU_EM_CR0

#define QDU_EM_CR0 0

◆ QDU_EM_CR01

#define QDU_EM_CR01 2

◆ QDU_EM_CR1

#define QDU_EM_CR1 1

◆ QDU_EM_IE

#define QDU_EM_IE 3

◆ QDU_EM_INC

#define QDU_EM_INC 5

◆ QDU_EM_INF

#define QDU_EM_INF 6

◆ QDU_EM_TBR

#define QDU_EM_TBR 4

◆ QDU_ES_T

#define QDU_ES_T 1

◆ QDU_ES_Z

#define QDU_ES_Z 0

◆ QDU_QEM_1X

#define QDU_QEM_1X 0

◆ QDU_QEM_2X

#define QDU_QEM_2X 1

◆ QDU_QEM_4X

#define QDU_QEM_4X 2

◆ QDU_TBS_66M

#define QDU_TBS_66M 0

◆ QDU_TBS_SYNC0

#define QDU_TBS_SYNC0 4

◆ QDU_TBS_SYNC1

#define QDU_TBS_SYNC1 5

◆ QDU_TBS_SYNC2

#define QDU_TBS_SYNC2 6

◆ QDU_TBS_SYNC3

#define QDU_TBS_SYNC3 7

◆ QDU_TBS_TRIG

#define QDU_TBS_TRIG 1

◆ QDU_TOM_CR0E

#define QDU_TOM_CR0E 1

◆ QDU_TOM_CR0L

#define QDU_TOM_CR0L 0

◆ QDU_TOM_DIR

#define QDU_TOM_DIR 4

◆ QDU_TOM_EM

#define QDU_TOM_EM 5

◆ QDU_TOM_GTS

#define QDU_TOM_GTS 2

◆ QDU_TOM_STD

#define QDU_TOM_STD 3

◆ QDU_TRS_HW

#define QDU_TRS_HW 1

◆ QDU_TRS_SW

#define QDU_TRS_SW 0

◆ QDU_TSM_NOTS

#define QDU_TSM_NOTS 0

◆ QDU_TSM_TSADD

#define QDU_TSM_TSADD 1

◆ QDU_TSM_TSONLY

#define QDU_TSM_TSONLY 2

◆ SDRAM_ADDRESS

#define SDRAM_ADDRESS (0x00000000)

◆ SET_STS_FLAG

#define SET_STS_FLAG	(	DEV,
		SS,
		FG,
		FLAG
	)	(((pDEVOBJ)(DEV))->status[(SS)&7][FG] \|= FLAG)

◆ SET_STS_FLAGp

#define SET_STS_FLAGp	(	DEV,
		SS,
		FG,
		FLAG
	)	{(((pDEVOBJ)(DEV))->status[(SS)&7][FG] \|= FLAG); _printf("line=%d ss=%d sts=%x\n", __LINE__, SS,((pDEVOBJ)(DEV))->status[SS][FG]);}

◆ SIMA_ADCT_OF

#define SIMA_ADCT_OF (0)

◆ SIMA_CTRL_OF

#define SIMA_CTRL_OF (2)

◆ SIMA_LENG_OF

#define SIMA_LENG_OF (4)

◆ SIMA_OF_SIZE

#define SIMA_OF_SIZE (0x10)

◆ SIMA_OFFS_OF

#define SIMA_OFFS_OF (8)

◆ SIMA_SEGM_OF

#define SIMA_SEGM_OF (10)

◆ SIMA_STAT_OF

#define SIMA_STAT_OF (14)

◆ SIMA_TBUS_OF

#define SIMA_TBUS_OF (6)

◆ SIMA_TIME_OF

#define SIMA_TIME_OF (12)

◆ SL553_CMD_GET_RT

#define SL553_CMD_GET_RT ( C ) (((C)>>11)&31)

◆ SL553_CMD_GET_SA

#define SL553_CMD_GET_SA ( C ) (((C)>>5)&31)

◆ SL553_CMD_GET_TR

#define SL553_CMD_GET_TR ( C ) (((C)>>10)&1)

◆ SL553_CMD_GET_WC

#define SL553_CMD_GET_WC ( C ) ((C)&31)

◆ SL553_CMDWORD_RT

#define SL553_CMDWORD_RT ( C ) (((C)&0xf800)>>11)

◆ SL553_CMDWORD_SA

#define SL553_CMDWORD_SA ( C ) (((C)&0x03e0)>>5)

◆ SL553_CMDWORD_TR

#define SL553_CMDWORD_TR ( C ) (((C)&0x0400)>>10)

◆ SL553_CMDWORD_WC

#define SL553_CMDWORD_WC ( C ) (((C)&0x01f)>>0)

◆ SL553_MEMVAL_ERRI

#define SL553_MEMVAL_ERRI (1L<<29)

◆ SL553_MEMVAL_LB_EN

#define SL553_MEMVAL_LB_EN (1L<<30)

◆ SL553_MEMVAL_MD_IRQ_EN

#define SL553_MEMVAL_MD_IRQ_EN (1L<<26)

◆ SL553_MEMVAL_MD_RX_DW

#define SL553_MEMVAL_MD_RX_DW (1L<<27)

◆ SL553_MEMVAL_MD_RX_EN

#define SL553_MEMVAL_MD_RX_EN (1L<<24)

◆ SL553_MEMVAL_MD_TX_DW

#define SL553_MEMVAL_MD_TX_DW (1L<<28)

◆ SL553_MEMVAL_MD_TX_EN

#define SL553_MEMVAL_MD_TX_EN (1L<<25)

◆ SL553_MEMVAL_RX_EN

#define SL553_MEMVAL_RX_EN (1L<<20)

◆ SL553_MEMVAL_RX_IRQ_EN

#define SL553_MEMVAL_RX_IRQ_EN (1L<<22)

◆ SL553_MEMVAL_RX_WCMAX_LSB

#define SL553_MEMVAL_RX_WCMAX_LSB (1L<<5)

◆ SL553_MEMVAL_RX_WCMAX_MSB

#define SL553_MEMVAL_RX_WCMAX_MSB (1L<<9)

◆ SL553_MEMVAL_RX_WCMIN_LSB

#define SL553_MEMVAL_RX_WCMIN_LSB (1L<<0)

◆ SL553_MEMVAL_RX_WCMIN_MSB

#define SL553_MEMVAL_RX_WCMIN_MSB (1L<<4)

◆ SL553_MEMVAL_RXEN

#define SL553_MEMVAL_RXEN (1L<<20)

◆ SL553_MEMVAL_TX_EN

#define SL553_MEMVAL_TX_EN (1L<<21)

◆ SL553_MEMVAL_TX_IRQ_EN

#define SL553_MEMVAL_TX_IRQ_EN (1L<<23)

◆ SL553_MEMVAL_TX_WCMAX_LSB

#define SL553_MEMVAL_TX_WCMAX_LSB (1L<<15)

◆ SL553_MEMVAL_TX_WCMAX_MSB

#define SL553_MEMVAL_TX_WCMAX_MSB (1L<<19)

◆ SL553_MEMVAL_TX_WCMIN_LSB

#define SL553_MEMVAL_TX_WCMIN_LSB (1L<<10)

◆ SL553_MEMVAL_TX_WCMIN_MSB

#define SL553_MEMVAL_TX_WCMIN_MSB (1L<<14)

◆ SL553_MEMVAL_TXEN

#define SL553_MEMVAL_TXEN (1L<<21)

◆ SL553_MJF_BCCB_SEGM

#define SL553_MJF_BCCB_SEGM ( N ) (((N)&0x7f)<<10)

◆ SL553_MJF_DESC_BCCB_A

#define SL553_MJF_DESC_BCCB_A ( N ) ((N&0xf)<<10)

◆ SL553_MJF_DESC_ED

#define SL553_MJF_DESC_ED (1L<<4)

◆ SL553_MJF_DESC_EN

#define SL553_MJF_DESC_EN (1L<<8)

◆ SL553_MJF_DESC_EN_SWAP

#define SL553_MJF_DESC_EN_SWAP (1L<<5)

◆ SL553_MJF_DESC_IRQ

#define SL553_MJF_DESC_IRQ (1L<<6)

◆ SL553_MJF_DESC_LINK

#define SL553_MJF_DESC_LINK (1L<<9)

◆ SL553_MJF_DESC_MRF

#define SL553_MJF_DESC_MRF ( N ) ((N)&0xf)

◆ SL553_MJF_DESC_OT

#define SL553_MJF_DESC_OT (1L<<7)

◆ SL553_MNF_BCCB_OFFS

#define SL553_MNF_BCCB_OFFS ( N ) (((N)&0xf)<<10)

◆ SL553_MNF_BLOCK0

#define SL553_MNF_BLOCK0 (1L<<0)

◆ SL553_MNF_BLOCK1

#define SL553_MNF_BLOCK1 (1L<<1)

◆ SL553_MNF_DESC_BCCB_A

#define SL553_MNF_DESC_BCCB_A ( N ) ((N&0xff)<<10)

◆ SL553_MNF_DESC_CB

#define SL553_MNF_DESC_CB (1L<<6)

◆ SL553_MNF_DESC_ED

#define SL553_MNF_DESC_ED (1L<<4)

◆ SL553_MNF_DESC_EN

#define SL553_MNF_DESC_EN (1L<<8)

◆ SL553_MNF_DESC_ERR

#define SL553_MNF_DESC_ERR (1L<<3)

◆ SL553_MNF_DESC_ERRC0

#define SL553_MNF_DESC_ERRC0 (1L<<0)

◆ SL553_MNF_DESC_ERRC2

#define SL553_MNF_DESC_ERRC2 (1L<<2)

◆ SL553_MNF_DESC_OT

#define SL553_MNF_DESC_OT (1L<<7)

◆ SL553_MNF_DESC_RR

#define SL553_MNF_DESC_RR (1L<<5)

◆ SL553_MODE_ENABLE

#define SL553_MODE_ENABLE 1

◆ SL553_PORT_BCGT_CMD

#define SL553_PORT_BCGT_CMD ( N ) (((N)&0xf)<<28)

◆ SL553_PORT_BCGT_CMD_BCB_BCB

#define SL553_PORT_BCGT_CMD_BCB_BCB (2L<<28)

◆ SL553_PORT_BCGT_CMD_BCB_MNF

#define SL553_PORT_BCGT_CMD_BCB_MNF (4L<<28)

◆ SL553_PORT_BCGT_CMD_BCB_NORET

#define SL553_PORT_BCGT_CMD_BCB_NORET (0L<<28)

◆ SL553_PORT_BCGT_CMD_MNF_BCB

#define SL553_PORT_BCGT_CMD_MNF_BCB (3L<<28)

◆ SL553_PORT_BCGT_CMD_MNF_MNF

#define SL553_PORT_BCGT_CMD_MNF_MNF (5L<<28)

◆ SL553_PORT_BCGT_CMD_MNF_NORET

#define SL553_PORT_BCGT_CMD_MNF_NORET (1L<<28)

◆ SL553_PORT_BCGT_MJFD

#define SL553_PORT_BCGT_MJFD ( N ) (((N)&0xff)<<0)

◆ SL553_PORT_BCGT_MNFD

#define SL553_PORT_BCGT_MNFD ( N ) (((N)&0xff)<<8)

◆ SL553_PORT_BCPOS_CUR_BLOCK

#define SL553_PORT_BCPOS_CUR_BLOCK ( N ) (((N)>>15)&0x1)

◆ SL553_PORT_BCPOS_CUR_MJFD

#define SL553_PORT_BCPOS_CUR_MJFD ( N ) (((N)>>0)&0xff)

◆ SL553_PORT_BCPOS_CUR_MNFD

#define SL553_PORT_BCPOS_CUR_MNFD ( N ) (((N)>>8)&0x7f)

◆ SL553_PORT_BCPOS_GET_GMJFD

#define SL553_PORT_BCPOS_GET_GMJFD ( N ) (((N)>>16)&0xff)

◆ SL553_PORT_BCPOS_GET_GMNFD

#define SL553_PORT_BCPOS_GET_GMNFD ( N ) (((N)>>24)&0xff)

◆ SL553_PORT_BCPOS_GP

#define SL553_PORT_BCPOS_GP (1L<<31)

◆ SL553_PORT_BCSTS_BAD

#define SL553_PORT_BCSTS_BAD (1L<<10)

◆ SL553_PORT_BCSTS_BCO

#define SL553_PORT_BCSTS_BCO (1L<<8)

◆ SL553_PORT_BCSTS_BIR

#define SL553_PORT_BCSTS_BIR (1L<<12)

◆ SL553_PORT_BCSTS_BRF

#define SL553_PORT_BCSTS_BRF (1L<<0)

◆ SL553_PORT_BCSTS_BSY

#define SL553_PORT_BCSTS_BSY (1L<<31)

◆ SL553_PORT_BCSTS_BTO

#define SL553_PORT_BCSTS_BTO (1L<<11)

◆ SL553_PORT_BCSTS_BWB

#define SL553_PORT_BCSTS_BWB (1L<<9)

◆ SL553_PORT_BCSTS_DSC

#define SL553_PORT_BCSTS_DSC ( S ) (((S)&0xff0000)>>16)

◆ SL553_PORT_BCSTS_DSC0

#define SL553_PORT_BCSTS_DSC0 (1L<<16)

◆ SL553_PORT_BCSTS_DSC7

#define SL553_PORT_BCSTS_DSC7 (1L<<23)

◆ SL553_PORT_BCSTS_HBT

#define SL553_PORT_BCSTS_HBT (1L<<7)

◆ SL553_PORT_BCSTS_MBRF

#define SL553_PORT_BCSTS_MBRF (1L<<2)

◆ SL553_PORT_BCSTS_MF

#define SL553_PORT_BCSTS_MF (1L<<4)

◆ SL553_PORT_BCSTS_MRBF

#define SL553_PORT_BCSTS_MRBF (1L<<3)

◆ SL553_PORT_BCSTS_MRF

#define SL553_PORT_BCSTS_MRF ( S ) (((S)&0xf000000)>>24)

◆ SL553_PORT_BCSTS_MRF0

#define SL553_PORT_BCSTS_MRF0 (1L<<24)

◆ SL553_PORT_BCSTS_MRF3

#define SL553_PORT_BCSTS_MRF3 (1L<<27)

◆ SL553_PORT_BCSTS_MTD

#define SL553_PORT_BCSTS_MTD (1L<<6)

◆ SL553_PORT_BCSTS_RBF

#define SL553_PORT_BCSTS_RBF (1L<<1)

◆ SL553_PORT_BCSTS_RSV28

#define SL553_PORT_BCSTS_RSV28 (1L<<28)

◆ SL553_PORT_BCSTS_RSV29

#define SL553_PORT_BCSTS_RSV29 (1L<<29)

◆ SL553_PORT_BCSTS_RSV30

#define SL553_PORT_BCSTS_RSV30 (1L<<30)

◆ SL553_PORT_BCSTS_RTR

#define SL553_PORT_BCSTS_RTR (1L<<5)

◆ SL553_PORT_BCSWAP_MNF

#define SL553_PORT_BCSWAP_MNF ( MASK ) ((MASK)&0xffff)

◆ SL553_RECEIVE

#define SL553_RECEIVE 0

◆ SL553_RT_CFG0_BSRE

#define SL553_RT_CFG0_BSRE (1L<<2)

◆ SL553_RT_CFG0_BSY

#define SL553_RT_CFG0_BSY (1L<<3)

◆ SL553_RT_CFG0_M0DIS

#define SL553_RT_CFG0_M0DIS (1L<<9)

◆ SL553_RT_CFG0_M0DIST

#define SL553_RT_CFG0_M0DIST (1L<<11)

◆ SL553_RT_CFG0_M1553A

#define SL553_RT_CFG0_M1553A (1L<<7)

◆ SL553_RT_CFG0_M1DIS

#define SL553_RT_CFG0_M1DIS (1L<<8)

◆ SL553_RT_CFG0_M1DIST

#define SL553_RT_CFG0_M1DIST (1L<<10)

◆ SL553_RT_CFG0_RSTD

#define SL553_RT_CFG0_RSTD (1L<<6)

◆ SL553_RT_CFG0_SF

#define SL553_RT_CFG0_SF (1L<<4)

◆ SL553_RT_CFG0_SR

#define SL553_RT_CFG0_SR (1L<<1)

◆ SL553_RT_CFG0_TF

#define SL553_RT_CFG0_TF (1L<<5)

◆ SL553_RT_DEFERRED

#define SL553_RT_DEFERRED (1L<<1)

◆ SL553_RT_DIS_MD_RST

#define SL553_RT_DIS_MD_RST (1L<<2)

◆ SL553_TRANSMIT

#define SL553_TRANSMIT 1

◆ SL553_TX_COMMAND

#define SL553_TX_COMMAND	(	RT,
		TR,
		SA,
		WC
	)	(SL553_TXFW_WT\|(((RT)&31)<<11)\|(((TR)&1)<<10)\|(((SA)&31)<<5)\|(((WC)&31)<<0))

◆ SL553_TX_DATA

#define SL553_TX_DATA ( D ) ((D)&0xffff)

◆ SL553_TX_STATUS

#define SL553_TX_STATUS	(	RT,
		ME,
		I,
		SR,
		BC,
		BSY,
		SS,
		DBA,
		TF
	)	(SL553_TXFW_WT\|(((RT)&31)<<11)\|(((ME)&1)<<10)\|(((I)&1)<<9)\|(((SR)&1)<<8)\|(((BC)&1)<<4)\|(((BSY)&1)<<3)\|(((SS)&1)<<2)\|(((DBA)&1)<<1)\|(((TF)&1)<<0))

◆ SL553_TXFW_708_WORD

#define SL553_TXFW_708_WORD	(	CODE,
		DLY,
		DATA
	)	(SL553_TXFW_WORD(DLY, DATA)\|UEI1553_ERR_CODE(CODE))

◆ SL553_TXFW_BUSA

#define SL553_TXFW_BUSA (1L<<28)

◆ SL553_TXFW_BUSB

#define SL553_TXFW_BUSB (0L<<28)

◆ SL553_TXFW_DLY

#define SL553_TXFW_DLY (1L<<29)

◆ SL553_TXFW_ERR_WORD

#define SL553_TXFW_ERR_WORD	(	CODE,
		DLY,
		DATA
	)	(SL553_TXFW_WORD(DLY, DATA)\|UEI1553_ERR_CODE(CODE))

◆ SL553_TXFW_PAR

#define SL553_TXFW_PAR (1L<<31)

◆ SL553_TXFW_uSDLY

#define SL553_TXFW_uSDLY ( uS ) (SL553_TXFW_DLY|((uS)&0xfffffff))

◆ SL553_TXFW_WORD

#define SL553_TXFW_WORD	(	DLY,
		DATA
	)	((((DLY)&0xfff)<<16) \| ((DATA)&0xf000ffff))

◆ SL553_TXFW_WT

#define SL553_TXFW_WT (1L<<30)

◆ SL553_VALID_W

#define SL553_VALID_W	(	RMIN,
		RMAX,
		TMIN,
		TMAX,
		FLAGS
	)	((((RMIN)&0x1f)<<0)\|(((RMAX)&0x1f)<<5)\|(((TMIN)&0x1f)<<10)\|(((TMAX)&0x1f)<<15)\|((FLAGS)&0xfff00000))

◆ SS_DIR_MASK

#define SS_DIR_MASK (0x1)

◆ STS_FW

#define STS_FW (2)

◆ STS_FW_BAD_CONFIG

#define STS_FW_BAD_CONFIG (1UL<<7)

◆ STS_FW_BAD_CONFIG_MASK

#define STS_FW_BAD_CONFIG_MASK (STS_FW_CLK_OOR | STS_FW_BUF_SCANS_PER_INT | STS_FW_BUF_SAMPS_PER_PKT | STS_FW_BUF_RING_SZ | STS_FW_BUF_PREBUF_SZ)

◆ STS_FW_BAD_OPER

#define STS_FW_BAD_OPER (1UL<<19)

◆ STS_FW_BUF_OVER

#define STS_FW_BUF_OVER (1UL<<8)

◆ STS_FW_BUF_PREBUF_SZ

#define STS_FW_BUF_PREBUF_SZ (1UL<<6)

◆ STS_FW_BUF_RING_SZ

#define STS_FW_BUF_RING_SZ (1UL<<5)

◆ STS_FW_BUF_SAMPS_PER_PKT

#define STS_FW_BUF_SAMPS_PER_PKT (1UL<<4)

◆ STS_FW_BUF_SCANS_PER_INT

#define STS_FW_BUF_SCANS_PER_INT (1UL<<3)

◆ STS_FW_BUF_UNDER

#define STS_FW_BUF_UNDER (1UL<<9)

◆ STS_FW_CHNL_ERR

#define STS_FW_CHNL_ERR (1UL<<2)

◆ STS_FW_CLIO_FAIL

#define STS_FW_CLIO_FAIL (1UL<<15)

◆ STS_FW_CLK_OOR

#define STS_FW_CLK_OOR (1UL<<0)

◆ STS_FW_CONFIG_DONE

#define STS_FW_CONFIG_DONE (1UL<<30)

◆ STS_FW_DIAG_0

#define STS_FW_DIAG_0 (1UL<<3)

◆ STS_FW_DIAG_1

#define STS_FW_DIAG_1 (1UL<<4)

◆ STS_FW_EEPROM_FAIL

#define STS_FW_EEPROM_FAIL (1UL<<12)

◆ STS_FW_GENERAL_FAIL

#define STS_FW_GENERAL_FAIL (1UL<<13)

◆ STS_FW_IO_FAIL

#define STS_FW_IO_FAIL (1UL<<17)

◆ STS_FW_ISO_TIMEOUT

#define STS_FW_ISO_TIMEOUT (1UL<<14)

◆ STS_FW_LAYER_ERR

#define STS_FW_LAYER_ERR (1UL<<20)

◆ STS_FW_LYR_FIFO_OVER

#define STS_FW_LYR_FIFO_OVER (1UL<<10)

◆ STS_FW_LYR_FIFO_UNDER

#define STS_FW_LYR_FIFO_UNDER (1UL<<11)

◆ STS_FW_NO_MEMORY

#define STS_FW_NO_MEMORY (1UL<<18)

◆ STS_FW_OPER_MODE

#define STS_FW_OPER_MODE (1UL<<31)

◆ STS_FW_OUT_FAIL

#define STS_FW_OUT_FAIL (1UL<<16)

◆ STS_FW_OVERLOAD

#define STS_FW_OVERLOAD (1UL<<21)

◆ STS_FW_STICKY

#define STS_FW_STICKY (STS_FW_EEPROM_FAIL|STS_FW_GENERAL_FAIL)

◆ STS_FW_SYNC_ERR

#define STS_FW_SYNC_ERR (1UL<<1)

◆ STS_LOGIC

#define STS_LOGIC (3)

◆ STS_LOGIC_BAD_MASK

◆ STS_LOGIC_CALIBRATING

#define STS_LOGIC_CALIBRATING (1UL<<30)

◆ STS_LOGIC_CLCLK_CLI_ERR

#define STS_LOGIC_CLCLK_CLI_ERR (1UL<<9)

◆ STS_LOGIC_CLCLK_CLO_ERR

#define STS_LOGIC_CLCLK_CLO_ERR (1UL<<8)

◆ STS_LOGIC_CLI_NOT_RUNNING

#define STS_LOGIC_CLI_NOT_RUNNING (1UL<<5)

◆ STS_LOGIC_CLO_NOT_RUNNING

#define STS_LOGIC_CLO_NOT_RUNNING (1UL<<4)

◆ STS_LOGIC_CVCLK_CLI_ERR

#define STS_LOGIC_CVCLK_CLI_ERR (1UL<<7)

◆ STS_LOGIC_CVCLK_CLO_ERR

#define STS_LOGIC_CVCLK_CLO_ERR (1UL<<6)

◆ STS_LOGIC_DC_FAILED

#define STS_LOGIC_DC_FAILED (1UL<<1)

◆ STS_LOGIC_DC_OOR

#define STS_LOGIC_DC_OOR (1UL<<0)

◆ STS_LOGIC_NO_REPORTING

#define STS_LOGIC_NO_REPORTING (1UL<<31)

◆ STS_LOGIC_STICKY

#define STS_LOGIC_STICKY (STS_LOGIC_NO_REPORTING|STS_LOGIC_CALIBRATING)

◆ STS_LOGIC_TRIG_START

#define STS_LOGIC_TRIG_START (1UL<<2)

◆ STS_LOGIC_TRIG_STOP

#define STS_LOGIC_TRIG_STOP (1UL<<3)

◆ STS_POST

#define STS_POST (1)

◆ STS_POST_BUSFAIL_ADDR

#define STS_POST_BUSFAIL_ADDR (1L<<9)

◆ STS_POST_BUSFAIL_DATA

#define STS_POST_BUSFAIL_DATA (1L<<8)

◆ STS_POST_BUSTEST_FAILED

#define STS_POST_BUSTEST_FAILED (1L<<7)

◆ STS_POST_DC24

#define STS_POST_DC24 (1L<<5)

◆ STS_POST_DCCORE

#define STS_POST_DCCORE (1L<<6)

◆ STS_POST_EEPROM_FAIL

#define STS_POST_EEPROM_FAIL (1L<<1)

◆ STS_POST_FLASH_FAILED

#define STS_POST_FLASH_FAILED (1L<<3)

◆ STS_POST_LAYER_FAILED

#define STS_POST_LAYER_FAILED (1L<<2)

◆ STS_POST_MEM_FAIL

#define STS_POST_MEM_FAIL (1L<<0)

◆ STS_POST_OVERCURRENT

#define STS_POST_OVERCURRENT (1L<<11)

◆ STS_POST_OVERHEAT

#define STS_POST_OVERHEAT (1L<<10)

◆ STS_POST_RESET_FAILED

#define STS_POST_RESET_FAILED (1L<<12)

◆ STS_POST_SDCARD_FAILED

#define STS_POST_SDCARD_FAILED (1L<<4)

◆ STS_POST_STICKY

#define STS_POST_STICKY (STS_POST_MEM_FAIL|STS_POST_BUSTEST_FAILED|STS_POST_BUSFAIL_DATA|STS_POST_BUSFAIL_ADDR)

◆ STS_POST_UNRECOG_LAYER

#define STS_POST_UNRECOG_LAYER (1L<<13)

◆ STS_STATE

#define STS_STATE (0)

◆ STS_STATE_STICKY

#define STS_STATE_STICKY (0)

◆ STS_STATE_TS_INS

#define STS_STATE_TS_INS	(	S,
		TS
	)	((S & 0xffff00ff)\|((TS<<8) & 0xff00))

◆ STS_STATE_TS_SH

#define STS_STATE_TS_SH 8

◆ TRLISTSZ

#define TRLISTSZ 256

◆ UDP_HDR_OFFSET

#define UDP_HDR_OFFSET (ETH_HDR_SIZE + IP_HDR_SIZE)

◆ UDP_HDR_SIZE

#define UDP_HDR_SIZE (8)

◆ UEI1553_D0

#define UEI1553_D0 (1<<0)

◆ UEI1553_D15

#define UEI1553_D15 (1<<15)

◆ UEI1553_DLY0

#define UEI1553_DLY0 (1<<0)

◆ UEI1553_DLY28

#define UEI1553_DLY28 (1<<28)

◆ UEI1553_DLYUS

#define UEI1553_DLYUS (1<<29)

◆ UEI1553_ERR_708_CSYNC

#define UEI1553_ERR_708_CSYNC 0xe

◆ UEI1553_ERR_708_DATA

#define UEI1553_ERR_708_DATA 0xf

◆ UEI1553_ERR_708_DSYNC

#define UEI1553_ERR_708_DSYNC 0xd

◆ UEI1553_ERR_CODE

#define UEI1553_ERR_CODE ( N ) (((N)&0xf)<<25)

◆ UEI1553_ERR_DED

#define UEI1553_ERR_DED 0x8

◆ UEI1553_ERR_DNE

#define UEI1553_ERR_DNE 0x4

◆ UEI1553_ERR_DPE

#define UEI1553_ERR_DPE 0x3

◆ UEI1553_ERR_NE

#define UEI1553_ERR_NE 0x0

◆ UEI1553_ERR_SED

#define UEI1553_ERR_SED 0x7

◆ UEI1553_ERR_SNE

#define UEI1553_ERR_SNE 0x2

◆ UEI1553_ERR_SPE

#define UEI1553_ERR_SPE 0x1

◆ UEI1553_ERR_TFB

#define UEI1553_ERR_TFB 0x6

◆ UEI1553_ERR_TMB

#define UEI1553_ERR_TMB 0x5

◆ UEI1553_GAP0

#define UEI1553_GAP0 (1<<16)

◆ UEI1553_GAP12

#define UEI1553_GAP12 (1<<28)

◆ UEI1553_GAP_708CS

#define UEI1553_GAP_708CS 0xE

◆ UEI1553_GAP_708D

#define UEI1553_GAP_708D 0xD

◆ UEI1553_GAP_708DS

#define UEI1553_GAP_708DS 0xF

◆ UEI1553_GAP_GET

#define UEI1553_GAP_GET ( N ) (((N)&0x1fff)>>16)

◆ UEI1553_GAP_GET708

#define UEI1553_GAP_GET708 ( N ) (((N)&0xf)>>26)

◆ UEI1553_PE

#define UEI1553_PE (1<<31)

◆ UEI1553_TYPE

#define UEI1553_TYPE (1<<30)

Typedef Documentation

◆ DQGETPRM

typedef struct DQSETPRM DQGETPRM

◆ DQPKT

typedef struct DQPKT DQPKT

◆ pBCCB_Block

typedef struct BCCB_Block * pBCCB_Block

◆ pBCCB_Control

typedef struct BCCB_Control * pBCCB_Control

◆ pBCCB_Status

typedef struct BCCB_Status * pBCCB_Status

◆ pCAL_DAC_SET_211

typedef struct CAL_DAC_SET_211 * pCAL_DAC_SET_211

◆ pCAL_DAC_SET_217

typedef struct CAL_DAC_SET_217 * pCAL_DAC_SET_217

◆ pCAL_DAC_SET_EXT_211

typedef struct CAL_DAC_SET_EXT_211 * pCAL_DAC_SET_EXT_211

◆ pDEVEEPROM_2000_

typedef struct DEVEEPROM_2000_ * pDEVEEPROM_2000_

◆ pDEVEEPROM_201_

typedef struct DEVEEPROM_201_ * pDEVEEPROM_201_

◆ pDEVEEPROM_205_

typedef struct DEVEEPROM_205_ * pDEVEEPROM_205_

◆ pDEVEEPROM_208_

typedef struct DEVEEPROM_208_ * pDEVEEPROM_208_

◆ pDEVEEPROM_211_

typedef struct DEVEEPROM_211_ * pDEVEEPROM_211_

◆ pDEVEEPROM_217_

typedef struct DEVEEPROM_217_ * pDEVEEPROM_217_

◆ pDEVEEPROM_224_

typedef struct DEVEEPROM_224_ * pDEVEEPROM_224_

◆ pDEVEEPROM_225_

typedef struct DEVEEPROM_225_ * pDEVEEPROM_225_

◆ pDEVEEPROM_254_

typedef struct DEVEEPROM_254_ * pDEVEEPROM_254_

◆ pDEVEEPROM_255_

typedef struct DEVEEPROM_255_ * pDEVEEPROM_255_

◆ pDEVEEPROM_301_

typedef struct DEVEEPROM_301_ * pDEVEEPROM_301_

◆ pDEVEEPROM_332_

typedef struct DEVEEPROM_332_ * pDEVEEPROM_332_

◆ pDEVEEPROM_358_

typedef struct DEVEEPROM_358_ * pDEVEEPROM_358_

◆ pDEVEEPROM_401_

typedef struct DEVEEPROM_401_ * pDEVEEPROM_401_

◆ pDEVEEPROM_403_

typedef struct DEVEEPROM_403_ * pDEVEEPROM_403_

◆ pDEVEEPROM_416_

typedef struct DEVEEPROM_416_ * pDEVEEPROM_416_

◆ pDEVEEPROM_432_

typedef struct DEVEEPROM_432_ * pDEVEEPROM_432_

◆ pDEVEEPROM_448_

typedef struct DEVEEPROM_448_ * pDEVEEPROM_448_

◆ pDEVEEPROM_462_

typedef struct DEVEEPROM_462_ * pDEVEEPROM_462_

◆ pDEVEEPROM_501_

typedef struct DEVEEPROM_501_ * pDEVEEPROM_501_

◆ pDEVEEPROM_503_

typedef struct DEVEEPROM_503_ * pDEVEEPROM_503_

◆ pDEVEEPROM_504_

typedef struct DEVEEPROM_504_ * pDEVEEPROM_504_

◆ pDEVEEPROM_553_

typedef struct DEVEEPROM_553_ * pDEVEEPROM_553_

◆ pDEVEEPROM_566_

typedef struct DEVEEPROM_566_ * pDEVEEPROM_566_

◆ pDEVEEPROM_601_

typedef struct DEVEEPROM_601_ * pDEVEEPROM_601_

◆ pDEVEEPROM_604_

typedef struct DEVEEPROM_604_ * pDEVEEPROM_604_

◆ pDEVEEPROM_801_

typedef struct DEVEEPROM_801_ * pDEVEEPROM_801_

◆ pDEVEEPROM_802_

typedef struct DEVEEPROM_802_ * pDEVEEPROM_802_

◆ pDQ254SetExt

typedef struct DQ254SetExt * pDQ254SetExt

◆ pDQ255SetExt

typedef struct DQ255SetExt * pDQ255SetExt

◆ pDQ553Control

typedef struct DQ553Control * pDQ553Control

◆ pDQ_358CAL_HEAD

typedef struct DQ_358CAL_HEAD * pDQ_358CAL_HEAD

◆ pDQAI225CALDATA

typedef struct DQAI225CALDATA * pDQAI225CALDATA

◆ pDQAXMAP

typedef struct DQAXMAP * pDQAXMAP

◆ pDQBM553Filter

typedef struct DQBM553Filter * pDQBM553Filter

◆ pDQBM553Message

typedef struct DQBM553Message * pDQBM553Message

◆ pDQBM553MessageStor

typedef struct DQBM553MessageStor * pDQBM553MessageStor

◆ pDQBM553RTSAEntry

typedef struct DQBM553RTSAEntry * pDQBM553RTSAEntry

◆ pDQBM553Trigger

typedef struct DQBM553Trigger * pDQBM553Trigger

◆ pDQBURST

typedef struct DQBURST * pDQBURST

◆ pDQCALCHAN_254_

typedef struct DQCALCHAN_254_ * pDQCALCHAN_254_

◆ pDQCALCHAN_255_

typedef struct DQCALCHAN_255_ * pDQCALCHAN_255_

◆ pDQCALSET_104

typedef struct DQCALSET_104 * pDQCALSET_104

◆ pDQCALSET_2000_

typedef struct DQCALSET_2000_ * pDQCALSET_2000_

◆ pDQCALSET_201_

typedef struct DQCALSET_201_ * pDQCALSET_201_

◆ pDQCALSET_205_

typedef struct DQCALSET_205_ * pDQCALSET_205_

◆ pDQCALSET_208_

typedef struct DQCALSET_208_ * pDQCALSET_208_

◆ pDQCALSET_211_

typedef struct DQCALSET_211_ * pDQCALSET_211_

◆ pDQCALSET_217_

typedef struct DQCALSET_217_ * pDQCALSET_217_

◆ pDQCALSET_217_X

typedef struct DQCALSET_217_X * pDQCALSET_217_X

◆ pDQCALSET_224_

typedef struct DQCALSET_224_ * pDQCALSET_224_

◆ pDQCALSET_225_

typedef struct DQCALSET_225_ * pDQCALSET_225_

◆ pDQCALSET_254_

typedef struct DQCALSET_254_ * pDQCALSET_254_

◆ pDQCALSET_255_

typedef struct DQCALSET_255_ * pDQCALSET_255_

◆ pDQCALSET_301_

typedef struct DQCALSET_301_ * pDQCALSET_301_

◆ pDQCALSET_332_

typedef struct DQCALSET_332_ * pDQCALSET_332_

◆ pDQCALSET_333_

typedef struct DQCALSET_333_ * pDQCALSET_333_

◆ pDQCALSET_358_

typedef struct DQCALSET_358_ * pDQCALSET_358_

◆ pDQCALSET_416_

typedef struct DQCALSET_416_ * pDQCALSET_416_

◆ pDQCALSET_432_

typedef struct DQCALSET_432_ * pDQCALSET_432_

◆ pDQCALSET_448_

typedef struct DQCALSET_448_ * pDQCALSET_448_

◆ pDQCALSET_462_

typedef struct DQCALSET_462_ * pDQCALSET_462_

◆ pDQCALSET_601_

typedef struct DQCALSET_601_ * pDQCALSET_601_

◆ pDQCALSET_604_

typedef struct DQCALSET_604_ * pDQCALSET_604_

◆ pDQCALSET_651_

typedef struct DQCALSET_651_ * pDQCALSET_651_

◆ pDQCALSET_801_

typedef struct DQCALSET_801_ * pDQCALSET_801_

◆ pDQCALSET_802_

typedef struct DQCALSET_802_ * pDQCALSET_802_

◆ pDQCALSET_91x_

typedef struct DQCALSET_91x_ * pDQCALSET_91x_

◆ pDQCALSET_EXT_AFOFF_211_

typedef struct DQCALSET_EXT_AFOFF_211_ * pDQCALSET_EXT_AFOFF_211_

◆ pDQCALSET_EXT_AFON_211_

typedef struct DQCALSET_EXT_AFON_211_ * pDQCALSET_EXT_AFON_211_

◆ pDQCALSET_LAYER_

typedef struct DQCALSET_LAYER_ * pDQCALSET_LAYER_

◆ pDQCDU

typedef struct DQCDU * pDQCDU

◆ pDQCFGCH_211

typedef struct DQCFGCH_211 * pDQCFGCH_211

◆ pDQCFGLAYER_211

typedef struct DQCFGLAYER_211 * pDQCFGLAYER_211

◆ pDQCHNL

typedef struct DQCHNL * pDQCHNL

◆ pDQCHNLSET_503_

typedef struct DQCHNLSET_503_ * pDQCHNLSET_503_

◆ pDQCHNLSET_601_

typedef struct DQCHNLSET_601_ * pDQCHNLSET_601_

◆ pDQCHNLSET_604_

typedef struct DQCHNLSET_604_ * pDQCHNLSET_604_

◆ pDQCHNLSET_801_

typedef struct DQCHNLSET_801_ * pDQCHNLSET_801_

◆ pDQCHNLSET_802_

typedef struct DQCHNLSET_802_ * pDQCHNLSET_802_

◆ pDQCLRMEM

typedef struct DQCLRMEM * pDQCLRMEM

◆ pDQCNAMES_104

typedef struct DQCNAMES_104 * pDQCNAMES_104

◆ pDQCNAMES_2000_

typedef struct DQCNAMES_2000_ * pDQCNAMES_2000_

◆ pDQCNAMES_201_

typedef struct DQCNAMES_201_ * pDQCNAMES_201_

◆ pDQCNAMES_205_

typedef struct DQCNAMES_205_ * pDQCNAMES_205_

◆ pDQCNAMES_207_

typedef struct DQCNAMES_207_ * pDQCNAMES_207_

◆ pDQCNAMES_208_

typedef struct DQCNAMES_208_ * pDQCNAMES_208_

◆ pDQCNAMES_211_

typedef struct DQCNAMES_211_ * pDQCNAMES_211_

◆ pDQCNAMES_217_

typedef struct DQCNAMES_217_ * pDQCNAMES_217_

◆ pDQCNAMES_224_

typedef struct DQCNAMES_224_ * pDQCNAMES_224_

◆ pDQCNAMES_225_

typedef struct DQCNAMES_225_ * pDQCNAMES_225_

◆ pDQCNAMES_254_

typedef struct DQCNAMES_254_ * pDQCNAMES_254_

◆ pDQCNAMES_255_

typedef struct DQCNAMES_255_ * pDQCNAMES_255_

◆ pDQCNAMES_301_

typedef struct DQCNAMES_301_ * pDQCNAMES_301_

◆ pDQCNAMES_332_

typedef struct DQCNAMES_332_ * pDQCNAMES_332_

◆ pDQCNAMES_358_

typedef struct DQCNAMES_358_ * pDQCNAMES_358_

◆ pDQCNAMES_401_

typedef struct DQCNAMES_401_ * pDQCNAMES_401_

◆ pDQCNAMES_403_

typedef struct DQCNAMES_403_ * pDQCNAMES_403_

◆ pDQCNAMES_416_

typedef struct DQCNAMES_416_ * pDQCNAMES_416_

◆ pDQCNAMES_432_

typedef struct DQCNAMES_432_ * pDQCNAMES_432_

◆ pDQCNAMES_448_

typedef struct DQCNAMES_448_ * pDQCNAMES_448_

◆ pDQCNAMES_462_

typedef struct DQCNAMES_462_ * pDQCNAMES_462_

◆ pDQCNAMES_501_

typedef struct DQCNAMES_501_ * pDQCNAMES_501_

◆ pDQCNAMES_503_

typedef struct DQCNAMES_503_ * pDQCNAMES_503_

◆ pDQCNAMES_504_

typedef struct DQCNAMES_504_ * pDQCNAMES_504_

◆ pDQCNAMES_508_

typedef struct DQCNAMES_508_ * pDQCNAMES_508_

◆ pDQCNAMES_550_

typedef struct DQCNAMES_550_ * pDQCNAMES_550_

◆ pDQCNAMES_553_

typedef struct DQCNAMES_553_ * pDQCNAMES_553_

◆ pDQCNAMES_566_

typedef struct DQCNAMES_566_ * pDQCNAMES_566_

◆ pDQCNAMES_601_

typedef struct DQCNAMES_601_ * pDQCNAMES_601_

◆ pDQCNAMES_604_

typedef struct DQCNAMES_604_ * pDQCNAMES_604_

◆ pDQCNAMES_651_

typedef struct DQCNAMES_651_ * pDQCNAMES_651_

◆ pDQCNAMES_801_

typedef struct DQCNAMES_801_ * pDQCNAMES_801_

◆ pDQCNAMES_802_

typedef struct DQCNAMES_802_ * pDQCNAMES_802_

◆ pDQCNAMES_90x_

typedef struct DQCNAMES_90x_ * pDQCNAMES_90x_

◆ pDQCNAMES_91x_

typedef struct DQCNAMES_91x_ * pDQCNAMES_91x_

◆ pDQCNAMES_LAYER_

typedef struct DQCNAMES_LAYER_ * pDQCNAMES_LAYER_

◆ pDQCRCINFO

typedef struct DQCRCINFO * pDQCRCINFO

◆ pDQDIO416DATAIN

typedef struct DQDIO416DATAIN * pDQDIO416DATAIN

◆ pDQDIO416DATAOUT

typedef struct DQDIO416DATAOUT * pDQDIO416DATAOUT

◆ pDQDIO432CVTD

typedef struct DQDIO432CVTD * pDQDIO432CVTD

◆ pDQDIO432DATAIN

typedef struct DQDIO432DATAIN * pDQDIO432DATAIN

◆ pDQDIO432DATAOUT

typedef struct DQDIO432DATAOUT * pDQDIO432DATAOUT

◆ pDQDIO432PWM

typedef struct DQDIO432PWM * pDQDIO432PWM

◆ pDQDIO448DATAOUT

typedef struct DQDIO448DATAOUT * pDQDIO448DATAOUT

◆ pDQDIO462DATAIN

typedef struct DQDIO462DATAIN * pDQDIO462DATAIN

◆ pDQDIO462DATAOUT

typedef struct DQDIO462DATAOUT * pDQDIO462DATAOUT

◆ pDQEECMNDEVS

typedef struct DQEECMNDEVS * pDQEECMNDEVS

◆ pDQEVENT

typedef struct DQEVENT * pDQEVENT

◆ pDQEXCAL_358

typedef struct DQEXCAL_358 * pDQEXCAL_358

◆ pDQEXCAL_358_8

typedef struct DQEXCAL_358_8 * pDQEXCAL_358_8

◆ pDQFGC

typedef struct DQFGC * pDQFGC

◆ pDQFIFO

typedef struct DQFIFO * pDQFIFO

◆ pDQGETCFG

typedef struct DQGETCFG * pDQGETCFG

◆ pDQGETCFG_RQ

typedef struct DQGETCFG_RQ * pDQGETCFG_RQ

◆ pDQGETPRM

typedef struct DQSETPRM * pDQGETPRM

◆ pDQINITPRM_2000_

typedef struct DQINITPRM_2000_ * pDQINITPRM_2000_

◆ pDQINITPRM_301_

typedef struct DQINITPRM_301_ * pDQINITPRM_301_

◆ pDQINITPRM_332_

typedef struct DQINITPRM_332_ * pDQINITPRM_332_

◆ pDQINITPRM_358_

typedef struct DQINITPRM_358_ * pDQINITPRM_358_

◆ pDQINITPRM_401_

typedef struct DQINITPRM_401_ * pDQINITPRM_401_

◆ pDQINITPRM_403_

typedef struct DQINITPRM_403_ * pDQINITPRM_403_

◆ pDQINITPRM_416_

typedef struct DQINITPRM_416_ * pDQINITPRM_416_

◆ pDQINITPRM_432_

typedef struct DQINITPRM_432_ * pDQINITPRM_432_

◆ pDQINITPRM_448_

typedef struct DQINITPRM_448_ * pDQINITPRM_448_

◆ pDQINITPRM_462_

typedef struct DQINITPRM_462_ * pDQINITPRM_462_

◆ pDQINITPRM_501_

typedef struct DQINITPRM_501_ * pDQINITPRM_501_

◆ pDQINITPRM_503_

typedef struct DQINITPRM_503_ * pDQINITPRM_503_

◆ pDQINITPRM_504_

typedef struct DQINITPRM_504_ * pDQINITPRM_504_

◆ pDQINITPRM_550_

typedef struct DQINITPRM_550_ * pDQINITPRM_550_

◆ pDQINITPRM_553_

typedef struct DQINITPRM_553_ * pDQINITPRM_553_

◆ pDQINITPRM_566_

typedef struct DQINITPRM_566_ * pDQINITPRM_566_

◆ pDQINITPRM_651_

typedef struct DQINITPRM_651_ * pDQINITPRM_651_

◆ pDQINITPRM_90x_

typedef struct DQINITPRM_90x_ * pDQINITPRM_90x_

◆ pDQINITPRM_91x_

typedef struct DQINITPRM_91x_ * pDQINITPRM_91x_

◆ pDQIOCTL

typedef struct DQIOCTL * pDQIOCTL

◆ pDQMAN

typedef struct DQMAN * pDQMAN

◆ pDQMSG_501

typedef struct DQMSG_501 * pDQMSG_501

◆ pDQMSG_501_L

typedef struct DQMSG_501_L * pDQMSG_501_L

◆ pDQMSG_566

typedef struct DQMSG_566 * pDQMSG_566

◆ pDQMSG_566_L

typedef struct DQMSG_566_L * pDQMSG_566_L

◆ pDQMSG_601

typedef struct DQMSG_601 * pDQMSG_601

◆ pDQMSG_601_L

typedef struct DQMSG_601_L * pDQMSG_601_L

◆ pDQMSG_604

typedef struct DQMSG_604 * pDQMSG_604

◆ pDQMSG_801

typedef struct DQMSG_801 * pDQMSG_801

◆ pDQMSG_802

typedef struct DQMSG_802 * pDQMSG_802

◆ pDQOPMODEPRM_104

typedef struct DQOPMODEPRM_104 * pDQOPMODEPRM_104

◆ pDQOPMODEPRM_2000_

typedef struct DQOPMODEPRM_2000_ * pDQOPMODEPRM_2000_

◆ pDQOPMODEPRM_201_

typedef struct DQOPMODEPRM_201_ * pDQOPMODEPRM_201_

◆ pDQOPMODEPRM_205_

typedef struct DQOPMODEPRM_205_ * pDQOPMODEPRM_205_

◆ pDQOPMODEPRM_208_

typedef struct DQOPMODEPRM_208_ * pDQOPMODEPRM_208_

◆ pDQOPMODEPRM_211_

typedef struct DQOPMODEPRM_211_ * pDQOPMODEPRM_211_

◆ pDQOPMODEPRM_217_

typedef struct DQOPMODEPRM_217_ * pDQOPMODEPRM_217_

◆ pDQOPMODEPRM_224_

typedef struct DQOPMODEPRM_224_ * pDQOPMODEPRM_224_

◆ pDQOPMODEPRM_225_

typedef struct DQOPMODEPRM_225_ * pDQOPMODEPRM_225_

◆ pDQOPMODEPRM_254_

typedef struct DQOPMODEPRM_254_ * pDQOPMODEPRM_254_

◆ pDQOPMODEPRM_255_

typedef struct DQOPMODEPRM_255_ * pDQOPMODEPRM_255_

◆ pDQOPMODEPRM_301_

typedef struct DQOPMODEPRM_301_ * pDQOPMODEPRM_301_

◆ pDQOPMODEPRM_332_

typedef struct DQOPMODEPRM_332_ * pDQOPMODEPRM_332_

◆ pDQOPMODEPRM_358_

typedef struct DQOPMODEPRM_358_ * pDQOPMODEPRM_358_

◆ pDQOPMODEPRM_401_

typedef struct DQOPMODEPRM_401_ * pDQOPMODEPRM_401_

◆ pDQOPMODEPRM_403_

typedef struct DQOPMODEPRM_403_ * pDQOPMODEPRM_403_

◆ pDQOPMODEPRM_416_

typedef struct DQOPMODEPRM_416_ * pDQOPMODEPRM_416_

◆ pDQOPMODEPRM_432_

typedef struct DQOPMODEPRM_432_ * pDQOPMODEPRM_432_

◆ pDQOPMODEPRM_448_

typedef struct DQOPMODEPRM_448_ * pDQOPMODEPRM_448_

◆ pDQOPMODEPRM_462_

typedef struct DQOPMODEPRM_462_ * pDQOPMODEPRM_462_

◆ pDQOPMODEPRM_501_

typedef struct DQOPMODEPRM_501_ * pDQOPMODEPRM_501_

◆ pDQOPMODEPRM_503_

typedef struct DQOPMODEPRM_503_ * pDQOPMODEPRM_503_

◆ pDQOPMODEPRM_504_

typedef struct DQOPMODEPRM_504_ * pDQOPMODEPRM_504_

◆ pDQOPMODEPRM_550_

typedef struct DQOPMODEPRM_550_ * pDQOPMODEPRM_550_

◆ pDQOPMODEPRM_553_

typedef struct DQOPMODEPRM_553_ * pDQOPMODEPRM_553_

◆ pDQOPMODEPRM_566_

typedef struct DQOPMODEPRM_566_ * pDQOPMODEPRM_566_

◆ pDQOPMODEPRM_601_

typedef struct DQOPMODEPRM_601_ * pDQOPMODEPRM_601_

◆ pDQOPMODEPRM_604_

typedef struct DQOPMODEPRM_604_ * pDQOPMODEPRM_604_

◆ pDQOPMODEPRM_651_

typedef struct DQOPMODEPRM_651_ * pDQOPMODEPRM_651_

◆ pDQOPMODEPRM_801_

typedef struct DQOPMODEPRM_801_ * pDQOPMODEPRM_801_

◆ pDQOPMODEPRM_802_

typedef struct DQOPMODEPRM_802_ * pDQOPMODEPRM_802_

◆ pDQOPMODEPRM_90x_

typedef struct DQOPMODEPRM_90x_ * pDQOPMODEPRM_90x_

◆ pDQOPMODEPRM_91x_

typedef struct DQOPMODEPRM_91x_ * pDQOPMODEPRM_91x_

◆ pDQOPMODEPRM_LAYER_

typedef struct DQOPMODEPRM_LAYER_ * pDQOPMODEPRM_LAYER_

◆ pDQPKT

typedef struct DQPKT * pDQPKT

◆ pDQPRMFLAGS

typedef struct DQPRMFLAGS * pDQPRMFLAGS

◆ pDQPRMFLAGS_651_

typedef struct DQPRMFLAGS_651_ * pDQPRMFLAGS_651_

◆ pDQPRMFLAGS_91x_

typedef struct DQPRMFLAGS_91x_ * pDQPRMFLAGS_91x_

◆ pDQRBF

typedef struct DQRBF * pDQRBF

◆ pDQRBFDEV

typedef struct DQRBFDEV * pDQRBFDEV

◆ pDQRDCFG

typedef struct DQRDCFG * pDQRDCFG

◆ pDQRDCHNL

typedef struct DQRDCHNL * pDQRDCHNL

◆ pDQSDOWNPRM_2000_

typedef struct DQSDOWNPRM_2000_ * pDQSDOWNPRM_2000_

◆ pDQSDOWNPRM_301_

typedef struct DQSDOWNPRM_301_ * pDQSDOWNPRM_301_

◆ pDQSDOWNPRM_332_

typedef struct DQSDOWNPRM_332_ * pDQSDOWNPRM_332_

◆ pDQSDOWNPRM_358_

typedef struct DQSDOWNPRM_358_ * pDQSDOWNPRM_358_

◆ pDQSDOWNPRM_401_

typedef struct DQSDOWNPRM_401_ * pDQSDOWNPRM_401_

◆ pDQSDOWNPRM_403_

typedef struct DQSDOWNPRM_403_ * pDQSDOWNPRM_403_

◆ pDQSDOWNPRM_416_

typedef struct DQSDOWNPRM_416_ * pDQSDOWNPRM_416_

◆ pDQSDOWNPRM_432_

typedef struct DQSDOWNPRM_432_ * pDQSDOWNPRM_432_

◆ pDQSDOWNPRM_462_

typedef struct DQSDOWNPRM_462_ * pDQSDOWNPRM_462_

◆ pDQSDOWNPRM_501_

typedef struct DQSDOWNPRM_501_ * pDQSDOWNPRM_501_

◆ pDQSDOWNPRM_503_

typedef struct DQSDOWNPRM_503_ * pDQSDOWNPRM_503_

◆ pDQSDOWNPRM_504_

typedef struct DQSDOWNPRM_504_ * pDQSDOWNPRM_504_

◆ pDQSDOWNPRM_550_

typedef struct DQSDOWNPRM_550_ * pDQSDOWNPRM_550_

◆ pDQSDOWNPRM_553_

typedef struct DQSDOWNPRM_553_ * pDQSDOWNPRM_553_

◆ pDQSDOWNPRM_566_

typedef struct DQSDOWNPRM_566_ * pDQSDOWNPRM_566_

◆ pDQSDOWNPRM_651_

typedef struct DQSDOWNPRM_651_ * pDQSDOWNPRM_651_

◆ pDQSDOWNPRM_90x_

typedef struct DQSDOWNPRM_90x_ * pDQSDOWNPRM_90x_

◆ pDQSDOWNPRM_91x_

typedef struct DQSDOWNPRM_91x_ * pDQSDOWNPRM_91x_

◆ pDQSETCAL

typedef struct DQSETCAL * pDQSETCAL

◆ pDQSETCFG

typedef struct DQSETCFG * pDQSETCFG

◆ pDQSETCL

typedef struct DQSETCL * pDQSETCL

◆ pDQSETCLK

typedef struct DQSETCLK * pDQSETCLK

◆ pDQSETCOMM

typedef struct DQSETCOMM * pDQSETCOMM

◆ pDQSETPRM

typedef struct DQSETPRM * pDQSETPRM

◆ pDQSETTRIG

typedef struct DQSETTRIG * pDQSETTRIG

◆ pDQSETTRL

typedef struct DQSETTRL * pDQSETTRL

◆ pDQWMSET_601_

typedef struct DQWMSET_601_ * pDQWMSET_601_

◆ pDQWMSET_801_

typedef struct DQWMSET_801_ * pDQWMSET_801_

◆ pDQWMSET_802_

typedef struct DQWMSET_802_ * pDQWMSET_802_

◆ pDQWRCHNL

typedef struct DQWRCHNL * pDQWRCHNL

◆ pDQWRRD

typedef struct DQWRRD * pDQWRRD

◆ pDQWRRDFIFO

typedef struct DQWRRDFIFO * pDQWRRDFIFO

◆ pDQWRVALM

typedef struct DQWRVALM * pDQWRVALM

◆ pdwDQPKT

typedef struct dwDQPKT * pdwDQPKT

◆ pdwDQWRVALM

typedef struct dwDQWRVALM * pdwDQWRVALM

◆ pEV401_ID

typedef struct EV401_ID * pEV401_ID

◆ pEV501_ID

typedef struct EV501_ID * pEV501_ID

◆ pEV553_ID

typedef struct EV553_ID * pEV553_ID

◆ pEV601_ID

typedef struct EV601_ID * pEV601_ID

◆ pHW_TEST_DATA

typedef struct HW_TEST_DATA * pHW_TEST_DATA

◆ pNBUFSTR

typedef struct NBUFSTR * pNBUFSTR

◆ pSGNLS

typedef struct _SIGS * pSGNLS

◆ pSIMA_MSG_CTRL_STATUS

typedef struct SIMA_MSG_CTRL_STATUS * pSIMA_MSG_CTRL_STATUS

◆ pSL553CUST_LUT

typedef struct SL553CUST_LUT * pSL553CUST_LUT

◆ pSYNCPLL

typedef struct _SYNCPAL * pSYNCPLL

◆ pSYNCRT

typedef struct _SYNCRT * pSYNCRT

◆ pwDQPKT

typedef struct wDQPKT * pwDQPKT

◆ pwDQRDVALM

typedef struct wDQRDVALM * pwDQRDVALM

◆ pwDQWRVALM

typedef struct wDQWRVALM * pwDQWRVALM

◆ pWFMEASURE_254

typedef struct WFMEASURE_254 * pWFMEASURE_254

◆ pWFMEASURE_255

typedef struct WFMEASURE_255 * pWFMEASURE_255

◆ pWFPRM_254

typedef struct WFPRM_254 * pWFPRM_254

◆ pWFPRM_255

typedef struct WFPRM_255 * pWFPRM_255

◆ SGNLS

typedef struct _SIGS SGNLS

◆ SYNCPLL

typedef struct _SYNCPAL SYNCPLL

◆ SYNCRT

typedef struct _SYNCRT SYNCRT

◆ tSL553CommandType

typedef enum _tSL553CommandType tSL553CommandType

Enumeration Type Documentation

◆ _tSL553CommandType

enum _tSL553CommandType

Enumerator
SL553CmdBCRT
SL553CmdRTBC
SL553CmdRTRT
SL553CmdModeTxNoData
SL553CmdModeTxWithData
SL553CmdModeRxWithData
SL553CmdBCRTBroadcast
SL553CmdRTRTBroadcast
SL553CmdModeTxNoDataBroadcast
SL553CmdModeRxWithDataBroadcast
SL553CmdBCRT
SL553CmdRTBC
SL553CmdRTRT
SL553CmdModeTxNoData
SL553CmdModeTxWithData
SL553CmdModeRxWithData
SL553CmdBCRTBroadcast
SL553CmdRTRTBroadcast
SL553CmdModeTxNoDataBroadcast
SL553CmdModeRxWithDataBroadcast
SL553CmdBCRT
SL553CmdRTBC
SL553CmdRTRT
SL553CmdModeTxNoData
SL553CmdModeTxWithData
SL553CmdModeRxWithData
SL553CmdBCRTBroadcast
SL553CmdRTRTBroadcast
SL553CmdModeTxNoDataBroadcast
SL553CmdModeRxWithDataBroadcast

◆ event401_t

enum event401_t

Enumerator
EV401_CLEAR
EV401_DI_CHANGE
EV401_CLEAR
EV401_DI_CHANGE
EV401_CLEAR
EV401_DI_CHANGE

◆ event501_t

enum event501_t

Enumerator
EV501_CLEAR
EV501_TO
EV501_IN_FIFO
EV501_RX
EV501_OUT_FIFO
EV501_TX
EV501_BUS_ERROR
EV501_CLEAR
EV501_TO
EV501_IN_FIFO
EV501_RX
EV501_OUT_FIFO
EV501_TX
EV501_BUS_ERROR
EV501_CLEAR
EV501_TO
EV501_IN_FIFO
EV501_RX
EV501_OUT_FIFO
EV501_TX
EV501_BUS_ERROR

◆ event553_t

enum event553_t

Enumerator
EV553_CLEAR
EV553_NO_ACTIVITY
EV553_IN_FIFO
EV553_OUT_FIFO
EV553_BUS_ERROR
EV553_FSM_ERROR
EV553_BUS_CHANGED
EV553_MD_SHUTDOWN
EV553_MD_SYNCHRONIZE
EV553_MD_RESET
EV553_MD_MISC
EV553_RX
EV553_TX
EV553_BCST_RX
EV553_BCST_TX
EV553_MD
EV553_BC_ERROR
EV553_BC_BUS
EV553_BC_IRQ
EV553_BC_OVERRUN
EV553_BC_CMD_ERR
EV553_BC_HEARTBEAT
EV553_RT_CUST_LUT
EV553_CLEAR
EV553_NO_ACTIVITY
EV553_IN_FIFO
EV553_OUT_FIFO
EV553_BUS_ERROR
EV553_FSM_ERROR
EV553_BUS_CHANGED
EV553_MD_SHUTDOWN
EV553_MD_SYNCHRONIZE
EV553_MD_RESET
EV553_MD_MISC
EV553_RX
EV553_TX
EV553_BCST_RX
EV553_BCST_TX
EV553_MD
EV553_BC_ERROR
EV553_BC_BUS
EV553_BC_IRQ
EV553_BC_OVERRUN
EV553_BC_CMD_ERR
EV553_BC_HEARTBEAT
EV553_RT_CUST_LUT
EV553_CLEAR
EV553_NO_ACTIVITY
EV553_IN_FIFO
EV553_OUT_FIFO
EV553_BUS_ERROR
EV553_FSM_ERROR
EV553_BUS_CHANGED
EV553_MD_SHUTDOWN
EV553_MD_SYNCHRONIZE
EV553_MD_RESET
EV553_MD_MISC
EV553_RX
EV553_TX
EV553_BCST_RX
EV553_BCST_TX
EV553_MD
EV553_BC_ERROR
EV553_BC_BUS
EV553_BC_IRQ
EV553_BC_OVERRUN
EV553_BC_CMD_ERR
EV553_BC_HEARTBEAT
EV553_RT_CUST_LUT

◆ event601_t

enum event601_t

Enumerator
EV601_CLEAR
EV601_COUNT_COMPLETE
EV601_CR0_LESSTHEN
EV601_CR0_EXCEEDED
EV601_CR1_EXCEEDED
EV601_DATA_AVAILABLE
EV601_INP_TRANSITION
EV601_GATE_TRANSITION
EV601_CLEAR
EV601_COUNT_COMPLETE
EV601_CR0_LESSTHEN
EV601_CR0_EXCEEDED
EV601_CR1_EXCEEDED
EV601_DATA_AVAILABLE
EV601_INP_TRANSITION
EV601_GATE_TRANSITION
EV601_CLEAR
EV601_COUNT_COMPLETE
EV601_CR0_LESSTHEN
EV601_CR0_EXCEEDED
EV601_CR1_EXCEEDED
EV601_DATA_AVAILABLE
EV601_INP_TRANSITION
EV601_GATE_TRANSITION

Classes

Macros

Typedefs

Enumerations

Macro Definition Documentation

◆ _CAPS_553_

◆ _CAPS_8000_

◆ AI205_DEFDCR

◆ AI205_DEFTAPS

◆ AI205_FIR_DECRAT_ONLY

◆ AI205_FIR_DEFAULT

◆ AI205_FIR_DISABLED

◆ AI205_FIR_PROGRAMMED

◆ AI205_SHOW_SUM

◆ AI205_STARTRATE

◆ AI208_MAXEXCITE

◆ AI208_MINEXCITE

◆ AI211_CFGAMG_BW_0_1HZ

◆ AI211_CFGAMG_BW_10HZ

◆ AI211_CFGAMG_BW_1HZ

◆ AI211_CFGAMG_BW_DC

◆ AI211_CFGAMG_DEFAULT_STATE

◆ AI211_CFGAMG_FLOFF

◆ AI211_CFGAMG_FMTR

◆ AI211_CFGAMG_GAIN

◆ AI211_CFGAMG_GAIN_MASK

◆ AI211_CFGAMG_IDIS

◆ AI211_CFGAMG_L0COMP

◆ AI211_CFGAMG_L0STATE

◆ AI211_CFGAMG_L1COMP

◆ AI211_CFGAMG_L1STATE

◆ AI211_CFGAMG_M_ADCENFEN

◆ AI211_CFGAMG_OFFSET

◆ AI211_CFGAMG_S_ADCEN

◆ AI211_CLID_FMTR0_ADCD0

◆ AI211_CLID_FMTR0_CHN0

◆ AI211_CLID_FMTR0_INFOO

◆ AI211_CLID_FMTR0_INFOU

◆ AI211_CLID_FMTR0_SMSB0

◆ AI211_FIR_COEFF_LOAD

◆ AI211_FIR_DISABLE

◆ AI211_FIR_ENABLE

◆ AI211_FIR_SET_DECIMATION_RATE

◆ AI211_FIR_SET_DEFAULT

◆ AI211_FIRFIRST_DISABLE

◆ AI211_FIRFIRST_ENABLE

◆ AI211_MAXCVFRQ

◆ AI211_MINCVFRQ_AVG

◆ AI211_SEL_CHAN_0

◆ AI211_SEL_CHAN_1

◆ AI211_SEL_CHAN_2

◆ AI211_SEL_CHAN_3

◆ AI211_SEL_CHAN_ALL

◆ AI217_DEFAULT_CJC_GAIN_CAL

◆ AI217_DEFAULT_CJC_OFFS_CAL

◆ AI217_DEFAULT_GAIN_CAL

◆ AI217_DEFAULT_OFFS_CAL

◆ AI255_CHANONLY_MASK

◆ AI255_GAIN_MASK

◆ AO333_CAL_ADC_EE_ERR

◆ AO333_CAL_ADC_GAIN_RANGE

◆ AO333_CAL_ADC_N9_5_LIMIT

◆ AO333_CAL_ADC_OFFSET_RANGE

◆ AO333_CAL_ADC_RA_HIGH

◆ AO333_CAL_ADC_RA_LOW

◆ AO333_CAL_ADC_RD_FAIL

◆ AO333_CAL_ADC_SUCCESS

◆ AR566_ILE0

◆ AR566_ILE1

◆ AR566_ILE10

◆ AR566_ILE11

◆ AR566_ILE2

◆ AR566_ILE3

◆ AR566_ILE4

◆ AR566_ILE5

◆ AR566_ILE6

◆ AR566_ILE7

◆ AR566_ILE8

◆ AR566_ILE9

◆ AR566_IPE0