|
| #define | HPDI32_API_VERSION 4 |
| |
| #define | HPDI32_VENDOR_ID 0x10B5 /* PLX Technologies */ |
| |
| #define | HPDI32_SUBVENDOR_ID 0x10B5 /* PLX assigned subsystem device id */ |
| |
| #define | HPDI32_DEVICE_ID_32 0x9080 /* PCI9080 PCI interface chip */ |
| |
| #define | HPDI32_SUBSYSTEM_ID_32 0x2400 /* HPDI32 (32-bit PCI interface) */ |
| |
| #define | HPDI32_DEVICE_ID_64 0x9656 /* PCI9656 PCI interface chip */ |
| |
| #define | HPDI32_SUBSYSTEM_ID_64 0x2705 /* HPDI32 (64-bit PCI interface) */ |
| |
| #define | HPDI32_REG_ENCODE(s, o) GSC_REG_ENCODE(GSC_REG_GSC,(s),(o)) |
| |
| #define | HPDI32_FRR HPDI32_REG_ENCODE(4, 0x00) |
| |
| #define | HPDI32_BCR HPDI32_REG_ENCODE(4, 0x04) |
| |
| #define | HPDI32_BSR HPDI32_REG_ENCODE(4, 0x08) |
| |
| #define | HPDI32_TAR HPDI32_REG_ENCODE(4, 0x0C) |
| |
| #define | HPDI32_RAR HPDI32_REG_ENCODE(4, 0x10) |
| |
| #define | HPDI32_FSR HPDI32_REG_ENCODE(4, 0x14) |
| |
| #define | HPDI32_FDR HPDI32_REG_ENCODE(4, 0x18) |
| |
| #define | HPDI32_TSVLCR HPDI32_REG_ENCODE(4, 0x1C) |
| |
| #define | HPDI32_TLVLCR HPDI32_REG_ENCODE(4, 0x20) |
| |
| #define | HPDI32_TLILCR HPDI32_REG_ENCODE(4, 0x24) |
| |
| #define | HPDI32_RSCR HPDI32_REG_ENCODE(4, 0x28) |
| |
| #define | HPDI32_RLCR HPDI32_REG_ENCODE(4, 0x2C) |
| |
| #define | HPDI32_ICR HPDI32_REG_ENCODE(4, 0x30) |
| |
| #define | HPDI32_ISR HPDI32_REG_ENCODE(4, 0x34) |
| |
| #define | HPDI32_TCDR HPDI32_REG_ENCODE(4, 0x38) |
| |
| #define | HPDI32_TFSR HPDI32_REG_ENCODE(4, 0x40) |
| |
| #define | HPDI32_RFSR HPDI32_REG_ENCODE(4, 0x44) |
| |
| #define | HPDI32_TFWR HPDI32_REG_ENCODE(4, 0x48) |
| |
| #define | HPDI32_RFWR HPDI32_REG_ENCODE(4, 0x4C) |
| |
| #define | HPDI32_IELR HPDI32_REG_ENCODE(4, 0x50) |
| |
| #define | HPDI32_IHLR HPDI32_REG_ENCODE(4, 0x54) |
| |
| #define | HPDI32_FRR_FIRMWARE 0x000000FF /* Firmware Version */ |
| |
| #define | HPDI32_FRR_PCB 0x0000FF00 /* Hardware Revision Level */ |
| |
| #define | HPDI32_FRR_SUB_ID 0x00FF0000 /* Special variations of the board. */ |
| |
| #define | HPDI32_FRR_RESERVED 0xFF000000 /* Reserved use */ |
| |
| #define | HPDI32_FRR_FIRMWARE_DECODE(r) GSC_FIELD_DECODE(r, 7, 0) |
| |
| #define | HPDI32_FRR_FIRMWARE_ENCODE(v) GSC_FIELD_ENCODE(v, 7, 0) |
| |
| #define | HPDI32_FRR_PCB_DECODE(r) GSC_FIELD_DECODE(r,15, 8) |
| |
| #define | HPDI32_FRR_PCB_ENCODE(r) GSC_FIELD_ENCODE(r,15, 8) |
| |
| #define | HPDI32_FRR_SUB_ID_DECODE(r) GSC_FIELD_DECODE(r,23,16) |
| |
| #define | HPDI32_FRR_SUB_ID_ENCODE(v) GSC_FIELD_ENCODE(v,23,16) |
| |
| #define | HPDI32_FRR_RESERVED_DECODE(r) GSC_FIELD_DECODE(r,29,24) |
| |
| #define | HPDI32_FRR_RESERVED_ENCODE(v) GSC_FIELD_ENCODE(v,29,24) |
| |
| #define | HPDI32_FRR_RES_PMC_DECODE(r) GSC_FIELD_DECODE(r,24,24) |
| |
| #define | HPDI32_FRR_RES_PMC_ENCODE(v) GSC_FIELD_ENCODE(v,24,24) |
| |
| #define | HPDI32_FRR_RES_FW_64_DECODE(r) GSC_FIELD_DECODE(r,24,24) |
| |
| #define | HPDI32_FRR_RES_FW_64_ENCODE(v) GSC_FIELD_ENCODE(v,24,24) |
| |
| #define | HPDI32_FRR_CONFORM_DECODE(r) GSC_FIELD_DECODE(r,30,30) |
| |
| #define | HPDI32_FRR_CONFORM_ENCODE(v) GSC_FIELD_ENCODE(v,30,30) |
| |
| #define | HPDI32_FRR_FSR_DECODE(r) GSC_FIELD_DECODE(r,31,31) |
| |
| #define | HPDI32_FRR_FSR_ENCODE(v) GSC_FIELD_ENCODE(v,31,31) |
| |
| #define | HPDI32_FRR_PMC 0x01000000 /* 32-bit board: PMC form factor */ |
| |
| #define | HPDI32_FRR_FW_64 0x01000000 /* 64-bit board: 64-bit firmware */ |
| |
| #define | HPDI32_FRR_CONFORMANT 0x40000000 /* Conforms to new spec (below) */ |
| |
| #define | HPDI32_FRR_FSR 0x80000000 /* Feature Set Register is present */ |
| |
| #define | HPDI32_FRR_RESERVED_PMC 0x01 /* 32-bit board: PMC form factor */ |
| |
| #define | HPDI32_FRR_RESERVED_FW_64 0x01 /* 64-bit board: 64-bit firmware */ |
| |
| #define | HPDI32_FRR_SPEC_FIRMWARE 0x000000FF /* Firmware Version */ |
| |
| #define | HPDI32_FRR_SPEC_BOARD_VER 0x0000FF00 /* Customer specific version */ |
| |
| #define | HPDI32_FRR_SPEC_HW_REV 0x00FF0000 /* Hardware Revision Level */ |
| |
| #define | HPDI32_FRR_SPEC_FORM_FACTOR 0x0F000000 /* Hardware Revision Level */ |
| |
| #define | HPDI32_FRR_SPEC_BUS_SIZE 0x10000000 /* 64-bit if set, 32 otherwise */ |
| |
| #define | HPDI32_FRR_SPEC_UNUSED 0x20000000 /* Not used at this time */ |
| |
| #define | HPDI32_FRR_SPEC_CONFORMANT 0x40000000 /* Complies with this layout */ |
| |
| #define | HPDI32_FRR_SPEC_FSR 0x80000000 /* Feature Set Register is present */ |
| |
| #define | HPDI32_FRR_SPEC_FIRMWARE_DECODE(r) GSC_FIELD_DECODE(r, 7, 0) |
| |
| #define | HPDI32_FRR_SPEC_FIRMWARE_ENCODE(v) GSC_FIELD_ENCODE(v, 7, 0) |
| |
| #define | HPDI32_FRR_SPEC_BOARD_VER_DECODE(r) GSC_FIELD_DECODE(r,15, 8) |
| |
| #define | HPDI32_FRR_SPEC_BOARD_VER_ENCODE(v) GSC_FIELD_ENCODE(v,15, 8) |
| |
| #define | HPDI32_FRR_SPEC_HW_REV_DECODE(r) GSC_FIELD_DECODE(r,23,16) |
| |
| #define | HPDI32_FRR_SPEC_HW_REV_ENCODE(v) GSC_FIELD_ENCODE(v,23,16) |
| |
| #define | HPDI32_FRR_SPEC_FF_DECODE(r) GSC_FIELD_DECODE(r,27,24) |
| |
| #define | HPDI32_FRR_SPEC_FF_ENCODE(v) GSC_FIELD_ENCODE(v,27,24) |
| |
| #define | HPDI32_FRR_SPEC_BUS_SIZE_DECODE(r) GSC_FIELD_DECODE(r,28,28) |
| |
| #define | HPDI32_FRR_SPEC_BUS_SIZE_ENCODE(v) GSC_FIELD_ENCODE(v,28,28) |
| |
| #define | HPDI32_FRR_SPEC_UNUSED_DECODE(r) GSC_FIELD_DECODE(r,29,29) |
| |
| #define | HPDI32_FRR_SPEC_UNUSED_ENCODE(v) GSC_FIELD_ENCODE(v,29,29) |
| |
| #define | HPDI32_FRR_SPEC_CONFORM_DECODE(r) GSC_FIELD_DECODE(r,30,30) |
| |
| #define | HPDI32_FRR_SPEC_CONFORM_ENCODE(v) GSC_FIELD_ENCODE(v,30,30) |
| |
| #define | HPDI32_FRR_SPEC_FSR_DECODE(r) GSC_FIELD_DECODE(r,31,31) |
| |
| #define | HPDI32_FRR_SPEC_FSR_ENCODE(v) GSC_FIELD_ENCODE(v,31,31) |
| |
| #define | HPDI32_FRR_SPEC_BOARD_VER_STD 0x00 /* Standard Version */ |
| |
| #define | HPDI32_FRR_SPEC_FF_PCI 0x1 /* PCI */ |
| |
| #define | HPDI32_FRR_SPEC_FF_PMC 0x2 /* PMC */ |
| |
| #define | HPDI32_FRR_SPEC_FF_CPCI 0x3 /* cPCI */ |
| |
| #define | HPDI32_FRR_SPEC_FF_PC104P 0x4 /* PC-104+ */ |
| |
| #define | HPDI32_FRR_SPEC_BUS_SIZE_32 0x0 |
| |
| #define | HPDI32_FRR_SPEC_BUS_SIZE_64 0x1 |
| |
| #define | HPDI32_BCR_DEFAULT 0x00000000 /* Written during initialization */ |
| |
| #define | HPDI32_BCR_BOARD_RESET 0x00000001 /* Needs 10us pause. */ |
| |
| #define | HPDI32_BCR_TX_FIFO_RESET 0x00000002 |
| |
| #define | HPDI32_BCR_RX_FIFO_RESET 0x00000004 |
| |
| #define | HPDI32_BCR_RESERVED_1 0x00000008 |
| |
| #define | HPDI32_BCR_TX_ENABLED 0x00000010 |
| |
| #define | HPDI32_BCR_RX_ENABLED 0x00000020 |
| |
| #define | HPDI32_BCR_TX_AUTO_STOP_NO 0x00000040 /* Tx Start Auto Clear */ |
| |
| #define | HPDI32_BCR_STATUS_VALID 0x00000080 /* Status Valid Mirror: Line Valid Hi on Status Valid Hi */ |
| |
| #define | HPDI32_BCR_TX_START 0x00000100 |
| |
| #define | HPDI32_BCR_TX_THROTTLE 0x00000200 |
| |
| #define | HPDI32_BCR_DMDMA0_DIR 0x00000400 /* Set = Tx, Clear = Rx */ |
| |
| #define | HPDI32_BCR_SING_CYC_DIS 0x00000800 /* Single Cycle Disable */ |
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| #define | HPDI32_BCR_RESERVED_2 0x0000F000 |
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| #define | HPDI32_BCR_C0_MASK 0x01010000 /* Frame Valid/GPIO 6 */ |
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| #define | HPDI32_BCR_C0_FV 0x00000000 |
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| #define | HPDI32_BCR_C0_GPIO 0x01010000 /* It is GPIO if either is set. */ |
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| #define | HPDI32_BCR_C0_IN 0x01000000 |
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| #define | HPDI32_BCR_C0_OUT 0x00010000 |
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| #define | HPDI32_BCR_C0_OUT_H 0x01010000 |
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| #define | HPDI32_BCR_C0_OUT_L 0x00010000 |
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| #define | HPDI32_BCR_C1_MASK 0x02020000 /* Line Valid/GPIO 0 */ |
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| #define | HPDI32_BCR_C1_LV 0x00000000 |
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| #define | HPDI32_BCR_C1_GPIO 0x02020000 /* It is GPIO if either is set. */ |
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| #define | HPDI32_BCR_C1_IN 0x02000000 |
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| #define | HPDI32_BCR_C1_OUT 0x00020000 |
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| #define | HPDI32_BCR_C1_OUT_H 0x02020000 |
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| #define | HPDI32_BCR_C1_OUT_L 0x00020000 |
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| #define | HPDI32_BCR_C2_MASK 0x04040000 /* Status Valid/GPIO 1 */ |
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| #define | HPDI32_BCR_C2_SV 0x00000000 |
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| #define | HPDI32_BCR_C2_GPIO 0x04040000 /* It is GPIO if either is set. */ |
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| #define | HPDI32_BCR_C2_IN 0x04000000 |
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| #define | HPDI32_BCR_C2_OUT 0x00040000 |
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| #define | HPDI32_BCR_C2_OUT_H 0x04040000 |
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| #define | HPDI32_BCR_C2_OUT_L 0x00040000 |
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| #define | HPDI32_BCR_C3_MASK 0x08080000 /* Rx Ready/GPIO 2 */ |
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| #define | HPDI32_BCR_C3_RR 0x00000000 |
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| #define | HPDI32_BCR_C3_GPIO 0x08080000 /* It is GPIO if either is set. */ |
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| #define | HPDI32_BCR_C3_IN 0x08000000 |
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| #define | HPDI32_BCR_C3_OUT 0x00080000 |
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| #define | HPDI32_BCR_C3_OUT_H 0x08080000 |
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| #define | HPDI32_BCR_C3_OUT_L 0x00080000 |
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| #define | HPDI32_BCR_C4_MASK 0x10100000 /* Tx Data Ready/GPIO 3 */ |
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| #define | HPDI32_BCR_C4_TR 0x00000000 |
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| #define | HPDI32_BCR_C4_GPIO 0x10100000 /* It is GPIO if either is set. */ |
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| #define | HPDI32_BCR_C4_IN 0x10000000 |
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| #define | HPDI32_BCR_C4_OUT 0x00100000 |
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| #define | HPDI32_BCR_C4_OUT_H 0x10100000 |
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| #define | HPDI32_BCR_C4_OUT_L 0x00100000 |
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| #define | HPDI32_BCR_C5_MASK 0x20200000 /* Tx Enable/GPIO 4 */ |
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| #define | HPDI32_BCR_C5_TE 0x00000000 |
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| #define | HPDI32_BCR_C5_GPIO 0x20200000 /* It is GPIO if either is set. */ |
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| #define | HPDI32_BCR_C5_IN 0x20000000 |
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| #define | HPDI32_BCR_C5_OUT 0x00200000 |
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| #define | HPDI32_BCR_C5_OUT_H 0x20200000 |
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| #define | HPDI32_BCR_C5_OUT_L 0x00200000 |
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| #define | HPDI32_BCR_C6_MASK 0x40400000 /* Rx Enable/GPIO 5 */ |
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| #define | HPDI32_BCR_C6_RE 0x00000000 |
| |
| #define | HPDI32_BCR_C6_GPIO 0x40400000 /* It is GPIO if either is set. */ |
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| #define | HPDI32_BCR_C6_IN 0x40000000 |
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| #define | HPDI32_BCR_C6_OUT 0x00400000 |
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| #define | HPDI32_BCR_C6_OUT_H 0x40400000 |
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| #define | HPDI32_BCR_C6_OUT_L 0x00400000 |
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| #define | HPDI32_BCR_RESERVED_3 0x00800000 |
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| #define | HPDI32_BCR_TEST_MODE 0x80000000 /* Tx/Rx Tri-Stated when low */ |
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| #define | HPDI32_BSR_D_MASK 0x0000007F |
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| #define | HPDI32_BSR_D0 0x00000001 |
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| #define | HPDI32_BSR_D1 0x00000002 |
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| #define | HPDI32_BSR_D2 0x00000004 |
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| #define | HPDI32_BSR_D3 0x00000008 |
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| #define | HPDI32_BSR_D4 0x00000010 |
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| #define | HPDI32_BSR_D5 0x00000020 |
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| #define | HPDI32_BSR_D6 0x00000040 |
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| #define | HPDI32_BSR_GPIO_0_ HPDI32_BSR_D1 |
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| #define | HPDI32_BSR_GPIO_1_ HPDI32_BSR_D2 |
| |
| #define | HPDI32_BSR_GPIO_2_ HPDI32_BSR_D3 |
| |
| #define | HPDI32_BSR_GPIO_3_ HPDI32_BSR_D4 |
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| #define | HPDI32_BSR_GPIO_4_ HPDI32_BSR_D5 |
| |
| #define | HPDI32_BSR_GPIO_5_ HPDI32_BSR_D6 |
| |
| #define | HPDI32_BSR_GPIO_6_ HPDI32_BSR_D0 |
| |
| #define | HPDI32_BSR_FRAME_VALID_ HPDI32_BSR_D0 |
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| #define | HPDI32_BSR_LINE_VALID_ HPDI32_BSR_D1 |
| |
| #define | HPDI32_BSR_STATUS_VALID_ HPDI32_BSR_D2 |
| |
| #define | HPDI32_BSR_RX_READY_ HPDI32_BSR_D3 |
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| #define | HPDI32_BSR_TX_READY_ HPDI32_BSR_D4 |
| |
| #define | HPDI32_BSR_TX_ENABLED_ HPDI32_BSR_D5 |
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| #define | HPDI32_BSR_RX_ENABLED_ HPDI32_BSR_D6 |
| |
| #define | HPDI32_BSR_TX_ACTIVE 0x00000080 |
| |
| #define | HPDI32_BSR_TX_MASK 0x00000F00 |
| |
| #define | HPDI32_BSR_TX_NOT_EMPTY 0x00000100 |
| |
| #define | HPDI32_BSR_TX_NOT_AE 0x00000200 |
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| #define | HPDI32_BSR_TX_NOT_AF 0x00000400 |
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| #define | HPDI32_BSR_TX_NOT_FULL 0x00000800 |
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| #define | HPDI32_BSR_RX_MASK 0x0000F000 |
| |
| #define | HPDI32_BSR_RX_NOT_EMPTY 0x00001000 |
| |
| #define | HPDI32_BSR_RX_NOT_AE 0x00002000 |
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| #define | HPDI32_BSR_RX_NOT_AF 0x00004000 |
| |
| #define | HPDI32_BSR_RX_NOT_FULL 0x00008000 |
| |
| #define | HPDI32_BSR_BJ0 0x00010000 /* Board/User Jumpers: Not on PMC. */ |
| |
| #define | HPDI32_BSR_BJ1 0x00020000 /* Board/User Jumpers: Not on PMC. */ |
| |
| #define | HPDI32_BSR_PECL 0x00040000 /* PECL transceivers */ |
| |
| #define | HPDI32_BSR_TX_OVERRUN 0x00200000 |
| |
| #define | HPDI32_BSR_RX_UNDER_RUN 0x00400000 |
| |
| #define | HPDI32_BSR_RX_OVERRUN 0x00800000 |
| |
| #define | HPDI32_BSR_BJ_DECODE(r) GSC_FIELD_DECODE(r,17,16) |
| |
| #define | HPDI32_BSR_BJ_ENCODE(v) GSC_FIELD_ENCODE(v,17,16) |
| |
| #define | HPDI32_ALMOST_ENCODE(f, e) |
| |
| #define | HPDI32_DECODE_EMPTY(r) GSC_FIELD_DECODE(r,15,0) |
| |
| #define | HPDI32_DECODE_FULL(r) GSC_FIELD_DECODE(r,31,16) |
| |
| #define | HPDI32_TAR_ENCODE(f, e) HPDI32_ALMOST_ENCODE((f),(e)) |
| |
| #define | HPDI32_TAR_DECODE_EMPTY(r) HPDI32_DECODE_EMPTY((r)) |
| |
| #define | HPDI32_TAR_DECODE_FULL(r) HPDI32_DECODE_FULL((r)) |
| |
| #define | HPDI32_TAR_AE 0x0000FFFF |
| |
| #define | HPDI32_TAR_AE_DEFAULT 0x0000000F |
| |
| #define | HPDI32_TAR_AF 0xFFFF0000 |
| |
| #define | HPDI32_TAR_AF_DEFAULT 0x00100000 |
| |
| #define | HPDI32_RAR_ENCODE(f, e) HPDI32_ALMOST_ENCODE((f),(e)) |
| |
| #define | HPDI32_RAR_DECODE_EMPTY(r) HPDI32_DECODE_EMPTY((r)) |
| |
| #define | HPDI32_RAR_DECODE_FULL(r) HPDI32_DECODE_FULL((r)) |
| |
| #define | HPDI32_RAR_AE 0x0000FFFF |
| |
| #define | HPDI32_RAR_AE_DEFAULT 0x0000000F |
| |
| #define | HPDI32_RAR_AF 0xFFFF0000 |
| |
| #define | HPDI32_RAR_AF_DEFAULT 0x00100000 |
| |
| #define | HPDI32_FSR_MASK 0x000000FF |
| |
| #define | HPDI32_FSR_TFSR_RFSR 0x00000001 |
| |
| #define | HPDI32_FSR_TFWR_RFWR 0x00000002 |
| |
| #define | HPDI32_FSR_IELR_IHLR 0x00000004 |
| |
| #define | HPDI32_FSR_GPIO_0_5 0x00000008 /* Cable Command 1 to 6 */ |
| |
| #define | HPDI32_FSR_DMDMA_CH1 0x00000010 /* Demand Mode DMA on Ch 1? */ |
| |
| #define | HPDI32_FSR_OVR_UNDR_RUN 0x00000020 |
| |
| #define | HPDI32_FSR_GPIO6_TXAS 0x00000040 |
| |
| #define | HPDI32_FSR_SCD 0x00000080 |
| |
| #define | HPDI32_TLILCR_COUNT_MASK 0x0000FFFF |
| |
| #define | HPDI32_TCDR_DIV_MASK 0x0000FFFF |
| |
| #define | HPDI32_ICR_DEFAULT 0x00000000 /* Written during initialization */ |
| |
| #define | HPDI32_IRQ_C0A_ 0x00000001 /* Command 0 Active: Frame Valid Begin/GPIO 6 High */ |
| |
| #define | HPDI32_IRQ_C0I_ 0x00000002 /* Command 0 Inactive: Frame Valid End/GPIO 6 Low */ |
| |
| #define | HPDI32_IRQ_C1_ 0x00000004 /* Command 1: Line Valid/GPIO 0 */ |
| |
| #define | HPDI32_IRQ_C2_ 0x00000008 /* Command 2: Status Valid/GPIO 1 */ |
| |
| #define | HPDI32_IRQ_C3_ 0x00000010 /* Command 3: Rx Ready/GPIO 2 */ |
| |
| #define | HPDI32_IRQ_C4_ 0x00000020 /* Command 4: Tx Ready/GPIO 3 */ |
| |
| #define | HPDI32_IRQ_C5_ 0x00000040 /* Command 5: Tx Enable/GPIO 4 */ |
| |
| #define | HPDI32_IRQ_C6_ 0x00000080 /* Command 6: Rx Enable/GPIO 5 */ |
| |
| #define | HPDI32_IRQ_TX_E 0x00000100 /* Tx FIFO Empty */ |
| |
| #define | HPDI32_IRQ_TX_AE 0x00000200 /* Tx FIFO Almost Empty */ |
| |
| #define | HPDI32_IRQ_TX_AF 0x00000400 /* Tx FIFO Almost Full */ |
| |
| #define | HPDI32_IRQ_TX_F 0x00000800 /* Tx FIFO Full */ |
| |
| #define | HPDI32_IRQ_RX_E 0x00001000 /* Rx FIFO Empty */ |
| |
| #define | HPDI32_IRQ_RX_AE 0x00002000 /* Rx FIFO Almost Empty */ |
| |
| #define | HPDI32_IRQ_RX_AF 0x00004000 /* Rx FIFO Almost Full */ |
| |
| #define | HPDI32_IRQ_RX_F 0x00008000 /* Rx FIFO Full */ |
| |
| #define | HPDI32_IRQ_FVB_ HPDI32_IRQ_C0A_ |
| |
| #define | HPDI32_IRQ_FVE_ HPDI32_IRQ_C0I_ |
| |
| #define | HPDI32_IRQ_LV_ HPDI32_IRQ_C1_ |
| |
| #define | HPDI32_IRQ_SV_ HPDI32_IRQ_C2_ |
| |
| #define | HPDI32_IRQ_RR_ HPDI32_IRQ_C3_ |
| |
| #define | HPDI32_IRQ_TR_ HPDI32_IRQ_C4_ |
| |
| #define | HPDI32_IRQ_TE_ HPDI32_IRQ_C5_ |
| |
| #define | HPDI32_IRQ_RE_ HPDI32_IRQ_C6_ |
| |
| #define | HPDI32_IRQ_GPIO_0_ HPDI32_IRQ_C1_ |
| |
| #define | HPDI32_IRQ_GPIO_1_ HPDI32_IRQ_C2_ |
| |
| #define | HPDI32_IRQ_GPIO_2_ HPDI32_IRQ_C3_ |
| |
| #define | HPDI32_IRQ_GPIO_3_ HPDI32_IRQ_C4_ |
| |
| #define | HPDI32_IRQ_GPIO_4_ HPDI32_IRQ_C5_ |
| |
| #define | HPDI32_IRQ_GPIO_5_ HPDI32_IRQ_C6_ |
| |
| #define | HPDI32_IRQ_GPIO_6H_ HPDI32_IRQ_C0A_ |
| |
| #define | HPDI32_IRQ_GPIO_6L_ HPDI32_IRQ_C0I_ |
| |
| #define | HPDI32_IELR_DEFAULT 0x0000FFFF /* Written during initialization */ |
| |
| #define | HPDI32_IHLR_DEFAULT 0x0000FFFF /* Written during initialization */ |
| |
| #define | HPDI32_CONFIG_GET(h, p, w, g) hpdi32_config((h),(p),(w),GSC_NO_CHANGE,(g)) |
| |
| #define | HPDI32_CONFIG_SET(h, p, w, s) hpdi32_config((h),(p),(w),(s),NULL) |
| |
| #define | HPDI32_CONFIG_SET_GET(h, p, w, s, g) hpdi32_config((h),(p),(w),(s),(g)) |
| |
| #define | HPDI32_CONFIG_ENCODE(g, i) |
| |
| #define | HPDI32_CONFIG_GROUP_DECODE(v) GSC_FIELD_DECODE((v),31,16) |
| |
| #define | HPDI32_CONFIG_INDEX_DECODE(v) GSC_FIELD_DECODE((v),15,0) |
| |
| #define | HPDI32_CONFIG_GROUP_CABLE 0 |
| |
| #define | HPDI32_CONFIG_GROUP_FIFO 1 |
| |
| #define | HPDI32_CONFIG_GROUP_IO 2 |
| |
| #define | HPDI32_CONFIG_GROUP_IRQ 3 |
| |
| #define | HPDI32_CONFIG_GROUP_MISC 4 |
| |
| #define | HPDI32_CONFIG_GROUP_RX 5 |
| |
| #define | HPDI32_CONFIG_GROUP_TX 6 |
| |
| #define | HPDI32_WHICH_RX 0x01 |
| |
| #define | HPDI32_WHICH_TX 0x02 |
| |
| #define | HPDI32_WHICH_TX_RX (HPDI32_WHICH_TX | HPDI32_WHICH_RX) |
| |
| #define | HPDI32_WHICH_TX_RX_AF_AE (HPDI32_WHICH_TX_RX | HPDI32_WHICH_AF_AE) |
| |
| #define | HPDI32_WHICH_AE 0x04 /* Almost Empty */ |
| |
| #define | HPDI32_WHICH_AF 0x08 /* Almost Full */ |
| |
| #define | HPDI32_WHICH_AF_AE (HPDI32_WHICH_AF | HPDI32_WHICH_AE) |
| |
| #define | HPDI32_WHICH_RX_AE (HPDI32_WHICH_RX | HPDI32_WHICH_AE) |
| |
| #define | HPDI32_WHICH_RX_AF (HPDI32_WHICH_RX | HPDI32_WHICH_AF) |
| |
| #define | HPDI32_WHICH_RX_AE_AF (HPDI32_WHICH_RX | HPDI32_WHICH_AF_AE) |
| |
| #define | HPDI32_WHICH_TX_AE (HPDI32_WHICH_TX | HPDI32_WHICH_AE) |
| |
| #define | HPDI32_WHICH_TX_AF (HPDI32_WHICH_TX | HPDI32_WHICH_AF) |
| |
| #define | HPDI32_WHICH_TX_AE_AF (HPDI32_WHICH_TX | HPDI32_WHICH_AF_AE) |
| |
| #define | HPDI32_WHICH_COMMAND_0_ 0x01 |
| |
| #define | HPDI32_WHICH_COMMAND_1_ 0x02 |
| |
| #define | HPDI32_WHICH_COMMAND_2_ 0x04 |
| |
| #define | HPDI32_WHICH_COMMAND_3_ 0x08 |
| |
| #define | HPDI32_WHICH_COMMAND_4_ 0x10 |
| |
| #define | HPDI32_WHICH_COMMAND_5_ 0x20 |
| |
| #define | HPDI32_WHICH_COMMAND_6_ 0x40 |
| |
| #define | HPDI32_WHICH_COMMAND_ALL_ 0x7F |
| |
| #define | HPDI32_WHICH_GPIO_0_ HPDI32_WHICH_COMMAND_1_ |
| |
| #define | HPDI32_WHICH_GPIO_1_ HPDI32_WHICH_COMMAND_2_ |
| |
| #define | HPDI32_WHICH_GPIO_2_ HPDI32_WHICH_COMMAND_3_ |
| |
| #define | HPDI32_WHICH_GPIO_3_ HPDI32_WHICH_COMMAND_4_ |
| |
| #define | HPDI32_WHICH_GPIO_4_ HPDI32_WHICH_COMMAND_5_ |
| |
| #define | HPDI32_WHICH_GPIO_5_ HPDI32_WHICH_COMMAND_6_ |
| |
| #define | HPDI32_WHICH_GPIO_6_ HPDI32_WHICH_COMMAND_0_ |
| |
| #define | HPDI32_WHICH_GPIO_ALL_ HPDI32_WHICH_COMMAND_ALL_ |
| |
| #define | HPDI32_WHICH_FRAME_VALID_ HPDI32_WHICH_COMMAND_0_ |
| |
| #define | HPDI32_WHICH_LINE_VALID_ HPDI32_WHICH_COMMAND_1_ |
| |
| #define | HPDI32_WHICH_STATUS_VALID_ HPDI32_WHICH_COMMAND_2_ |
| |
| #define | HPDI32_WHICH_RX_READY_ HPDI32_WHICH_COMMAND_3_ |
| |
| #define | HPDI32_WHICH_TX_READY_ HPDI32_WHICH_COMMAND_4_ |
| |
| #define | HPDI32_WHICH_TX_ENABLED_ HPDI32_WHICH_COMMAND_5_ |
| |
| #define | HPDI32_WHICH_RX_ENABLED_ HPDI32_WHICH_COMMAND_6_ |
| |
| #define | HPDI32_WHICH_FC_ALL_ HPDI32_WHICH_COMMAND_ALL_ |
| |
| #define | HPDI32_WHICH_FV_ HPDI32_WHICH_FRAME_VALID_ |
| |
| #define | HPDI32_WHICH_LV_ HPDI32_WHICH_LINE_VALID_ |
| |
| #define | HPDI32_WHICH_SV_ HPDI32_WHICH_STATUS_VALID_ |
| |
| #define | HPDI32_WHICH_RR_ HPDI32_WHICH_RX_READY_ |
| |
| #define | HPDI32_WHICH_TR_ HPDI32_WHICH_TX_READY_ |
| |
| #define | HPDI32_WHICH_TE_ HPDI32_WHICH_TX_ENABLED_ |
| |
| #define | HPDI32_WHICH_RE_ HPDI32_WHICH_RX_ENABLED_ |
| |
| #define | HPDI32_WHICH_IRQ_C0A_ 0x0001 /* Cable Command 0/Frame Valid Begin/GPIO 6 */ |
| |
| #define | HPDI32_WHICH_IRQ_C0I_ 0x0002 /* Cable Command 0/Frame Valid End/GPIO 6 */ |
| |
| #define | HPDI32_WHICH_IRQ_C1_ 0x0004 /* Cable Command 1/Line Valid/GPIO 0 */ |
| |
| #define | HPDI32_WHICH_IRQ_C2_ 0x0008 /* Cable Command 2/Status Valid/GPIO 1 */ |
| |
| #define | HPDI32_WHICH_IRQ_C3_ 0x0010 /* Cable Command 3/Rx Ready/GPIO 2 */ |
| |
| #define | HPDI32_WHICH_IRQ_C4_ 0x0020 /* Cable Command 4/Tx Ready/GPIO 3 */ |
| |
| #define | HPDI32_WHICH_IRQ_C5_ 0x0040 /* Cable Command 5/Tx Enable/GPIO 4 */ |
| |
| #define | HPDI32_WHICH_IRQ_C6_ 0x0080 /* Cable Command 6/Rx Enable/GPIO 5 */ |
| |
| #define | HPDI32_WHICH_IRQ_TX_E 0x0100 /* Tx FIFO Empty */ |
| |
| #define | HPDI32_WHICH_IRQ_TX_AE 0x0200 /* Tx FIFO Almost Empty */ |
| |
| #define | HPDI32_WHICH_IRQ_TX_AF 0x0400 /* Tx FIFO Almost Full */ |
| |
| #define | HPDI32_WHICH_IRQ_TX_F 0x0800 /* Tx FIFO Full */ |
| |
| #define | HPDI32_WHICH_IRQ_RX_E 0x1000 /* Rx FIFO Empty */ |
| |
| #define | HPDI32_WHICH_IRQ_RX_AE 0x2000 /* Rx FIFO Almost Empty */ |
| |
| #define | HPDI32_WHICH_IRQ_RX_AF 0x4000 /* Rx FIFO Almost Full */ |
| |
| #define | HPDI32_WHICH_IRQ_RX_F 0x8000 /* Rx FIFO Full */ |
| |
| #define | HPDI32_WHICH_IRQ_ALL 0xFFFF |
| |
| #define | HPDI32_WHICH_IRQ_FVB_ HPDI32_WHICH_IRQ_C0A_ |
| |
| #define | HPDI32_WHICH_IRQ_FVE_ HPDI32_WHICH_IRQ_C0I_ |
| |
| #define | HPDI32_WHICH_IRQ_LV_ HPDI32_WHICH_IRQ_C1_ |
| |
| #define | HPDI32_WHICH_IRQ_SV_ HPDI32_WHICH_IRQ_C2_ |
| |
| #define | HPDI32_WHICH_IRQ_RR_ HPDI32_WHICH_IRQ_C3_ |
| |
| #define | HPDI32_WHICH_IRQ_TR_ HPDI32_WHICH_IRQ_C4_ |
| |
| #define | HPDI32_WHICH_IRQ_TE_ HPDI32_WHICH_IRQ_C5_ |
| |
| #define | HPDI32_WHICH_IRQ_RE_ HPDI32_WHICH_IRQ_C6_ |
| |
| #define | HPDI32_WHICH_IRQ_GPIO_0_ HPDI32_WHICH_IRQ_C1_ |
| |
| #define | HPDI32_WHICH_IRQ_GPIO_1_ HPDI32_WHICH_IRQ_C2_ |
| |
| #define | HPDI32_WHICH_IRQ_GPIO_2_ HPDI32_WHICH_IRQ_C3_ |
| |
| #define | HPDI32_WHICH_IRQ_GPIO_3_ HPDI32_WHICH_IRQ_C4_ |
| |
| #define | HPDI32_WHICH_IRQ_GPIO_4_ HPDI32_WHICH_IRQ_C5_ |
| |
| #define | HPDI32_WHICH_IRQ_GPIO_5_ HPDI32_WHICH_IRQ_C6_ |
| |
| #define | HPDI32_WHICH_IRQ_GPIO_6H_ HPDI32_WHICH_IRQ_C0A_ |
| |
| #define | HPDI32_WHICH_IRQ_GPIO_6L_ HPDI32_WHICH_IRQ_C0I_ |
| |
| #define | HPDI32_CABLE_ENCODE(i) HPDI32_CONFIG_ENCODE(HPDI32_CONFIG_GROUP_CABLE, (i)) |
| |
| #define | HPDI32_CABLE_CLOCK_STATE HPDI32_CABLE_ENCODE(0) /* GET only */ |
| |
| #define | HPDI32_CABLE_COMMAND_MODE HPDI32_CABLE_ENCODE(1) |
| |
| #define | HPDI32_CABLE_COMMAND_STATE HPDI32_CABLE_ENCODE(2) /* GET only */ |
| |
| #define | HPDI32_CABLE_CLOCK_STATE_INACTIVE 0 |
| |
| #define | HPDI32_CABLE_CLOCK_STATE_ACTIVE 1 |
| |
| #define | HPDI32_CABLE_CLOCK_STATE__GET(h, g) HPDI32_CONFIG_GET((h),HPDI32_CABLE_CLOCK_STATE,0,(g)) |
| |
| #define | HPDI32_CABLE_COMMAND_MODE_FLOW_CONTROL 0 /* Values follow BCR bit patterns */ |
| |
| #define | HPDI32_CABLE_COMMAND_MODE_GPIO_IN 2 |
| |
| #define | HPDI32_CABLE_COMMAND_MODE_GPIO_OUT_LOW 1 |
| |
| #define | HPDI32_CABLE_COMMAND_MODE_GPIO_OUT_HI 3 |
| |
| #define | HPDI32_CABLE_COMMAND_MODE_DEFAULT HPDI32_CABLE_COMMAND_MODE_FLOW_CONTROL |
| |
| #define | HPDI32_CABLE_COMMAND_MODE__GET(h, w, g) HPDI32_CONFIG_GET((h),HPDI32_CABLE_COMMAND_MODE,(w),(g)) |
| |
| #define | HPDI32_CABLE_COMMAND_MODE__SET(h, w, s) HPDI32_CONFIG_SET((h),HPDI32_CABLE_COMMAND_MODE,(w),(s)) |
| |
| #define | HPDI32_CABLE_COMMAND_MODE__RESET(h, w) HPDI32_CABLE_COMMAND_MODE__SET((h),(w),HPDI32_CABLE_COMMAND_MODE_DEFAULT) |
| |
| #define | HPDI32_CABLE_COMMAND_MODE__FC(h, w) HPDI32_CABLE_COMMAND_MODE__SET((h),(w),HPDI32_CABLE_COMMAND_MODE_FLOW_CONTROL) |
| |
| #define | HPDI32_CABLE_COMMAND_MODE__GPIO_IN(h, w) HPDI32_CABLE_COMMAND_MODE__SET((h),(w),HPDI32_CABLE_COMMAND_MODE_GPIO_IN) |
| |
| #define | HPDI32_CABLE_COMMAND_MODE__GPIO_LOW(h, w) HPDI32_CABLE_COMMAND_MODE__SET((h),(w),HPDI32_CABLE_COMMAND_MODE_GPIO_OUT_LOW) |
| |
| #define | HPDI32_CABLE_COMMAND_MODE__GPIO_HI(h, w) HPDI32_CABLE_COMMAND_MODE__SET((h),(w),HPDI32_CABLE_COMMAND_MODE_GPIO_OUT_HI) |
| |
| #define | HPDI32_CABLE_COMMAND_MODE__0_GET(h, g) HPDI32_CABLE_COMMAND_MODE__GET(h,HPDI32_WHICH_COMMAND_0_,g) |
| |
| #define | HPDI32_CABLE_COMMAND_MODE__0_SET(h, s) HPDI32_CABLE_COMMAND_MODE__SET(h,HPDI32_WHICH_COMMAND_0_,s) |
| |
| #define | HPDI32_CABLE_COMMAND_MODE__0_RESET(h) HPDI32_CABLE_COMMAND_MODE__0_SET(h,HPDI32_CABLE_COMMAND_MODE_DEFAULT) |
| |
| #define | HPDI32_CABLE_COMMAND_MODE__0_FC(h) HPDI32_CABLE_COMMAND_MODE__FC(h,HPDI32_WHICH_COMMAND_0_) |
| |
| #define | HPDI32_CABLE_COMMAND_MODE__0_IN(h) HPDI32_CABLE_COMMAND_MODE__GPIO_IN(h,HPDI32_WHICH_COMMAND_0_) |
| |
| #define | HPDI32_CABLE_COMMAND_MODE__0_LOW(h) HPDI32_CABLE_COMMAND_MODE__GPIO_LOW(h,HPDI32_WHICH_COMMAND_0_) |
| |
| #define | HPDI32_CABLE_COMMAND_MODE__0_HI(h) HPDI32_CABLE_COMMAND_MODE__GPIO_HI(h,HPDI32_WHICH_COMMAND_0_) |
| |
| #define | HPDI32_CABLE_COMMAND_MODE__1_GET(h, g) HPDI32_CABLE_COMMAND_MODE__GET(h,HPDI32_WHICH_COMMAND_1_,g) |
| |
| #define | HPDI32_CABLE_COMMAND_MODE__1_SET(h, s) HPDI32_CABLE_COMMAND_MODE__SET(h,HPDI32_WHICH_COMMAND_1_,s) |
| |
| #define | HPDI32_CABLE_COMMAND_MODE__1_RESET(h) HPDI32_CABLE_COMMAND_MODE__SET(h,HPDI32_WHICH_COMMAND_1_,HPDI32_CABLE_COMMAND_MODE_DEFAULT) |
| |
| #define | HPDI32_CABLE_COMMAND_MODE__1_FC(h) HPDI32_CABLE_COMMAND_MODE__FC(h,HPDI32_WHICH_COMMAND_1_) |
| |
| #define | HPDI32_CABLE_COMMAND_MODE__1_IN(h) HPDI32_CABLE_COMMAND_MODE__GPIO_IN(h,HPDI32_WHICH_COMMAND_1_) |
| |
| #define | HPDI32_CABLE_COMMAND_MODE__1_LOW(h) HPDI32_CABLE_COMMAND_MODE__GPIO_LOW(h,HPDI32_WHICH_COMMAND_1_) |
| |
| #define | HPDI32_CABLE_COMMAND_MODE__1_HI(h) HPDI32_CABLE_COMMAND_MODE__GPIO_HI(h,HPDI32_WHICH_COMMAND_1_) |
| |
| #define | HPDI32_CABLE_COMMAND_MODE__2_GET(h, g) HPDI32_CABLE_COMMAND_MODE__GET(h,HPDI32_WHICH_COMMAND_2_,g) |
| |
| #define | HPDI32_CABLE_COMMAND_MODE__2_SET(h, s) HPDI32_CABLE_COMMAND_MODE__SET(h,HPDI32_WHICH_COMMAND_2_,s) |
| |
| #define | HPDI32_CABLE_COMMAND_MODE__2_RESET(h) HPDI32_CABLE_COMMAND_MODE__SET(h,HPDI32_WHICH_COMMAND_2_,HPDI32_CABLE_COMMAND_MODE_DEFAULT) |
| |
| #define | HPDI32_CABLE_COMMAND_MODE__2_FC(h) HPDI32_CABLE_COMMAND_MODE__FC(h,HPDI32_WHICH_COMMAND_2_) |
| |
| #define | HPDI32_CABLE_COMMAND_MODE__2_IN(h) HPDI32_CABLE_COMMAND_MODE__GPIO_IN(h,HPDI32_WHICH_COMMAND_2_) |
| |
| #define | HPDI32_CABLE_COMMAND_MODE__2_LOW(h) HPDI32_CABLE_COMMAND_MODE__GPIO_LOW(h,HPDI32_WHICH_COMMAND_2_) |
| |
| #define | HPDI32_CABLE_COMMAND_MODE__2_HI(h) HPDI32_CABLE_COMMAND_MODE__GPIO_HI(h,HPDI32_WHICH_COMMAND_2_) |
| |
| #define | HPDI32_CABLE_COMMAND_MODE__3_GET(h, g) HPDI32_CABLE_COMMAND_MODE__GET(h,HPDI32_WHICH_COMMAND_3_,g) |
| |
| #define | HPDI32_CABLE_COMMAND_MODE__3_SET(h, s) HPDI32_CABLE_COMMAND_MODE__SET(h,HPDI32_WHICH_COMMAND_3_,s) |
| |
| #define | HPDI32_CABLE_COMMAND_MODE__3_RESET(h) HPDI32_CABLE_COMMAND_MODE__SET(h,HPDI32_WHICH_COMMAND_3_,HPDI32_CABLE_COMMAND_MODE_DEFAULT) |
| |
| #define | HPDI32_CABLE_COMMAND_MODE__3_FC(h) HPDI32_CABLE_COMMAND_MODE__FC(h,HPDI32_WHICH_COMMAND_3_) |
| |
| #define | HPDI32_CABLE_COMMAND_MODE__3_IN(h) HPDI32_CABLE_COMMAND_MODE__GPIO_IN(h,HPDI32_WHICH_COMMAND_3_) |
| |
| #define | HPDI32_CABLE_COMMAND_MODE__3_LOW(h) HPDI32_CABLE_COMMAND_MODE__GPIO_LOW(h,HPDI32_WHICH_COMMAND_3_) |
| |
| #define | HPDI32_CABLE_COMMAND_MODE__3_HI(h) HPDI32_CABLE_COMMAND_MODE__GPIO_HI(h,HPDI32_WHICH_COMMAND_3_) |
| |
| #define | HPDI32_CABLE_COMMAND_MODE__4_GET(h, g) HPDI32_CABLE_COMMAND_MODE__GET(h,HPDI32_WHICH_COMMAND_4_,g) |
| |
| #define | HPDI32_CABLE_COMMAND_MODE__4_SET(h, s) HPDI32_CABLE_COMMAND_MODE__SET(h,HPDI32_WHICH_COMMAND_4_,s) |
| |
| #define | HPDI32_CABLE_COMMAND_MODE__4_RESET(h) HPDI32_CABLE_COMMAND_MODE__SET(h,HPDI32_WHICH_COMMAND_4_,HPDI32_CABLE_COMMAND_MODE_DEFAULT) |
| |
| #define | HPDI32_CABLE_COMMAND_MODE__4_FC(h) HPDI32_CABLE_COMMAND_MODE__FC(h,HPDI32_WHICH_COMMAND_4_) |
| |
| #define | HPDI32_CABLE_COMMAND_MODE__4_IN(h) HPDI32_CABLE_COMMAND_MODE__GPIO_IN(h,HPDI32_WHICH_COMMAND_4_) |
| |
| #define | HPDI32_CABLE_COMMAND_MODE__4_LOW(h) HPDI32_CABLE_COMMAND_MODE__GPIO_LOW(h,HPDI32_WHICH_COMMAND_4_) |
| |
| #define | HPDI32_CABLE_COMMAND_MODE__4_HI(h) HPDI32_CABLE_COMMAND_MODE__GPIO_HI(h,HPDI32_WHICH_COMMAND_4_) |
| |
| #define | HPDI32_CABLE_COMMAND_MODE__5_GET(h, g) HPDI32_CABLE_COMMAND_MODE__GET(h,HPDI32_WHICH_COMMAND_5_,g) |
| |
| #define | HPDI32_CABLE_COMMAND_MODE__5_SET(h, s) HPDI32_CABLE_COMMAND_MODE__SET(h,HPDI32_WHICH_COMMAND_5_,s) |
| |
| #define | HPDI32_CABLE_COMMAND_MODE__5_RESET(h) HPDI32_CABLE_COMMAND_MODE__SET(h,HPDI32_WHICH_COMMAND_5_,HPDI32_CABLE_COMMAND_MODE_DEFAULT) |
| |
| #define | HPDI32_CABLE_COMMAND_MODE__5_FC(h) HPDI32_CABLE_COMMAND_MODE__FC(h,HPDI32_WHICH_COMMAND_5_) |
| |
| #define | HPDI32_CABLE_COMMAND_MODE__5_IN(h) HPDI32_CABLE_COMMAND_MODE__GPIO_IN(h,HPDI32_WHICH_COMMAND_5_) |
| |
| #define | HPDI32_CABLE_COMMAND_MODE__5_LOW(h) HPDI32_CABLE_COMMAND_MODE__GPIO_LOW(h,HPDI32_WHICH_COMMAND_5_) |
| |
| #define | HPDI32_CABLE_COMMAND_MODE__5_HI(h) HPDI32_CABLE_COMMAND_MODE__GPIO_HI(h,HPDI32_WHICH_COMMAND_5_) |
| |
| #define | HPDI32_CABLE_COMMAND_MODE__6_GET(h, g) HPDI32_CABLE_COMMAND_MODE__GET(h,HPDI32_WHICH_COMMAND_6_,g) |
| |
| #define | HPDI32_CABLE_COMMAND_MODE__6_SET(h, s) HPDI32_CABLE_COMMAND_MODE__SET(h,HPDI32_WHICH_COMMAND_6_,s) |
| |
| #define | HPDI32_CABLE_COMMAND_MODE__6_RESET(h) HPDI32_CABLE_COMMAND_MODE__SET(h,HPDI32_WHICH_COMMAND_6_,HPDI32_CABLE_COMMAND_MODE_DEFAULT) |
| |
| #define | HPDI32_CABLE_COMMAND_MODE__6_FC(h) HPDI32_CABLE_COMMAND_MODE__FC(h,HPDI32_WHICH_COMMAND_6_) |
| |
| #define | HPDI32_CABLE_COMMAND_MODE__6_IN(h) HPDI32_CABLE_COMMAND_MODE__GPIO_IN(h,HPDI32_WHICH_COMMAND_6_) |
| |
| #define | HPDI32_CABLE_COMMAND_MODE__6_LOW(h) HPDI32_CABLE_COMMAND_MODE__GPIO_LOW(h,HPDI32_WHICH_COMMAND_6_) |
| |
| #define | HPDI32_CABLE_COMMAND_MODE__6_HI(h) HPDI32_CABLE_COMMAND_MODE__GPIO_HI(h,HPDI32_WHICH_COMMAND_6_) |
| |
| #define | HPDI32_CABLE_COMMAND_MODE__GPIO_0_GET(h, g) HPDI32_CABLE_COMMAND_MODE__GET(h,HPDI32_WHICH_GPIO_0_,g) |
| |
| #define | HPDI32_CABLE_COMMAND_MODE__GPIO_0_SET(h, s) HPDI32_CABLE_COMMAND_MODE__SET(h,HPDI32_WHICH_GPIO_0_,s) |
| |
| #define | HPDI32_CABLE_COMMAND_MODE__GPIO_0_RESET(h) HPDI32_CABLE_COMMAND_MODE__SET(h,HPDI32_WHICH_GPIO_0_,HPDI32_CABLE_COMMAND_MODE_DEFAULT) |
| |
| #define | HPDI32_CABLE_COMMAND_MODE__GPIO_0_FC(h) HPDI32_CABLE_COMMAND_MODE__FC(h,HPDI32_WHICH_GPIO_0_) |
| |
| #define | HPDI32_CABLE_COMMAND_MODE__GPIO_0_IN(h) HPDI32_CABLE_COMMAND_MODE__GPIO_IN(h,HPDI32_WHICH_GPIO_0_) |
| |
| #define | HPDI32_CABLE_COMMAND_MODE__GPIO_0_LOW(h) HPDI32_CABLE_COMMAND_MODE__GPIO_LOW(h,HPDI32_WHICH_GPIO_0_) |
| |
| #define | HPDI32_CABLE_COMMAND_MODE__GPIO_0_HI(h) HPDI32_CABLE_COMMAND_MODE__GPIO_HI(h,HPDI32_WHICH_GPIO_0_) |
| |
| #define | HPDI32_CABLE_COMMAND_MODE__GPIO_1_GET(h, g) HPDI32_CABLE_COMMAND_MODE__GET(h,HPDI32_WHICH_GPIO_1_,g) |
| |
| #define | HPDI32_CABLE_COMMAND_MODE__GPIO_1_SET(h, s) HPDI32_CABLE_COMMAND_MODE__SET(h,HPDI32_WHICH_GPIO_1_,s) |
| |
| #define | HPDI32_CABLE_COMMAND_MODE__GPIO_1_RESET(h) HPDI32_CABLE_COMMAND_MODE__SET(h,HPDI32_WHICH_GPIO_1_,HPDI32_CABLE_COMMAND_MODE_DEFAULT) |
| |
| #define | HPDI32_CABLE_COMMAND_MODE__GPIO_1_FC(h) HPDI32_CABLE_COMMAND_MODE__FC(h,HPDI32_WHICH_GPIO_1_) |
| |
| #define | HPDI32_CABLE_COMMAND_MODE__GPIO_1_IN(h) HPDI32_CABLE_COMMAND_MODE__GPIO_IN(h,HPDI32_WHICH_GPIO_1_) |
| |
| #define | HPDI32_CABLE_COMMAND_MODE__GPIO_1_LOW(h) HPDI32_CABLE_COMMAND_MODE__GPIO_LOW(h,HPDI32_WHICH_GPIO_1_) |
| |
| #define | HPDI32_CABLE_COMMAND_MODE__GPIO_1_HI(h) HPDI32_CABLE_COMMAND_MODE__GPIO_HI(h,HPDI32_WHICH_GPIO_1_) |
| |
| #define | HPDI32_CABLE_COMMAND_MODE__GPIO_2_GET(h, g) HPDI32_CABLE_COMMAND_MODE__GET(h,HPDI32_WHICH_GPIO_2_,g) |
| |
| #define | HPDI32_CABLE_COMMAND_MODE__GPIO_2_SET(h, s) HPDI32_CABLE_COMMAND_MODE__SET(h,HPDI32_WHICH_GPIO_2_,s) |
| |
| #define | HPDI32_CABLE_COMMAND_MODE__GPIO_2_RESET(h) HPDI32_CABLE_COMMAND_MODE__SET(h,HPDI32_WHICH_GPIO_2_,HPDI32_CABLE_COMMAND_MODE_DEFAULT) |
| |
| #define | HPDI32_CABLE_COMMAND_MODE__GPIO_2_FC(h) HPDI32_CABLE_COMMAND_MODE__FC(h,HPDI32_WHICH_GPIO_2_) |
| |
| #define | HPDI32_CABLE_COMMAND_MODE__GPIO_2_IN(h) HPDI32_CABLE_COMMAND_MODE__GPIO_IN(h,HPDI32_WHICH_GPIO_2_) |
| |
| #define | HPDI32_CABLE_COMMAND_MODE__GPIO_2_LOW(h) HPDI32_CABLE_COMMAND_MODE__GPIO_LOW(h,HPDI32_WHICH_GPIO_2_) |
| |
| #define | HPDI32_CABLE_COMMAND_MODE__GPIO_2_HI(h) HPDI32_CABLE_COMMAND_MODE__GPIO_HI(h,HPDI32_WHICH_GPIO_2_) |
| |
| #define | HPDI32_CABLE_COMMAND_MODE__GPIO_3_GET(h, g) HPDI32_CABLE_COMMAND_MODE__GET(h,HPDI32_WHICH_GPIO_3_,g) |
| |
| #define | HPDI32_CABLE_COMMAND_MODE__GPIO_3_SET(h, s) HPDI32_CABLE_COMMAND_MODE__SET(h,HPDI32_WHICH_GPIO_3_,s) |
| |
| #define | HPDI32_CABLE_COMMAND_MODE__GPIO_3_RESET(h) HPDI32_CABLE_COMMAND_MODE__SET(h,HPDI32_WHICH_GPIO_3_,HPDI32_CABLE_COMMAND_MODE_DEFAULT) |
| |
| #define | HPDI32_CABLE_COMMAND_MODE__GPIO_3_FC(h) HPDI32_CABLE_COMMAND_MODE__FC(h,HPDI32_WHICH_GPIO_3_) |
| |
| #define | HPDI32_CABLE_COMMAND_MODE__GPIO_3_IN(h) HPDI32_CABLE_COMMAND_MODE__GPIO_IN(h,HPDI32_WHICH_GPIO_3_) |
| |
| #define | HPDI32_CABLE_COMMAND_MODE__GPIO_3_LOW(h) HPDI32_CABLE_COMMAND_MODE__GPIO_LOW(h,HPDI32_WHICH_GPIO_3_) |
| |
| #define | HPDI32_CABLE_COMMAND_MODE__GPIO_3_HI(h) HPDI32_CABLE_COMMAND_MODE__GPIO_HI(h,HPDI32_WHICH_GPIO_3_) |
| |
| #define | HPDI32_CABLE_COMMAND_MODE__GPIO_4_GET(h, g) HPDI32_CABLE_COMMAND_MODE__GET(h,HPDI32_WHICH_GPIO_4_,g) |
| |
| #define | HPDI32_CABLE_COMMAND_MODE__GPIO_4_SET(h, s) HPDI32_CABLE_COMMAND_MODE__SET(h,HPDI32_WHICH_GPIO_4_,s) |
| |
| #define | HPDI32_CABLE_COMMAND_MODE__GPIO_4_RESET(h) HPDI32_CABLE_COMMAND_MODE__SET(h,HPDI32_WHICH_GPIO_4_,HPDI32_CABLE_COMMAND_MODE_DEFAULT) |
| |
| #define | HPDI32_CABLE_COMMAND_MODE__GPIO_4_FC(h) HPDI32_CABLE_COMMAND_MODE__FC(h,HPDI32_WHICH_GPIO_4_) |
| |
| #define | HPDI32_CABLE_COMMAND_MODE__GPIO_4_IN(h) HPDI32_CABLE_COMMAND_MODE__GPIO_IN(h,HPDI32_WHICH_GPIO_4_) |
| |
| #define | HPDI32_CABLE_COMMAND_MODE__GPIO_4_LOW(h) HPDI32_CABLE_COMMAND_MODE__GPIO_LOW(h,HPDI32_WHICH_GPIO_4_) |
| |
| #define | HPDI32_CABLE_COMMAND_MODE__GPIO_4_HI(h) HPDI32_CABLE_COMMAND_MODE__GPIO_HI(h,HPDI32_WHICH_GPIO_4_) |
| |
| #define | HPDI32_CABLE_COMMAND_MODE__GPIO_5_GET(h, g) HPDI32_CABLE_COMMAND_MODE__GET(h,HPDI32_WHICH_GPIO_5_,g) |
| |
| #define | HPDI32_CABLE_COMMAND_MODE__GPIO_5_SET(h, s) HPDI32_CABLE_COMMAND_MODE__SET(h,HPDI32_WHICH_GPIO_5_,s) |
| |
| #define | HPDI32_CABLE_COMMAND_MODE__GPIO_5_RESET(h) HPDI32_CABLE_COMMAND_MODE__SET(h,HPDI32_WHICH_GPIO_5_,HPDI32_CABLE_COMMAND_MODE_DEFAULT) |
| |
| #define | HPDI32_CABLE_COMMAND_MODE__GPIO_5_FC(h) HPDI32_CABLE_COMMAND_MODE__FC(h,HPDI32_WHICH_GPIO_5_) |
| |
| #define | HPDI32_CABLE_COMMAND_MODE__GPIO_5_IN(h) HPDI32_CABLE_COMMAND_MODE__GPIO_IN(h,HPDI32_WHICH_GPIO_5_) |
| |
| #define | HPDI32_CABLE_COMMAND_MODE__GPIO_5_LOW(h) HPDI32_CABLE_COMMAND_MODE__GPIO_LOW(h,HPDI32_WHICH_GPIO_5_) |
| |
| #define | HPDI32_CABLE_COMMAND_MODE__GPIO_5_HI(h) HPDI32_CABLE_COMMAND_MODE__GPIO_HI(h,HPDI32_WHICH_GPIO_5_) |
| |
| #define | HPDI32_CABLE_COMMAND_MODE__GPIO_6_GET(h, g) HPDI32_CABLE_COMMAND_MODE__GET(h,HPDI32_WHICH_GPIO_6_,g) |
| |
| #define | HPDI32_CABLE_COMMAND_MODE__GPIO_6_SET(h, s) HPDI32_CABLE_COMMAND_MODE__SET(h,HPDI32_WHICH_GPIO_6_,s) |
| |
| #define | HPDI32_CABLE_COMMAND_MODE__GPIO_6_RESET(h) HPDI32_CABLE_COMMAND_MODE__SET(h,HPDI32_WHICH_GPIO_6_,HPDI32_CABLE_COMMAND_MODE_DEFAULT) |
| |
| #define | HPDI32_CABLE_COMMAND_MODE__GPIO_6_FC(h) HPDI32_CABLE_COMMAND_MODE__FC(h,HPDI32_WHICH_GPIO_6_) |
| |
| #define | HPDI32_CABLE_COMMAND_MODE__GPIO_6_IN(h) HPDI32_CABLE_COMMAND_MODE__GPIO_IN(h,HPDI32_WHICH_GPIO_6_) |
| |
| #define | HPDI32_CABLE_COMMAND_MODE__GPIO_6_LOW(h) HPDI32_CABLE_COMMAND_MODE__GPIO_LOW(h,HPDI32_WHICH_GPIO_6_) |
| |
| #define | HPDI32_CABLE_COMMAND_MODE__GPIO_6_HI(h) HPDI32_CABLE_COMMAND_MODE__GPIO_HI(h,HPDI32_WHICH_GPIO_6_) |
| |
| #define | HPDI32_CABLE_COMMAND_MODE__FV_GET(h, g) HPDI32_CABLE_COMMAND_MODE__GET(h,HPDI32_WHICH_FV_,g) |
| |
| #define | HPDI32_CABLE_COMMAND_MODE__FV_SET(h, s) HPDI32_CABLE_COMMAND_MODE__SET(h,HPDI32_WHICH_FV_,s) |
| |
| #define | HPDI32_CABLE_COMMAND_MODE__FV_RESET(h) HPDI32_CABLE_COMMAND_MODE__SET(h,HPDI32_WHICH_FV_,HPDI32_CABLE_COMMAND_MODE_DEFAULT) |
| |
| #define | HPDI32_CABLE_COMMAND_MODE__FV_FC(h) HPDI32_CABLE_COMMAND_MODE__FC(h,HPDI32_WHICH_FV_) |
| |
| #define | HPDI32_CABLE_COMMAND_MODE__FV_IN(h) HPDI32_CABLE_COMMAND_MODE__GPIO_IN(h,HPDI32_WHICH_FV_) |
| |
| #define | HPDI32_CABLE_COMMAND_MODE__FV_LOW(h) HPDI32_CABLE_COMMAND_MODE__GPIO_LOW(h,HPDI32_WHICH_FV_) |
| |
| #define | HPDI32_CABLE_COMMAND_MODE__FV_HI(h) HPDI32_CABLE_COMMAND_MODE__GPIO_HI(h,HPDI32_WHICH_FV_) |
| |
| #define | HPDI32_CABLE_COMMAND_MODE__LV_GET(h, g) HPDI32_CABLE_COMMAND_MODE__GET(h,HPDI32_WHICH_LV_,g) |
| |
| #define | HPDI32_CABLE_COMMAND_MODE__LV_SET(h, s) HPDI32_CABLE_COMMAND_MODE__SET(h,HPDI32_WHICH_LV_,s) |
| |
| #define | HPDI32_CABLE_COMMAND_MODE__LV_RESET(h) HPDI32_CABLE_COMMAND_MODE__SET(h,HPDI32_WHICH_LV_,HPDI32_CABLE_COMMAND_MODE_DEFAULT) |
| |
| #define | HPDI32_CABLE_COMMAND_MODE__LV_FC(h) HPDI32_CABLE_COMMAND_MODE__FC(h,HPDI32_WHICH_LV_) |
| |
| #define | HPDI32_CABLE_COMMAND_MODE__LV_IN(h) HPDI32_CABLE_COMMAND_MODE__GPIO_IN(h,HPDI32_WHICH_LV_) |
| |
| #define | HPDI32_CABLE_COMMAND_MODE__LV_LOW(h) HPDI32_CABLE_COMMAND_MODE__GPIO_LOW(h,HPDI32_WHICH_LV_) |
| |
| #define | HPDI32_CABLE_COMMAND_MODE__LV_HI(h) HPDI32_CABLE_COMMAND_MODE__GPIO_HI(h,HPDI32_WHICH_LV_) |
| |
| #define | HPDI32_CABLE_COMMAND_MODE__SV_GET(h, g) HPDI32_CABLE_COMMAND_MODE__GET(h,HPDI32_WHICH_SV_,g) |
| |
| #define | HPDI32_CABLE_COMMAND_MODE__SV_SET(h, s) HPDI32_CABLE_COMMAND_MODE__SET(h,HPDI32_WHICH_SV_,s) |
| |
| #define | HPDI32_CABLE_COMMAND_MODE__SV_RESET(h) HPDI32_CABLE_COMMAND_MODE__SET(h,HPDI32_WHICH_SV_,HPDI32_CABLE_COMMAND_MODE_DEFAULT) |
| |
| #define | HPDI32_CABLE_COMMAND_MODE__SV_FC(h) HPDI32_CABLE_COMMAND_MODE__FC(h,HPDI32_WHICH_SV_) |
| |
| #define | HPDI32_CABLE_COMMAND_MODE__SV_IN(h) HPDI32_CABLE_COMMAND_MODE__GPIO_IN(h,HPDI32_WHICH_SV_) |
| |
| #define | HPDI32_CABLE_COMMAND_MODE__SV_LOW(h) HPDI32_CABLE_COMMAND_MODE__GPIO_LOW(h,HPDI32_WHICH_SV_) |
| |
| #define | HPDI32_CABLE_COMMAND_MODE__SV_HI(h) HPDI32_CABLE_COMMAND_MODE__GPIO_HI(h,HPDI32_WHICH_SV_) |
| |
| #define | HPDI32_CABLE_COMMAND_MODE__RR_GET(h, g) HPDI32_CABLE_COMMAND_MODE__GET(h,HPDI32_WHICH_RR_,g) |
| |
| #define | HPDI32_CABLE_COMMAND_MODE__RR_SET(h, s) HPDI32_CABLE_COMMAND_MODE__SET(h,HPDI32_WHICH_RR_,s) |
| |
| #define | HPDI32_CABLE_COMMAND_MODE__RR_RESET(h) HPDI32_CABLE_COMMAND_MODE__SET(h,HPDI32_WHICH_RR_,HPDI32_CABLE_COMMAND_MODE_DEFAULT) |
| |
| #define | HPDI32_CABLE_COMMAND_MODE__RR_FC(h) HPDI32_CABLE_COMMAND_MODE__FC(h,HPDI32_WHICH_RR_) |
| |
| #define | HPDI32_CABLE_COMMAND_MODE__RR_IN(h) HPDI32_CABLE_COMMAND_MODE__GPIO_IN(h,HPDI32_WHICH_RR_) |
| |
| #define | HPDI32_CABLE_COMMAND_MODE__RR_LOW(h) HPDI32_CABLE_COMMAND_MODE__GPIO_LOW(h,HPDI32_WHICH_RR_) |
| |
| #define | HPDI32_CABLE_COMMAND_MODE__RR_HI(h) HPDI32_CABLE_COMMAND_MODE__GPIO_HI(h,HPDI32_WHICH_RR_) |
| |
| #define | HPDI32_CABLE_COMMAND_MODE__TR_GET(h, g) HPDI32_CABLE_COMMAND_MODE__GET(h,HPDI32_WHICH_TR_,g) |
| |
| #define | HPDI32_CABLE_COMMAND_MODE__TR_SET(h, s) HPDI32_CABLE_COMMAND_MODE__SET(h,HPDI32_WHICH_TR_,s) |
| |
| #define | HPDI32_CABLE_COMMAND_MODE__TR_RESET(h) HPDI32_CABLE_COMMAND_MODE__SET(h,HPDI32_WHICH_TR_,HPDI32_CABLE_COMMAND_MODE_DEFAULT) |
| |
| #define | HPDI32_CABLE_COMMAND_MODE__TR_FC(h) HPDI32_CABLE_COMMAND_MODE__FC(h,HPDI32_WHICH_TR_) |
| |
| #define | HPDI32_CABLE_COMMAND_MODE__TR_IN(h) HPDI32_CABLE_COMMAND_MODE__GPIO_IN(h,HPDI32_WHICH_TR_) |
| |
| #define | HPDI32_CABLE_COMMAND_MODE__TR_LOW(h) HPDI32_CABLE_COMMAND_MODE__GPIO_LOW(h,HPDI32_WHICH_TR_) |
| |
| #define | HPDI32_CABLE_COMMAND_MODE__TR_HI(h) HPDI32_CABLE_COMMAND_MODE__GPIO_HI(h,HPDI32_WHICH_TR_) |
| |
| #define | HPDI32_CABLE_COMMAND_MODE__TE_GET(h, g) HPDI32_CABLE_COMMAND_MODE__GET(h,HPDI32_WHICH_TE_,g) |
| |
| #define | HPDI32_CABLE_COMMAND_MODE__TE_SET(h, s) HPDI32_CABLE_COMMAND_MODE__SET(h,HPDI32_WHICH_TE_,s) |
| |
| #define | HPDI32_CABLE_COMMAND_MODE__TE_RESET(h) HPDI32_CABLE_COMMAND_MODE__SET(h,HPDI32_WHICH_TE_,HPDI32_CABLE_COMMAND_MODE_DEFAULT) |
| |
| #define | HPDI32_CABLE_COMMAND_MODE__TE_FC(h) HPDI32_CABLE_COMMAND_MODE__FC(h,HPDI32_WHICH_TE_) |
| |
| #define | HPDI32_CABLE_COMMAND_MODE__TE_IN(h) HPDI32_CABLE_COMMAND_MODE__GPIO_IN(h,HPDI32_WHICH_TE_) |
| |
| #define | HPDI32_CABLE_COMMAND_MODE__TE_LOW(h) HPDI32_CABLE_COMMAND_MODE__GPIO_LOW(h,HPDI32_WHICH_TE_) |
| |
| #define | HPDI32_CABLE_COMMAND_MODE__TE_HI(h) HPDI32_CABLE_COMMAND_MODE__GPIO_HI(h,HPDI32_WHICH_TE_) |
| |
| #define | HPDI32_CABLE_COMMAND_MODE__RE_GET(h, g) HPDI32_CABLE_COMMAND_MODE__GET(h,HPDI32_WHICH_RE_,g) |
| |
| #define | HPDI32_CABLE_COMMAND_MODE__RE_SET(h, s) HPDI32_CABLE_COMMAND_MODE__SET(h,HPDI32_WHICH_RE_,s) |
| |
| #define | HPDI32_CABLE_COMMAND_MODE__RE_RESET(h) HPDI32_CABLE_COMMAND_MODE__SET(h,HPDI32_WHICH_RE_,HPDI32_CABLE_COMMAND_MODE_DEFAULT) |
| |
| #define | HPDI32_CABLE_COMMAND_MODE__RE_FC(h) HPDI32_CABLE_COMMAND_MODE__FC(h,HPDI32_WHICH_RE_) |
| |
| #define | HPDI32_CABLE_COMMAND_MODE__RE_IN(h) HPDI32_CABLE_COMMAND_MODE__GPIO_IN(h,HPDI32_WHICH_RE_) |
| |
| #define | HPDI32_CABLE_COMMAND_MODE__RE_LOW(h) HPDI32_CABLE_COMMAND_MODE__GPIO_LOW(h,HPDI32_WHICH_RE_) |
| |
| #define | HPDI32_CABLE_COMMAND_MODE__RE_HI(h) HPDI32_CABLE_COMMAND_MODE__GPIO_HI(h,HPDI32_WHICH_RE_) |
| |
| #define | HPDI32_CABLE_COMMAND_STATE_INACTIVE 0 |
| |
| #define | HPDI32_CABLE_COMMAND_STATE_ACTIVE 1 |
| |
| #define | HPDI32_CABLE_COMMAND_STATE__GET(h, w, g) HPDI32_CONFIG_GET((h),HPDI32_CABLE_COMMAND_STATE,(w),(g)) |
| |
| #define | HPDI32_CABLE_COMMAND_STATE__0_GET(h, g) HPDI32_CABLE_COMMAND_STATE__GET(h,HPDI32_WHICH_COMMAND_0_,g) |
| |
| #define | HPDI32_CABLE_COMMAND_STATE__1_GET(h, g) HPDI32_CABLE_COMMAND_STATE__GET(h,HPDI32_WHICH_COMMAND_1_,g) |
| |
| #define | HPDI32_CABLE_COMMAND_STATE__2_GET(h, g) HPDI32_CABLE_COMMAND_STATE__GET(h,HPDI32_WHICH_COMMAND_2_,g) |
| |
| #define | HPDI32_CABLE_COMMAND_STATE__3_GET(h, g) HPDI32_CABLE_COMMAND_STATE__GET(h,HPDI32_WHICH_COMMAND_3_,g) |
| |
| #define | HPDI32_CABLE_COMMAND_STATE__4_GET(h, g) HPDI32_CABLE_COMMAND_STATE__GET(h,HPDI32_WHICH_COMMAND_4_,g) |
| |
| #define | HPDI32_CABLE_COMMAND_STATE__5_GET(h, g) HPDI32_CABLE_COMMAND_STATE__GET(h,HPDI32_WHICH_COMMAND_5_,g) |
| |
| #define | HPDI32_CABLE_COMMAND_STATE__6_GET(h, g) HPDI32_CABLE_COMMAND_STATE__GET(h,HPDI32_WHICH_COMMAND_6_,g) |
| |
| #define | HPDI32_CABLE_COMMAND_STATE__GPIO_0_GET(h, g) HPDI32_CABLE_COMMAND_STATE__GET(h,HPDI32_WHICH_GPIO_0_,g) |
| |
| #define | HPDI32_CABLE_COMMAND_STATE__GPIO_1_GET(h, g) HPDI32_CABLE_COMMAND_STATE__GET(h,HPDI32_WHICH_GPIO_1_,g) |
| |
| #define | HPDI32_CABLE_COMMAND_STATE__GPIO_2_GET(h, g) HPDI32_CABLE_COMMAND_STATE__GET(h,HPDI32_WHICH_GPIO_2_,g) |
| |
| #define | HPDI32_CABLE_COMMAND_STATE__GPIO_3_GET(h, g) HPDI32_CABLE_COMMAND_STATE__GET(h,HPDI32_WHICH_GPIO_3_,g) |
| |
| #define | HPDI32_CABLE_COMMAND_STATE__GPIO_4_GET(h, g) HPDI32_CABLE_COMMAND_STATE__GET(h,HPDI32_WHICH_GPIO_4_,g) |
| |
| #define | HPDI32_CABLE_COMMAND_STATE__GPIO_5_GET(h, g) HPDI32_CABLE_COMMAND_STATE__GET(h,HPDI32_WHICH_GPIO_5_,g) |
| |
| #define | HPDI32_CABLE_COMMAND_STATE__GPIO_6_GET(h, g) HPDI32_CABLE_COMMAND_STATE__GET(h,HPDI32_WHICH_GPIO_6_,g) |
| |
| #define | HPDI32_CABLE_COMMAND_STATE__FV_GET(h, g) HPDI32_CABLE_COMMAND_STATE__GET(h,HPDI32_WHICH_FV_,g) |
| |
| #define | HPDI32_CABLE_COMMAND_STATE__LV_GET(h, g) HPDI32_CABLE_COMMAND_STATE__GET(h,HPDI32_WHICH_LV_,g) |
| |
| #define | HPDI32_CABLE_COMMAND_STATE__SV_GET(h, g) HPDI32_CABLE_COMMAND_STATE__GET(h,HPDI32_WHICH_SV_,g) |
| |
| #define | HPDI32_CABLE_COMMAND_STATE__RR_GET(h, g) HPDI32_CABLE_COMMAND_STATE__GET(h,HPDI32_WHICH_RR_,g) |
| |
| #define | HPDI32_CABLE_COMMAND_STATE__TR_GET(h, g) HPDI32_CABLE_COMMAND_STATE__GET(h,HPDI32_WHICH_TR_,g) |
| |
| #define | HPDI32_CABLE_COMMAND_STATE__TE_GET(h, g) HPDI32_CABLE_COMMAND_STATE__GET(h,HPDI32_WHICH_TE_,g) |
| |
| #define | HPDI32_CABLE_COMMAND_STATE__RE_GET(h, g) HPDI32_CABLE_COMMAND_STATE__GET(h,HPDI32_WHICH_RE_,g) |
| |
| #define | HPDI32_FIFO_ENCODE(i) HPDI32_CONFIG_ENCODE(HPDI32_CONFIG_GROUP_FIFO, (i)) |
| |
| #define | HPDI32_FIFO_ALMOST_LEVEL HPDI32_FIFO_ENCODE(0) /* Tx, Rx, AE, AF */ |
| |
| #define | HPDI32_FIFO_RESET HPDI32_FIFO_ENCODE(1) /* Tx, Rx */ |
| |
| #define | HPDI32_FIFO_SIZE HPDI32_FIFO_ENCODE(2) /* Tx, Rx, GET only */ |
| |
| #define | HPDI32_FIFO_STATUS HPDI32_FIFO_ENCODE(3) /* Tx, Rx, GET only */ |
| |
| #define | HPDI32_FIFO_TRANSFER_SIZE HPDI32_FIFO_ENCODE(4) /* Tx, Rx, GET only */ |
| |
| #define | HPDI32_FIFO_ALMOST_EMPTY_DEFAULT 0x0F |
| |
| #define | HPDI32_FIFO_ALMOST_FULL_DEFAULT 0x10 |
| |
| #define | HPDI32_FIFO_ALMOST_LEVEL_MAX 0xFFFF |
| |
| #define | HPDI32_FIFO_ALMOST_LEVEL__GET(h, w, g) HPDI32_CONFIG_GET((h),HPDI32_FIFO_ALMOST_LEVEL,(w),(g)) |
| |
| #define | HPDI32_FIFO_ALMOST_LEVEL__SET(h, w, s) HPDI32_CONFIG_SET((h),HPDI32_FIFO_ALMOST_LEVEL,(w),(s)) |
| |
| #define | HPDI32_FIFO_ALMOST_LEVEL__RX_AE_GET(h, g) HPDI32_FIFO_ALMOST_LEVEL__GET((h),HPDI32_WHICH_RX | HPDI32_WHICH_AE,(g)) |
| |
| #define | HPDI32_FIFO_ALMOST_LEVEL__RX_AE_SET(h, s) HPDI32_FIFO_ALMOST_LEVEL__SET((h),HPDI32_WHICH_RX | HPDI32_WHICH_AE,(s)) |
| |
| #define | HPDI32_FIFO_ALMOST_LEVEL__RX_AF_GET(h, g) HPDI32_FIFO_ALMOST_LEVEL__GET((h),HPDI32_WHICH_RX | HPDI32_WHICH_AF,(g)) |
| |
| #define | HPDI32_FIFO_ALMOST_LEVEL__RX_AF_SET(h, s) HPDI32_FIFO_ALMOST_LEVEL__SET((h),HPDI32_WHICH_RX | HPDI32_WHICH_AF,(s)) |
| |
| #define | HPDI32_FIFO_ALMOST_LEVEL__TX_AE_GET(h, g) HPDI32_FIFO_ALMOST_LEVEL__GET((h),HPDI32_WHICH_TX | HPDI32_WHICH_AE,(g)) |
| |
| #define | HPDI32_FIFO_ALMOST_LEVEL__TX_AE_SET(h, s) HPDI32_FIFO_ALMOST_LEVEL__SET((h),HPDI32_WHICH_TX | HPDI32_WHICH_AE,(s)) |
| |
| #define | HPDI32_FIFO_ALMOST_LEVEL__TX_AF_GET(h, g) HPDI32_FIFO_ALMOST_LEVEL__GET((h),HPDI32_WHICH_TX | HPDI32_WHICH_AF,(g)) |
| |
| #define | HPDI32_FIFO_ALMOST_LEVEL__TX_AF_SET(h, s) HPDI32_FIFO_ALMOST_LEVEL__SET((h),HPDI32_WHICH_TX | HPDI32_WHICH_AF,(s)) |
| |
| #define | HPDI32_FIFO_RESET_NO 0 |
| |
| #define | HPDI32_FIFO_RESET_YES 1 |
| |
| #define | HPDI32_FIFO_RESET_DEFAULT HPDI32_FIFO_RESET_NO |
| |
| #define | HPDI32_FIFO_RESET__SET(h, w, s) HPDI32_CONFIG_SET((h),HPDI32_FIFO_RESET,(w),(s)) |
| |
| #define | HPDI32_FIFO_RESET__RESET(h, w) HPDI32_CONFIG_SET((h),HPDI32_FIFO_RESET,(w),HPDI32_FIFO_RESET_DEFAULT) |
| |
| #define | HPDI32_FIFO_RESET__RX_SET(h, s) HPDI32_FIFO_RESET__SET((h),HPDI32_WHICH_RX,(s)) |
| |
| #define | HPDI32_FIFO_RESET__RX_RESET(h) HPDI32_FIFO_RESET__SET((h),HPDI32_WHICH_RX,HPDI32_FIFO_RESET_DEFAULT) |
| |
| #define | HPDI32_FIFO_RESET__RX_YES(h) HPDI32_FIFO_RESET__RX_SET((h),HPDI32_FIFO_RESET_YES) |
| |
| #define | HPDI32_FIFO_RESET__TX_SET(h, s) HPDI32_FIFO_RESET__SET((h),HPDI32_WHICH_TX,(s)) |
| |
| #define | HPDI32_FIFO_RESET__TX_RESET(h) HPDI32_FIFO_RESET__SET((h),HPDI32_WHICH_TX,HPDI32_FIFO_RESET_DEFAULT) |
| |
| #define | HPDI32_FIFO_RESET__TX_YES(h) HPDI32_FIFO_RESET__TX_SET((h),HPDI32_FIFO_RESET_YES) |
| |
| #define | HPDI32_FIFO_RESET__YES(h, w) HPDI32_CONFIG_SET((h),HPDI32_FIFO_RESET,(w),HPDI32_FIFO_RESET_YES) |
| |
| #define | HPDI32_FIFO_SIZE__GET(h, w, g) HPDI32_CONFIG_GET((h),HPDI32_FIFO_SIZE,(w),(g)) |
| |
| #define | HPDI32_FIFO_SIZE__RX_GET(h, g) HPDI32_FIFO_SIZE__GET((h),HPDI32_WHICH_RX,(g)) |
| |
| #define | HPDI32_FIFO_SIZE__TX_GET(h, g) HPDI32_FIFO_SIZE__GET((h),HPDI32_WHICH_TX,(g)) |
| |
| #define | HPDI32_FIFO_STATUS_EMPTY 0 |
| |
| #define | HPDI32_FIFO_STATUS_ALMOST_EMPTY 1 |
| |
| #define | HPDI32_FIFO_STATUS_MEDIAN 2 |
| |
| #define | HPDI32_FIFO_STATUS_ALMOST_FULL 3 |
| |
| #define | HPDI32_FIFO_STATUS_FULL 4 |
| |
| #define | HPDI32_FIFO_STATUS__GET(h, w, g) HPDI32_CONFIG_GET((h),HPDI32_FIFO_STATUS,(w),(g)) |
| |
| #define | HPDI32_FIFO_STATUS__RX_GET(h, g) HPDI32_FIFO_STATUS__GET((h),HPDI32_WHICH_RX,(g)) |
| |
| #define | HPDI32_FIFO_STATUS__TX_GET(h, g) HPDI32_FIFO_STATUS__GET((h),HPDI32_WHICH_TX,(g)) |
| |
| #define | HPDI32_FIFO_TRANSFER_SIZE__GET(h, w, g) HPDI32_CONFIG_GET((h),HPDI32_FIFO_TRANSFER_SIZE,(w),(g)) |
| |
| #define | HPDI32_FIFO_TRANSFER_SIZE__RX_GET(h, g) HPDI32_FIFO_TRANSFER_SIZE__GET((h),HPDI32_WHICH_RX,(g)) |
| |
| #define | HPDI32_FIFO_TRANSFER_SIZE__TX_GET(h, g) HPDI32_FIFO_TRANSFER_SIZE__GET((h),HPDI32_WHICH_TX,(g)) |
| |
| #define | HPDI32_IO_ENCODE(i) HPDI32_CONFIG_ENCODE(HPDI32_CONFIG_GROUP_IO, (i)) |
| |
| #define | HPDI32_IO_ABORT HPDI32_IO_ENCODE( 0) /* Tx, Rx */ |
| |
| #define | HPDI32_IO_ABORTED HPDI32_IO_ENCODE( 1) /* Tx, Rx, GET only */ |
| |
| #define | HPDI32_IO_BUFFER_POINTER HPDI32_IO_ENCODE( 2) /* Tx, Rx, GET only */ |
| |
| #define | HPDI32_IO_BUFFER_SIZE HPDI32_IO_ENCODE( 3) /* Tx, Rx */ |
| |
| #define | HPDI32_IO_CALLBACK_ARG HPDI32_IO_ENCODE( 4) /* Tx, Rx */ |
| |
| #define | HPDI32_IO_CALLBACK_FUNC HPDI32_IO_ENCODE( 5) /* Tx, Rx */ |
| |
| #define | HPDI32_IO_DATA_SIZE HPDI32_IO_ENCODE( 6) /* Tx, Rx */ |
| |
| #define | HPDI32_IO_DMA_CHANNEL_SEL HPDI32_IO_ENCODE( 7) /* Tx, Rx */ |
| |
| #define | HPDI32_IO_DMA_CONTROL_MODE HPDI32_IO_ENCODE( 8) /* Tx, Rx */ |
| |
| #define | HPDI32_IO_DMA_PRIORITY HPDI32_IO_ENCODE( 9) /* Tx, Rx */ |
| |
| #define | HPDI32_IO_MODE HPDI32_IO_ENCODE(10) /* Tx, Rx */ |
| |
| #define | HPDI32_IO_OVERLAP_ENABLE HPDI32_IO_ENCODE(11) /* Tx, Rx */ |
| |
| #define | HPDI32_IO_PIO_THRESHOLD HPDI32_IO_ENCODE(12) /* Tx, Rx */ |
| |
| #define | HPDI32_IO_STATUS HPDI32_IO_ENCODE(13) /* Tx, Rx, GET only */ |
| |
| #define | HPDI32_IO_TIMEOUT HPDI32_IO_ENCODE(14) /* Tx, Rx */ |
| |
| #define | HPDI32_IO_SINGLE_CYCLE HPDI32_IO_ENCODE(15) /* Tx, Rx */ |
| |
| #define | HPDI32_IO_ABORT_NO 0 |
| |
| #define | HPDI32_IO_ABORT_YES 1 |
| |
| #define | HPDI32_IO_ABORT_DEFAULT HPDI32_IO_ABORT_NO |
| |
| #define | HPDI32_IO_ABORT__SET(h, w, s) HPDI32_CONFIG_SET((h),HPDI32_IO_ABORT,(w),(s)) |
| |
| #define | HPDI32_IO_ABORT__RX_SET(h, s) HPDI32_IO_ABORT__SET((h),HPDI32_WHICH_RX,(s)) |
| |
| #define | HPDI32_IO_ABORT__RX_YES(h) HPDI32_IO_ABORT__RX_SET((h),HPDI32_IO_ABORT_YES) |
| |
| #define | HPDI32_IO_ABORT__TX_SET(h, s) HPDI32_IO_ABORT__SET((h),HPDI32_WHICH_TX,(s)) |
| |
| #define | HPDI32_IO_ABORT__TX_YES(h) HPDI32_IO_ABORT__TX_SET((h),HPDI32_IO_ABORT_YES) |
| |
| #define | HPDI32_IO_ABORTED_NO 0 |
| |
| #define | HPDI32_IO_ABORTED_YES 1 |
| |
| #define | HPDI32_IO_ABORTED__GET(h, w, g) HPDI32_CONFIG_GET((h),HPDI32_IO_ABORTED,(w),(g)) |
| |
| #define | HPDI32_IO_ABORTED__RX_GET(h, g) HPDI32_IO_ABORTED__GET((h),HPDI32_WHICH_RX,(g)) |
| |
| #define | HPDI32_IO_ABORTED__TX_GET(h, g) HPDI32_IO_ABORTED__GET((h),HPDI32_WHICH_TX,(g)) |
| |
| #define | HPDI32_IO_BUFFER_POINTER__GET(h, w, g) HPDI32_CONFIG_GET((h),HPDI32_IO_BUFFER_POINTER,(w),(g)) |
| |
| #define | HPDI32_IO_BUFFER_POINTER__RX_GET(h, g) HPDI32_IO_BUFFER_POINTER__GET((h),HPDI32_WHICH_RX,(g)) |
| |
| #define | HPDI32_IO_BUFFER_POINTER__TX_GET(h, g) HPDI32_IO_BUFFER_POINTER__GET((h),HPDI32_WHICH_TX,(g)) |
| |
| #define | HPDI32_IO_BUFFER_SIZE_DEFAULT 0 |
| |
| #define | HPDI32_IO_BUFFER_SIZE__GET(h, w, g) HPDI32_CONFIG_GET((h),HPDI32_IO_BUFFER_SIZE,(w),(g)) |
| |
| #define | HPDI32_IO_BUFFER_SIZE__SET(h, w, s, g) HPDI32_CONFIG_SET_GET((h),HPDI32_IO_BUFFER_SIZE,(w),(s),(g)) |
| |
| #define | HPDI32_IO_BUFFER_SIZE__RX_GET(h, g) HPDI32_IO_BUFFER_SIZE__GET((h),HPDI32_WHICH_RX,(g)) |
| |
| #define | HPDI32_IO_BUFFER_SIZE__RX_SET(h, s, g) HPDI32_IO_BUFFER_SIZE__SET((h),HPDI32_WHICH_RX,(s),(g)) |
| |
| #define | HPDI32_IO_BUFFER_SIZE__RX_FREE(h) HPDI32_IO_BUFFER_SIZE__RX_SET(h,0,0) |
| |
| #define | HPDI32_IO_BUFFER_SIZE__TX_GET(h, g) HPDI32_IO_BUFFER_SIZE__GET((h),HPDI32_WHICH_TX,(g)) |
| |
| #define | HPDI32_IO_BUFFER_SIZE__TX_SET(h, s, g) HPDI32_IO_BUFFER_SIZE__SET((h),HPDI32_WHICH_TX,(s),(g)) |
| |
| #define | HPDI32_IO_BUFFER_SIZE__TX_FREE(h) HPDI32_IO_BUFFER_SIZE__TX_SET(h,0,0) |
| |
| #define | HPDI32_IO_CALLBACK_ARG_DEFAULT 0 |
| |
| #define | HPDI32_IO_CALLBACK_ARG__GET(h, w, g) HPDI32_CONFIG_GET((h),HPDI32_IO_CALLBACK_ARG,(w),(g)) |
| |
| #define | HPDI32_IO_CALLBACK_ARG__SET(h, w, s) HPDI32_CONFIG_SET((h),HPDI32_IO_CALLBACK_ARG,(w),(s)) |
| |
| #define | HPDI32_IO_CALLBACK_ARG__RESET(h, w) HPDI32_CONFIG_SET((h),HPDI32_IO_CALLBACK_ARG,(w),HPDI32_IO_CALLBACK_ARG_DEFAULT) |
| |
| #define | HPDI32_IO_CALLBACK_ARG__RX_GET(h, g) HPDI32_IO_CALLBACK_ARG__GET((h),HPDI32_WHICH_RX,(g)) |
| |
| #define | HPDI32_IO_CALLBACK_ARG__RX_SET(h, s) HPDI32_IO_CALLBACK_ARG__SET((h),HPDI32_WHICH_RX,(s)) |
| |
| #define | HPDI32_IO_CALLBACK_ARG__RX_RESET(h) HPDI32_IO_CALLBACK_ARG__SET((h),HPDI32_WHICH_RX,HPDI32_IO_CALLBACK_ARG_DEFAULT) |
| |
| #define | HPDI32_IO_CALLBACK_ARG__TX_GET(h, g) HPDI32_IO_CALLBACK_ARG__GET((h),HPDI32_WHICH_TX,(g)) |
| |
| #define | HPDI32_IO_CALLBACK_ARG__TX_SET(h, s) HPDI32_IO_CALLBACK_ARG__SET((h),HPDI32_WHICH_TX,(s)) |
| |
| #define | HPDI32_IO_CALLBACK_ARG__TX_RESET(h) HPDI32_IO_CALLBACK_ARG__SET((h),HPDI32_WHICH_TX,HPDI32_IO_CALLBACK_ARG_DEFAULT) |
| |
| #define | HPDI32_IO_CALLBACK_FUNC_DEFAULT 0 |
| |
| #define | HPDI32_IO_CALLBACK_FUNC__GET(h, w, g) HPDI32_CONFIG_GET((h),HPDI32_IO_CALLBACK_FUNC,(w),(g)) |
| |
| #define | HPDI32_IO_CALLBACK_FUNC__SET(h, w, s) HPDI32_CONFIG_SET((h),HPDI32_IO_CALLBACK_FUNC,(w),(s)) |
| |
| #define | HPDI32_IO_CALLBACK_FUNC__RESET(h, w) HPDI32_CONFIG_SET((h),HPDI32_IO_CALLBACK_FUNC,(w),HPDI32_IO_CALLBACK_FUNC_DEFAULT) |
| |
| #define | HPDI32_IO_CALLBACK_FUNC__RX_GET(h, g) HPDI32_IO_CALLBACK_FUNC__GET((h),HPDI32_WHICH_RX,(g)) |
| |
| #define | HPDI32_IO_CALLBACK_FUNC__RX_SET(h, s) HPDI32_IO_CALLBACK_FUNC__SET((h),HPDI32_WHICH_RX,(s)) |
| |
| #define | HPDI32_IO_CALLBACK_FUNC__RX_RESET(h) HPDI32_IO_CALLBACK_FUNC__SET((h),HPDI32_WHICH_RX,HPDI32_IO_CALLBACK_FUNC_DEFAULT) |
| |
| #define | HPDI32_IO_CALLBACK_FUNC__TX_GET(h, g) HPDI32_IO_CALLBACK_FUNC__GET((h),HPDI32_WHICH_TX,(g)) |
| |
| #define | HPDI32_IO_CALLBACK_FUNC__TX_SET(h, s) HPDI32_IO_CALLBACK_FUNC__SET((h),HPDI32_WHICH_TX,(s)) |
| |
| #define | HPDI32_IO_CALLBACK_FUNC__TX_RESET(h) HPDI32_IO_CALLBACK_FUNC__SET((h),HPDI32_WHICH_TX,HPDI32_IO_CALLBACK_FUNC_DEFAULT) |
| |
| #define | HPDI32_IO_DATA_SIZE_8_BITS 8 |
| |
| #define | HPDI32_IO_DATA_SIZE_16_BITS 16 |
| |
| #define | HPDI32_IO_DATA_SIZE_32_BITS 32 |
| |
| #define | HPDI32_IO_DATA_SIZE_DEFAULT HPDI32_IO_DATA_SIZE_32_BITS |
| |
| #define | HPDI32_IO_DATA_SIZE__GET(h, w, g) HPDI32_CONFIG_GET((h),HPDI32_IO_DATA_SIZE,(w),(g)) |
| |
| #define | HPDI32_IO_DATA_SIZE__SET(h, w, s) HPDI32_CONFIG_SET((h),HPDI32_IO_DATA_SIZE,(w),(s)) |
| |
| #define | HPDI32_IO_DATA_SIZE__RESET(h, w) HPDI32_CONFIG_SET((h),HPDI32_IO_DATA_SIZE,(w),HPDI32_IO_DATA_SIZE_DEFAULT) |
| |
| #define | HPDI32_IO_DATA_SIZE__RX_GET(h, g) HPDI32_IO_DATA_SIZE__GET((h),HPDI32_WHICH_RX,(g)) |
| |
| #define | HPDI32_IO_DATA_SIZE__RX_SET(h, s) HPDI32_IO_DATA_SIZE__SET((h),HPDI32_WHICH_RX,(s)) |
| |
| #define | HPDI32_IO_DATA_SIZE__RX_RESET(h) HPDI32_IO_DATA_SIZE__SET((h),HPDI32_WHICH_RX,HPDI32_IO_DATA_SIZE_DEFAULT) |
| |
| #define | HPDI32_IO_DATA_SIZE__RX_8(h) HPDI32_IO_DATA_SIZE__RX_SET((h),HPDI32_IO_DATA_SIZE_8_BITS) |
| |
| #define | HPDI32_IO_DATA_SIZE__RX_16(h) HPDI32_IO_DATA_SIZE__RX_SET((h),HPDI32_IO_DATA_SIZE_16_BITS) |
| |
| #define | HPDI32_IO_DATA_SIZE__RX_32(h) HPDI32_IO_DATA_SIZE__RX_SET((h),HPDI32_IO_DATA_SIZE_32_BITS) |
| |
| #define | HPDI32_IO_DATA_SIZE__TX_GET(h, g) HPDI32_IO_DATA_SIZE__GET((h),HPDI32_WHICH_TX,(g)) |
| |
| #define | HPDI32_IO_DATA_SIZE__TX_SET(h, s) HPDI32_IO_DATA_SIZE__SET((h),HPDI32_WHICH_TX,(s)) |
| |
| #define | HPDI32_IO_DATA_SIZE__TX_RESET(h) HPDI32_IO_DATA_SIZE__SET((h),HPDI32_WHICH_TX,HPDI32_IO_DATA_SIZE_DEFAULT) |
| |
| #define | HPDI32_IO_DATA_SIZE__TX_8(h) HPDI32_IO_DATA_SIZE__TX_SET((h),HPDI32_IO_DATA_SIZE_8_BITS) |
| |
| #define | HPDI32_IO_DATA_SIZE__TX_16(h) HPDI32_IO_DATA_SIZE__TX_SET((h),HPDI32_IO_DATA_SIZE_16_BITS) |
| |
| #define | HPDI32_IO_DATA_SIZE__TX_32(h) HPDI32_IO_DATA_SIZE__TX_SET((h),HPDI32_IO_DATA_SIZE_32_BITS) |
| |
| #define | HPDI32_IO_DMA_CHANNEL_SEL_STATIC 0 |
| |
| #define | HPDI32_IO_DMA_CHANNEL_SEL_DYNAMIC 1 |
| |
| #define | HPDI32_IO_DMA_CHANNEL_SEL_RX_DEFAULT HPDI32_IO_DMA_CHANNEL_SEL_DYNAMIC |
| |
| #define | HPDI32_IO_DMA_CHANNEL_SEL_TX_DEFAULT HPDI32_IO_DMA_CHANNEL_SEL_STATIC |
| |
| #define | HPDI32_IO_DMA_CHANNEL_SEL__GET(h, w, g) HPDI32_CONFIG_GET((h),HPDI32_IO_DMA_CHANNEL_SEL,(w),(g)) |
| |
| #define | HPDI32_IO_DMA_CHANNEL_SEL__SET(h, w, s) HPDI32_CONFIG_SET((h),HPDI32_IO_DMA_CHANNEL_SEL,(w),(s)) |
| |
| #define | HPDI32_IO_DMA_CHANNEL_SEL__RX_GET(h, g) HPDI32_IO_DMA_CHANNEL_SEL__GET((h),HPDI32_WHICH_RX,(g)) |
| |
| #define | HPDI32_IO_DMA_CHANNEL_SEL__RX_SET(h, s) HPDI32_IO_DMA_CHANNEL_SEL__SET((h),HPDI32_WHICH_RX,(s)) |
| |
| #define | HPDI32_IO_DMA_CHANNEL_SEL__RX_RESET(h) HPDI32_IO_DMA_CHANNEL_SEL__SET((h),HPDI32_WHICH_RX,HPDI32_IO_DMA_CHANNEL_SEL_RX_DEFAULT) |
| |
| #define | HPDI32_IO_DMA_CHANNEL_SEL__RX_STATIC(h) HPDI32_IO_DMA_CHANNEL_SEL__RX_SET((h),HPDI32_IO_DMA_CHANNEL_SEL_STATIC) |
| |
| #define | HPDI32_IO_DMA_CHANNEL_SEL__RX_DYNAMIC(h) HPDI32_IO_DMA_CHANNEL_SEL__RX_SET((h),HPDI32_IO_DMA_CHANNEL_SEL_DYNAMIC) |
| |
| #define | HPDI32_IO_DMA_CHANNEL_SEL__TX_GET(h, g) HPDI32_IO_DMA_CHANNEL_SEL__GET((h),HPDI32_WHICH_TX,(g)) |
| |
| #define | HPDI32_IO_DMA_CHANNEL_SEL__TX_SET(h, s) HPDI32_IO_DMA_CHANNEL_SEL__SET((h),HPDI32_WHICH_TX,(s)) |
| |
| #define | HPDI32_IO_DMA_CHANNEL_SEL__TX_RESET(h) HPDI32_IO_DMA_CHANNEL_SEL__SET((h),HPDI32_WHICH_TX,HPDI32_IO_DMA_CHANNEL_SEL_TX_DEFAULT) |
| |
| #define | HPDI32_IO_DMA_CHANNEL_SEL__TX_STATIC(h) HPDI32_IO_DMA_CHANNEL_SEL__TX_SET((h),HPDI32_IO_DMA_CHANNEL_SEL_STATIC) |
| |
| #define | HPDI32_IO_DMA_CHANNEL_SEL__TX_DYNAMIC(h) HPDI32_IO_DMA_CHANNEL_SEL__TX_SET((h),HPDI32_IO_DMA_CHANNEL_SEL_DYNAMIC) |
| |
| #define | HPDI32_IO_DMA_CONTROL_MODE_MANUAL 0 |
| |
| #define | HPDI32_IO_DMA_CONTROL_MODE_AUTOMATIC 1 |
| |
| #define | HPDI32_IO_DMA_CONTROL_MODE_DEFAULT HPDI32_IO_DMA_CONTROL_MODE_AUTOMATIC |
| |
| #define | HPDI32_IO_DMA_CONTROL_MODE__GET(h, w, g) HPDI32_CONFIG_GET((h),HPDI32_IO_DMA_CONTROL_MODE,(w),(g)) |
| |
| #define | HPDI32_IO_DMA_CONTROL_MODE__SET(h, w, s) HPDI32_CONFIG_SET((h),HPDI32_IO_DMA_CONTROL_MODE,(w),(s)) |
| |
| #define | HPDI32_IO_DMA_CONTROL_MODE__RESET(h, w) HPDI32_CONFIG_SET((h),HPDI32_IO_DMA_CONTROL_MODE,(w),HPDI32_IO_DMA_CONTROL_MODE_DEFAULT) |
| |
| #define | HPDI32_IO_DMA_CONTROL_MODE__RX_GET(h, g) HPDI32_IO_DMA_CONTROL_MODE__GET((h),HPDI32_WHICH_RX,(g)) |
| |
| #define | HPDI32_IO_DMA_CONTROL_MODE__RX_SET(h, s) HPDI32_IO_DMA_CONTROL_MODE__SET((h),HPDI32_WHICH_RX,(s)) |
| |
| #define | HPDI32_IO_DMA_CONTROL_MODE__RX_RESET(h) HPDI32_IO_DMA_CONTROL_MODE__SET((h),HPDI32_WHICH_RX,HPDI32_IO_DMA_CONTROL_MODE_DEFAULT) |
| |
| #define | HPDI32_IO_DMA_CONTROL_MODE__RX_MANUAL(h) HPDI32_IO_DMA_CONTROL_MODE__RX_SET((h),HPDI32_IO_DMA_CONTROL_MODE_MANUAL) |
| |
| #define | HPDI32_IO_DMA_CONTROL_MODE__RX_AUTO(h) HPDI32_IO_DMA_CONTROL_MODE__RX_SET((h),HPDI32_IO_DMA_CONTROL_MODE_AUTOMATIC) |
| |
| #define | HPDI32_IO_DMA_CONTROL_MODE__TX_GET(h, g) HPDI32_IO_DMA_CONTROL_MODE__GET((h),HPDI32_WHICH_TX,(g)) |
| |
| #define | HPDI32_IO_DMA_CONTROL_MODE__TX_SET(h, s) HPDI32_IO_DMA_CONTROL_MODE__SET((h),HPDI32_WHICH_TX,(s)) |
| |
| #define | HPDI32_IO_DMA_CONTROL_MODE__TX_RESET(h) HPDI32_IO_DMA_CONTROL_MODE__SET((h),HPDI32_WHICH_TX,HPDI32_IO_DMA_CONTROL_MODE_DEFAULT) |
| |
| #define | HPDI32_IO_DMA_CONTROL_MODE__TX_MANUAL(h) HPDI32_IO_DMA_CONTROL_MODE__TX_SET((h),HPDI32_IO_DMA_CONTROL_MODE_MANUAL) |
| |
| #define | HPDI32_IO_DMA_CONTROL_MODE__TX_AUTO(h) HPDI32_IO_DMA_CONTROL_MODE__TX_SET((h),HPDI32_IO_DMA_CONTROL_MODE_AUTOMATIC) |
| |
| #define | HPDI32_IO_DMA_PRIORITY_DISABLE 0 |
| |
| #define | HPDI32_IO_DMA_PRIORITY_ENABLE 1 |
| |
| #define | HPDI32_IO_DMA_PRIORITY_RX_DEFAULT HPDI32_IO_DMA_PRIORITY_DISABLE |
| |
| #define | HPDI32_IO_DMA_PRIORITY_TX_DEFAULT HPDI32_IO_DMA_PRIORITY_ENABLE |
| |
| #define | HPDI32_IO_DMA_PRIORITY__GET(h, w, g) HPDI32_CONFIG_GET((h),HPDI32_IO_DMA_PRIORITY,(w),(g)) |
| |
| #define | HPDI32_IO_DMA_PRIORITY__SET(h, w, s) HPDI32_CONFIG_SET((h),HPDI32_IO_DMA_PRIORITY,(w),(s)) |
| |
| #define | HPDI32_IO_DMA_PRIORITY__RX_GET(h, g) HPDI32_IO_DMA_PRIORITY__GET((h),HPDI32_WHICH_RX,(g)) |
| |
| #define | HPDI32_IO_DMA_PRIORITY__RX_SET(h, s) HPDI32_IO_DMA_PRIORITY__SET((h),HPDI32_WHICH_RX,(s)) |
| |
| #define | HPDI32_IO_DMA_PRIORITY__RX_RESET(h) HPDI32_IO_DMA_PRIORITY__SET((h),HPDI32_WHICH_RX,HPDI32_IO_DMA_PRIORITY_RX_DEFAULT) |
| |
| #define | HPDI32_IO_DMA_PRIORITY__RX_DISABLE(h) HPDI32_IO_DMA_PRIORITY__RX_SET((h),HPDI32_IO_DMA_PRIORITY_DISABLE) |
| |
| #define | HPDI32_IO_DMA_PRIORITY__RX_ENABLE(h) HPDI32_IO_DMA_PRIORITY__RX_SET((h),HPDI32_IO_DMA_PRIORITY_ENABLE) |
| |
| #define | HPDI32_IO_DMA_PRIORITY__TX_GET(h, g) HPDI32_IO_DMA_PRIORITY__GET((h),HPDI32_WHICH_TX,(g)) |
| |
| #define | HPDI32_IO_DMA_PRIORITY__TX_SET(h, s) HPDI32_IO_DMA_PRIORITY__SET((h),HPDI32_WHICH_TX,(s)) |
| |
| #define | HPDI32_IO_DMA_PRIORITY__TX_RESET(h) HPDI32_IO_DMA_PRIORITY__SET((h),HPDI32_WHICH_TX,HPDI32_IO_DMA_PRIORITY_TX_DEFAULT) |
| |
| #define | HPDI32_IO_DMA_PRIORITY__TX_DISABLE(h) HPDI32_IO_DMA_PRIORITY__TX_SET((h),HPDI32_IO_DMA_PRIORITY_DISABLE) |
| |
| #define | HPDI32_IO_DMA_PRIORITY__TX_ENABLE(h) HPDI32_IO_DMA_PRIORITY__TX_SET((h),HPDI32_IO_DMA_PRIORITY_ENABLE) |
| |
| #define | HPDI32_IO_MODE_PIO 0 |
| |
| #define | HPDI32_IO_MODE_DMA 1 |
| |
| #define | HPDI32_IO_MODE_DMDMA 2 |
| |
| #define | HPDI32_IO_MODE_DEFAULT HPDI32_IO_MODE_DMDMA |
| |
| #define | HPDI32_IO_MODE__GET(h, w, g) HPDI32_CONFIG_GET((h),HPDI32_IO_MODE,(w),(g)) |
| |
| #define | HPDI32_IO_MODE__SET(h, w, s) HPDI32_CONFIG_SET((h),HPDI32_IO_MODE,(w),(s)) |
| |
| #define | HPDI32_IO_MODE__RESET(h, w) HPDI32_CONFIG_SET((h),HPDI32_IO_MODE,(w),HPDI32_IO_MODE_DEFAULT) |
| |
| #define | HPDI32_IO_MODE__RX_GET(h, g) HPDI32_IO_MODE__GET((h),HPDI32_WHICH_RX,(g)) |
| |
| #define | HPDI32_IO_MODE__RX_SET(h, s) HPDI32_IO_MODE__SET((h),HPDI32_WHICH_RX,(s)) |
| |
| #define | HPDI32_IO_MODE__RX_RESET(h) HPDI32_IO_MODE__SET((h),HPDI32_WHICH_RX,HPDI32_IO_MODE_DEFAULT) |
| |
| #define | HPDI32_IO_MODE__RX_PIO(h) HPDI32_IO_MODE__RX_SET((h),HPDI32_IO_MODE_PIO) |
| |
| #define | HPDI32_IO_MODE__RX_DMA(h) HPDI32_IO_MODE__RX_SET((h),HPDI32_IO_MODE_DMA) |
| |
| #define | HPDI32_IO_MODE__RX_DMDMA(h) HPDI32_IO_MODE__RX_SET((h),HPDI32_IO_MODE_DMDMA) |
| |
| #define | HPDI32_IO_MODE__TX_GET(h, g) HPDI32_IO_MODE__GET((h),HPDI32_WHICH_TX,(g)) |
| |
| #define | HPDI32_IO_MODE__TX_SET(h, s) HPDI32_IO_MODE__SET((h),HPDI32_WHICH_TX,(s)) |
| |
| #define | HPDI32_IO_MODE__TX_RESET(h) HPDI32_IO_MODE__SET((h),HPDI32_WHICH_TX,HPDI32_IO_MODE_DEFAULT) |
| |
| #define | HPDI32_IO_MODE__TX_PIO(h) HPDI32_IO_MODE__TX_SET((h),HPDI32_IO_MODE_PIO) |
| |
| #define | HPDI32_IO_MODE__TX_DMA(h) HPDI32_IO_MODE__TX_SET((h),HPDI32_IO_MODE_DMA) |
| |
| #define | HPDI32_IO_MODE__TX_DMDMA(h) HPDI32_IO_MODE__TX_SET((h),HPDI32_IO_MODE_DMDMA) |
| |
| #define | HPDI32_IO_OVERLAP_ENABLE_NO 0 |
| |
| #define | HPDI32_IO_OVERLAP_ENABLE_YES 1 |
| |
| #define | HPDI32_IO_OVERLAP_ENABLE_DEFAULT HPDI32_IO_OVERLAP_ENABLE_NO |
| |
| #define | HPDI32_IO_OVERLAP_ENABLE__GET(h, w, g) HPDI32_CONFIG_GET((h),HPDI32_IO_OVERLAP_ENABLE,(w),(g)) |
| |
| #define | HPDI32_IO_OVERLAP_ENABLE__SET(h, w, s) HPDI32_CONFIG_SET((h),HPDI32_IO_OVERLAP_ENABLE,(w),(s)) |
| |
| #define | HPDI32_IO_OVERLAP_ENABLE__RESET(h, w) HPDI32_CONFIG_SET((h),HPDI32_IO_OVERLAP_ENABLE,(w),HPDI32_IO_OVERLAP_ENABLE_DEFAULT) |
| |
| #define | HPDI32_IO_OVERLAP_ENABLE__RX_GET(h, g) HPDI32_IO_OVERLAP_ENABLE__GET((h),HPDI32_WHICH_RX,(g)) |
| |
| #define | HPDI32_IO_OVERLAP_ENABLE__RX_SET(h, s) HPDI32_IO_OVERLAP_ENABLE__SET((h),HPDI32_WHICH_RX,(s)) |
| |
| #define | HPDI32_IO_OVERLAP_ENABLE__RX_RESET(h) HPDI32_IO_OVERLAP_ENABLE__SET((h),HPDI32_WHICH_RX,HPDI32_IO_OVERLAP_ENABLE_DEFAULT) |
| |
| #define | HPDI32_IO_OVERLAP_ENABLE__RX_NO(h) HPDI32_IO_OVERLAP_ENABLE__RX_SET((h),HPDI32_IO_OVERLAP_ENABLE_NO) |
| |
| #define | HPDI32_IO_OVERLAP_ENABLE__RX_YES(h) HPDI32_IO_OVERLAP_ENABLE__RX_SET((h),HPDI32_IO_OVERLAP_ENABLE_YES) |
| |
| #define | HPDI32_IO_OVERLAP_ENABLE__TX_GET(h, g) HPDI32_IO_OVERLAP_ENABLE__GET((h),HPDI32_WHICH_TX,(g)) |
| |
| #define | HPDI32_IO_OVERLAP_ENABLE__TX_SET(h, s) HPDI32_IO_OVERLAP_ENABLE__SET((h),HPDI32_WHICH_TX,(s)) |
| |
| #define | HPDI32_IO_OVERLAP_ENABLE__TX_RESET(h) HPDI32_IO_OVERLAP_ENABLE__SET((h),HPDI32_WHICH_TX,HPDI32_IO_OVERLAP_ENABLE_DEFAULT) |
| |
| #define | HPDI32_IO_OVERLAP_ENABLE__TX_NO(h) HPDI32_IO_OVERLAP_ENABLE__TX_SET((h),HPDI32_IO_OVERLAP_ENABLE_NO) |
| |
| #define | HPDI32_IO_OVERLAP_ENABLE__TX_YES(h) HPDI32_IO_OVERLAP_ENABLE__TX_SET((h),HPDI32_IO_OVERLAP_ENABLE_YES) |
| |
| #define | HPDI32_IO_PIO_THRESHOLD_NONE 0 |
| |
| #define | HPDI32_IO_PIO_THRESHOLD_DEFAULT 16 /* Samples */ |
| |
| #define | HPDI32_IO_PIO_THRESHOLD__GET(h, w, g) HPDI32_CONFIG_GET((h),HPDI32_IO_PIO_THRESHOLD,(w),(g)) |
| |
| #define | HPDI32_IO_PIO_THRESHOLD__SET(h, w, s) HPDI32_CONFIG_SET((h),HPDI32_IO_PIO_THRESHOLD,(w),(s)) |
| |
| #define | HPDI32_IO_PIO_THRESHOLD__RESET(h, w) HPDI32_CONFIG_SET((h),HPDI32_IO_PIO_THRESHOLD,(w),HPDI32_IO_PIO_THRESHOLD_DEFAULT) |
| |
| #define | HPDI32_IO_PIO_THRESHOLD__RX_GET(h, g) HPDI32_IO_PIO_THRESHOLD__GET((h),HPDI32_WHICH_RX,(g)) |
| |
| #define | HPDI32_IO_PIO_THRESHOLD__RX_SET(h, s) HPDI32_IO_PIO_THRESHOLD__SET((h),HPDI32_WHICH_RX,(s)) |
| |
| #define | HPDI32_IO_PIO_THRESHOLD__RX_RESET(h) HPDI32_IO_PIO_THRESHOLD__SET((h),HPDI32_WHICH_RX,HPDI32_IO_PIO_THRESHOLD_DEFAULT) |
| |
| #define | HPDI32_IO_PIO_THRESHOLD__RX_NONE(h) HPDI32_IO_PIO_THRESHOLD__RX_SET((h),HPDI32_IO_PIO_THRESHOLD_NONE) |
| |
| #define | HPDI32_IO_PIO_THRESHOLD__TX_GET(h, g) HPDI32_IO_PIO_THRESHOLD__GET((h),HPDI32_WHICH_TX,(g)) |
| |
| #define | HPDI32_IO_PIO_THRESHOLD__TX_SET(h, s) HPDI32_IO_PIO_THRESHOLD__SET((h),HPDI32_WHICH_TX,(s)) |
| |
| #define | HPDI32_IO_PIO_THRESHOLD__TX_RESET(h) HPDI32_IO_PIO_THRESHOLD__SET((h),HPDI32_WHICH_TX,HPDI32_IO_PIO_THRESHOLD_DEFAULT) |
| |
| #define | HPDI32_IO_PIO_THRESHOLD__TX_NONE(h) HPDI32_IO_PIO_THRESHOLD__TX_SET((h),HPDI32_IO_PIO_THRESHOLD_NONE) |
| |
| #define | HPDI32_IO_STATUS__GET(h, w, g) HPDI32_CONFIG_GET((h),HPDI32_IO_STATUS,(w),(g)) |
| |
| #define | HPDI32_IO_STATUS__RX_GET(h, g) HPDI32_IO_STATUS__GET((h),HPDI32_WHICH_RX,(g)) |
| |
| #define | HPDI32_IO_STATUS__TX_GET(h, g) HPDI32_IO_STATUS__GET((h),HPDI32_WHICH_TX,(g)) |
| |
| #define | HPDI32_IO_TIMEOUT_NO_WAIT 0 |
| |
| #define | HPDI32_IO_TIMEOUT_MAX 3600 /* 1 hour */ |
| |
| #define | HPDI32_IO_TIMEOUT_DEFAULT 10 /* seconds */ |
| |
| #define | HPDI32_IO_TIMEOUT__GET(h, w, g) HPDI32_CONFIG_GET((h),HPDI32_IO_TIMEOUT,(w),(g)) |
| |
| #define | HPDI32_IO_TIMEOUT__SET(h, w, s) HPDI32_CONFIG_SET((h),HPDI32_IO_TIMEOUT,(w),(s)) |
| |
| #define | HPDI32_IO_TIMEOUT__RESET(h, w) HPDI32_CONFIG_SET((h),HPDI32_IO_TIMEOUT,(w),HPDI32_IO_TIMEOUT_DEFAULT) |
| |
| #define | HPDI32_IO_TIMEOUT__RX_GET(h, g) HPDI32_IO_TIMEOUT__GET((h),HPDI32_WHICH_RX,(g)) |
| |
| #define | HPDI32_IO_TIMEOUT__RX_SET(h, s) HPDI32_IO_TIMEOUT__SET((h),HPDI32_WHICH_RX,(s)) |
| |
| #define | HPDI32_IO_TIMEOUT__RX_NO_WAIT(h) HPDI32_IO_TIMEOUT__RX_SET((h),HPDI32_IO_TIMEOUT_NO_WAIT) |
| |
| #define | HPDI32_IO_TIMEOUT__RX_RESET(h) HPDI32_IO_TIMEOUT__RX_SET((h),HPDI32_IO_TIMEOUT_DEFAULT) |
| |
| #define | HPDI32_IO_TIMEOUT__TX_GET(h, g) HPDI32_IO_TIMEOUT__GET((h),HPDI32_WHICH_TX,(g)) |
| |
| #define | HPDI32_IO_TIMEOUT__TX_SET(h, s) HPDI32_IO_TIMEOUT__SET((h),HPDI32_WHICH_TX,(s)) |
| |
| #define | HPDI32_IO_TIMEOUT__TX_NO_WAIT(h) HPDI32_IO_TIMEOUT__TX_SET((h),HPDI32_IO_TIMEOUT_NO_WAIT) |
| |
| #define | HPDI32_IO_TIMEOUT__TX_RESET(h) HPDI32_IO_TIMEOUT__TX_SET((h),HPDI32_IO_TIMEOUT_DEFAULT) |
| |
| #define | HPDI32_IO_SINGLE_CYCLE_ABSENT 0 |
| |
| #define | HPDI32_IO_SINGLE_CYCLE_PRESENT 1 |
| |
| #define | HPDI32_IO_SINGLE_CYCLE_DEFAULT HPDI32_IO_SINGLE_CYCLE_PRESENT |
| |
| #define | HPDI32_IO_SINGLE_CYCLE__GET(h, w, g) HPDI32_CONFIG_GET((h),HPDI32_IO_SINGLE_CYCLE,(w),(g)) |
| |
| #define | HPDI32_IO_SINGLE_CYCLE__SET(h, w, s) HPDI32_CONFIG_SET((h),HPDI32_IO_SINGLE_CYCLE,(w),(s)) |
| |
| #define | HPDI32_IO_SINGLE_CYCLE__RESET(h, w) HPDI32_CONFIG_SET((h),HPDI32_IO_SINGLE_CYCLE,(w),HPDI32_IO_SINGLE_CYCLE_DEFAULT) |
| |
| #define | HPDI32_IO_SINGLE_CYCLE__ABSENT(h, w) HPDI32_IO_SINGLE_CYCLE__SET((h),(w),HPDI32_IO_SINGLE_CYCLE_ABSENT) |
| |
| #define | HPDI32_IO_SINGLE_CYCLE__PRESENT(h, w) HPDI32_IO_SINGLE_CYCLE__SET((h),(w),HPDI32_IO_SINGLE_CYCLE_PRESENT) |
| |
| #define | HPDI32_IO_SINGLE_CYCLE__RX_GET(h, g) HPDI32_IO_SINGLE_CYCLE__GET((h),HPDI32_WHICH_RX,(g)) |
| |
| #define | HPDI32_IO_SINGLE_CYCLE__RX_SET(h, s) HPDI32_IO_SINGLE_CYCLE__SET((h),HPDI32_WHICH_RX,(s)) |
| |
| #define | HPDI32_IO_SINGLE_CYCLE__RX_ABSENT(h) HPDI32_IO_SINGLE_CYCLE__RX_SET((h),HPDI32_IO_SINGLE_CYCLE_ABSENT) |
| |
| #define | HPDI32_IO_SINGLE_CYCLE__RX_PRESENT(h) HPDI32_IO_SINGLE_CYCLE__RX_SET((h),HPDI32_IO_SINGLE_CYCLE_PRESENT) |
| |
| #define | HPDI32_IO_SINGLE_CYCLE__RX_RESET(h) HPDI32_IO_SINGLE_CYCLE__RX_SET((h),HPDI32_IO_SINGLE_CYCLE_DEFAULT) |
| |
| #define | HPDI32_IO_SINGLE_CYCLE__TX_GET(h, g) HPDI32_IO_SINGLE_CYCLE__GET((h),HPDI32_WHICH_TX,(g)) |
| |
| #define | HPDI32_IO_SINGLE_CYCLE__TX_SET(h, s) HPDI32_IO_SINGLE_CYCLE__SET((h),HPDI32_WHICH_TX,(s)) |
| |
| #define | HPDI32_IO_SINGLE_CYCLE__TX_ABSENT(h) HPDI32_IO_SINGLE_CYCLE__TX_SET((h),HPDI32_IO_SINGLE_CYCLE_ABSENT) |
| |
| #define | HPDI32_IO_SINGLE_CYCLE__TX_PRESENT(h) HPDI32_IO_SINGLE_CYCLE__TX_SET((h),HPDI32_IO_SINGLE_CYCLE_PRESENT) |
| |
| #define | HPDI32_IO_SINGLE_CYCLE__TX_RESET(h) HPDI32_IO_SINGLE_CYCLE__TX_SET((h),HPDI32_IO_SINGLE_CYCLE_DEFAULT) |
| |
| #define | HPDI32_IRQ_ENCODE(i) HPDI32_CONFIG_ENCODE(HPDI32_CONFIG_GROUP_IRQ, (i)) |
| |
| #define | HPDI32_IRQ_CALLBACK_ARG HPDI32_IRQ_ENCODE(0) /* which: IRQ# */ |
| |
| #define | HPDI32_IRQ_CALLBACK_FUNC HPDI32_IRQ_ENCODE(1) /* which: IRQ# */ |
| |
| #define | HPDI32_IRQ_ENABLE HPDI32_IRQ_ENCODE(2) /* which: IRQ# */ |
| |
| #define | HPDI32_IRQ_STATE HPDI32_IRQ_ENCODE(3) /* which: IRQ# */ |
| |
| #define | HPDI32_IRQ_TRIGGER_CONFIG HPDI32_IRQ_ENCODE(4) /* which: IRQ# */ |
| |
| #define | HPDI32_IRQ_CALLBACK_ARG_DEFAULT 0 |
| |
| #define | HPDI32_IRQ_CALLBACK_ARG__GET(h, w, g) HPDI32_CONFIG_GET((h),HPDI32_IRQ_CALLBACK_ARG,(w),(g)) |
| |
| #define | HPDI32_IRQ_CALLBACK_ARG__SET(h, w, s) HPDI32_CONFIG_SET((h),HPDI32_IRQ_CALLBACK_ARG,(w),(s)) |
| |
| #define | HPDI32_IRQ_CALLBACK_ARG__C0A_GET(h, g) HPDI32_IRQ_CALLBACK_ARG__GET((h),HPDI32_WHICH_IRQ_C0A_,(g)) |
| |
| #define | HPDI32_IRQ_CALLBACK_ARG__C0A_SET(h, s) HPDI32_IRQ_CALLBACK_ARG__SET((h),HPDI32_WHICH_IRQ_C0A_,(s)) |
| |
| #define | HPDI32_IRQ_CALLBACK_ARG__C0A_RESET(h) HPDI32_IRQ_CALLBACK_ARG__SET((h),HPDI32_WHICH_IRQ_C0A_,HPDI32_IRQ_CALLBACK_ARG_DEFAULT) |
| |
| #define | HPDI32_IRQ_CALLBACK_ARG__C0I_GET(h, g) HPDI32_IRQ_CALLBACK_ARG__GET((h),HPDI32_WHICH_IRQ_C0I_,(g)) |
| |
| #define | HPDI32_IRQ_CALLBACK_ARG__C0I_SET(h, s) HPDI32_IRQ_CALLBACK_ARG__SET((h),HPDI32_WHICH_IRQ_C0I_,(s)) |
| |
| #define | HPDI32_IRQ_CALLBACK_ARG__C0I_RESET(h) HPDI32_IRQ_CALLBACK_ARG__SET((h),HPDI32_WHICH_IRQ_C0I_,HPDI32_IRQ_CALLBACK_ARG_DEFAULT) |
| |
| #define | HPDI32_IRQ_CALLBACK_ARG__C1_GET(h, g) HPDI32_IRQ_CALLBACK_ARG__GET((h),HPDI32_WHICH_IRQ_C1_,(g)) |
| |
| #define | HPDI32_IRQ_CALLBACK_ARG__C1_SET(h, s) HPDI32_IRQ_CALLBACK_ARG__SET((h),HPDI32_WHICH_IRQ_C1_,(s)) |
| |
| #define | HPDI32_IRQ_CALLBACK_ARG__C1_RESET(h) HPDI32_IRQ_CALLBACK_ARG__SET((h),HPDI32_WHICH_IRQ_C1_,HPDI32_IRQ_CALLBACK_ARG_DEFAULT) |
| |
| #define | HPDI32_IRQ_CALLBACK_ARG__C2_GET(h, g) HPDI32_IRQ_CALLBACK_ARG__GET((h),HPDI32_WHICH_IRQ_C2_,(g)) |
| |
| #define | HPDI32_IRQ_CALLBACK_ARG__C2_SET(h, s) HPDI32_IRQ_CALLBACK_ARG__SET((h),HPDI32_WHICH_IRQ_C2_,(s)) |
| |
| #define | HPDI32_IRQ_CALLBACK_ARG__C2_RESET(h) HPDI32_IRQ_CALLBACK_ARG__SET((h),HPDI32_WHICH_IRQ_C2_,HPDI32_IRQ_CALLBACK_ARG_DEFAULT) |
| |
| #define | HPDI32_IRQ_CALLBACK_ARG__C3_GET(h, g) HPDI32_IRQ_CALLBACK_ARG__GET((h),HPDI32_WHICH_IRQ_C3_,(g)) |
| |
| #define | HPDI32_IRQ_CALLBACK_ARG__C3_SET(h, s) HPDI32_IRQ_CALLBACK_ARG__SET((h),HPDI32_WHICH_IRQ_C3_,(s)) |
| |
| #define | HPDI32_IRQ_CALLBACK_ARG__C3_RESET(h) HPDI32_IRQ_CALLBACK_ARG__SET((h),HPDI32_WHICH_IRQ_C3_,HPDI32_IRQ_CALLBACK_ARG_DEFAULT) |
| |
| #define | HPDI32_IRQ_CALLBACK_ARG__C4_GET(h, g) HPDI32_IRQ_CALLBACK_ARG__GET((h),HPDI32_WHICH_IRQ_C4_,(g)) |
| |
| #define | HPDI32_IRQ_CALLBACK_ARG__C4_SET(h, s) HPDI32_IRQ_CALLBACK_ARG__SET((h),HPDI32_WHICH_IRQ_C4_,(s)) |
| |
| #define | HPDI32_IRQ_CALLBACK_ARG__C4_RESET(h) HPDI32_IRQ_CALLBACK_ARG__SET((h),HPDI32_WHICH_IRQ_C4_,HPDI32_IRQ_CALLBACK_ARG_DEFAULT) |
| |
| #define | HPDI32_IRQ_CALLBACK_ARG__C5_GET(h, g) HPDI32_IRQ_CALLBACK_ARG__GET((h),HPDI32_WHICH_IRQ_C5_,(g)) |
| |
| #define | HPDI32_IRQ_CALLBACK_ARG__C5_SET(h, s) HPDI32_IRQ_CALLBACK_ARG__SET((h),HPDI32_WHICH_IRQ_C5_,(s)) |
| |
| #define | HPDI32_IRQ_CALLBACK_ARG__C5_RESET(h) HPDI32_IRQ_CALLBACK_ARG__SET((h),HPDI32_WHICH_IRQ_C5_,HPDI32_IRQ_CALLBACK_ARG_DEFAULT) |
| |
| #define | HPDI32_IRQ_CALLBACK_ARG__C6_GET(h, g) HPDI32_IRQ_CALLBACK_ARG__GET((h),HPDI32_WHICH_IRQ_C6_,(g)) |
| |
| #define | HPDI32_IRQ_CALLBACK_ARG__C6_SET(h, s) HPDI32_IRQ_CALLBACK_ARG__SET((h),HPDI32_WHICH_IRQ_C6_,(s)) |
| |
| #define | HPDI32_IRQ_CALLBACK_ARG__C6_RESET(h) HPDI32_IRQ_CALLBACK_ARG__SET((h),HPDI32_WHICH_IRQ_C6_,HPDI32_IRQ_CALLBACK_ARG_DEFAULT) |
| |
| #define | HPDI32_IRQ_CALLBACK_ARG__TX_E_GET(h, g) HPDI32_IRQ_CALLBACK_ARG__GET((h),HPDI32_WHICH_IRQ_TX_E,(g)) |
| |
| #define | HPDI32_IRQ_CALLBACK_ARG__TX_E_SET(h, s) HPDI32_IRQ_CALLBACK_ARG__SET((h),HPDI32_WHICH_IRQ_TX_E,(s)) |
| |
| #define | HPDI32_IRQ_CALLBACK_ARG__TX_E_RESET(h) HPDI32_IRQ_CALLBACK_ARG__SET((h),HPDI32_WHICH_IRQ_TX_E,HPDI32_IRQ_CALLBACK_ARG_DEFAULT) |
| |
| #define | HPDI32_IRQ_CALLBACK_ARG__TX_AE_GET(h, g) HPDI32_IRQ_CALLBACK_ARG__GET((h),HPDI32_WHICH_IRQ_TX_AE,(g)) |
| |
| #define | HPDI32_IRQ_CALLBACK_ARG__TX_AE_SET(h, s) HPDI32_IRQ_CALLBACK_ARG__SET((h),HPDI32_WHICH_IRQ_TX_AE,(s)) |
| |
| #define | HPDI32_IRQ_CALLBACK_ARG__TX_AE_RESET(h) HPDI32_IRQ_CALLBACK_ARG__SET((h),HPDI32_WHICH_IRQ_TX_AE,HPDI32_IRQ_CALLBACK_ARG_DEFAULT) |
| |
| #define | HPDI32_IRQ_CALLBACK_ARG__TX_AF_GET(h, g) HPDI32_IRQ_CALLBACK_ARG__GET((h),HPDI32_WHICH_IRQ_TX_AF,(g)) |
| |
| #define | HPDI32_IRQ_CALLBACK_ARG__TX_AF_SET(h, s) HPDI32_IRQ_CALLBACK_ARG__SET((h),HPDI32_WHICH_IRQ_TX_AF,(s)) |
| |
| #define | HPDI32_IRQ_CALLBACK_ARG__TX_AF_RESET(h) HPDI32_IRQ_CALLBACK_ARG__SET((h),HPDI32_WHICH_IRQ_TX_AF,HPDI32_IRQ_CALLBACK_ARG_DEFAULT) |
| |
| #define | HPDI32_IRQ_CALLBACK_ARG__TX_F_GET(h, g) HPDI32_IRQ_CALLBACK_ARG__GET((h),HPDI32_WHICH_IRQ_TX_F,(g)) |
| |
| #define | HPDI32_IRQ_CALLBACK_ARG__TX_F_SET(h, s) HPDI32_IRQ_CALLBACK_ARG__SET((h),HPDI32_WHICH_IRQ_TX_F,(s)) |
| |
| #define | HPDI32_IRQ_CALLBACK_ARG__TX_F_RESET(h) HPDI32_IRQ_CALLBACK_ARG__SET((h),HPDI32_WHICH_IRQ_TX_F,HPDI32_IRQ_CALLBACK_ARG_DEFAULT) |
| |
| #define | HPDI32_IRQ_CALLBACK_ARG__RX_E_GET(h, g) HPDI32_IRQ_CALLBACK_ARG__GET((h),HPDI32_WHICH_IRQ_RX_E,(g)) |
| |
| #define | HPDI32_IRQ_CALLBACK_ARG__RX_E_SET(h, s) HPDI32_IRQ_CALLBACK_ARG__SET((h),HPDI32_WHICH_IRQ_RX_E,(s)) |
| |
| #define | HPDI32_IRQ_CALLBACK_ARG__RX_E_RESET(h) HPDI32_IRQ_CALLBACK_ARG__SET((h),HPDI32_WHICH_IRQ_RX_E,HPDI32_IRQ_CALLBACK_ARG_DEFAULT) |
| |
| #define | HPDI32_IRQ_CALLBACK_ARG__RX_AE_GET(h, g) HPDI32_IRQ_CALLBACK_ARG__GET((h),HPDI32_WHICH_IRQ_RX_AE,(g)) |
| |
| #define | HPDI32_IRQ_CALLBACK_ARG__RX_AE_SET(h, s) HPDI32_IRQ_CALLBACK_ARG__SET((h),HPDI32_WHICH_IRQ_RX_AE,(s)) |
| |
| #define | HPDI32_IRQ_CALLBACK_ARG__RX_AE_RESET(h) HPDI32_IRQ_CALLBACK_ARG__SET((h),HPDI32_WHICH_IRQ_RX_AE,HPDI32_IRQ_CALLBACK_ARG_DEFAULT) |
| |
| #define | HPDI32_IRQ_CALLBACK_ARG__RX_AF_GET(h, g) HPDI32_IRQ_CALLBACK_ARG__GET((h),HPDI32_WHICH_IRQ_RX_AF,(g)) |
| |
| #define | HPDI32_IRQ_CALLBACK_ARG__RX_AF_SET(h, s) HPDI32_IRQ_CALLBACK_ARG__SET((h),HPDI32_WHICH_IRQ_RX_AF,(s)) |
| |
| #define | HPDI32_IRQ_CALLBACK_ARG__RX_AF_RESET(h) HPDI32_IRQ_CALLBACK_ARG__SET((h),HPDI32_WHICH_IRQ_RX_AF,HPDI32_IRQ_CALLBACK_ARG_DEFAULT) |
| |
| #define | HPDI32_IRQ_CALLBACK_ARG__RX_F_GET(h, g) HPDI32_IRQ_CALLBACK_ARG__GET((h),HPDI32_WHICH_IRQ_RX_F,(g)) |
| |
| #define | HPDI32_IRQ_CALLBACK_ARG__RX_F_SET(h, s) HPDI32_IRQ_CALLBACK_ARG__SET((h),HPDI32_WHICH_IRQ_RX_F,(s)) |
| |
| #define | HPDI32_IRQ_CALLBACK_ARG__RX_F_RESET(h) HPDI32_IRQ_CALLBACK_ARG__SET((h),HPDI32_WHICH_IRQ_RX_F,HPDI32_IRQ_CALLBACK_ARG_DEFAULT) |
| |
| #define | HPDI32_IRQ_CALLBACK_ARG__FVB_GET(h, g) HPDI32_IRQ_CALLBACK_ARG__C0A_GET((h),(g)) |
| |
| #define | HPDI32_IRQ_CALLBACK_ARG__FVB_SET(h, s) HPDI32_IRQ_CALLBACK_ARG__C0A_SET((h),(s)) |
| |
| #define | HPDI32_IRQ_CALLBACK_ARG__FVB_RESET(h) HPDI32_IRQ_CALLBACK_ARG__C0A_SET((h),HPDI32_IRQ_CALLBACK_ARG_DEFAULT) |
| |
| #define | HPDI32_IRQ_CALLBACK_ARG__FVE_GET(h, g) HPDI32_IRQ_CALLBACK_ARG__C0I_GET((h),(g)) |
| |
| #define | HPDI32_IRQ_CALLBACK_ARG__FVE_SET(h, s) HPDI32_IRQ_CALLBACK_ARG__C0I_SET((h),(s)) |
| |
| #define | HPDI32_IRQ_CALLBACK_ARG__FVE_RESET(h) HPDI32_IRQ_CALLBACK_ARG__C0I_SET((h),HPDI32_IRQ_CALLBACK_ARG_DEFAULT) |
| |
| #define | HPDI32_IRQ_CALLBACK_ARG__LV_GET(h, g) HPDI32_IRQ_CALLBACK_ARG__C1_GET((h),(g)) |
| |
| #define | HPDI32_IRQ_CALLBACK_ARG__LV_SET(h, s) HPDI32_IRQ_CALLBACK_ARG__C1_SET((h),(s)) |
| |
| #define | HPDI32_IRQ_CALLBACK_ARG__LV_RESET(h) HPDI32_IRQ_CALLBACK_ARG__C1_SET((h),HPDI32_IRQ_CALLBACK_ARG_DEFAULT) |
| |
| #define | HPDI32_IRQ_CALLBACK_ARG__SV_GET(h, g) HPDI32_IRQ_CALLBACK_ARG__C2_GET((h),(g)) |
| |
| #define | HPDI32_IRQ_CALLBACK_ARG__SV_SET(h, s) HPDI32_IRQ_CALLBACK_ARG__C2_SET((h),(s)) |
| |
| #define | HPDI32_IRQ_CALLBACK_ARG__SV_RESET(h) HPDI32_IRQ_CALLBACK_ARG__C2_SET((h),HPDI32_IRQ_CALLBACK_ARG_DEFAULT) |
| |
| #define | HPDI32_IRQ_CALLBACK_ARG__RR_GET(h, g) HPDI32_IRQ_CALLBACK_ARG__C3_GET((h),(g)) |
| |
| #define | HPDI32_IRQ_CALLBACK_ARG__RR_SET(h, s) HPDI32_IRQ_CALLBACK_ARG__C3_SET((h),(s)) |
| |
| #define | HPDI32_IRQ_CALLBACK_ARG__RR_RESET(h) HPDI32_IRQ_CALLBACK_ARG__C3_SET((h),HPDI32_IRQ_CALLBACK_ARG_DEFAULT) |
| |
| #define | HPDI32_IRQ_CALLBACK_ARG__TR_GET(h, g) HPDI32_IRQ_CALLBACK_ARG__C4_GET((h),(g)) |
| |
| #define | HPDI32_IRQ_CALLBACK_ARG__TR_SET(h, s) HPDI32_IRQ_CALLBACK_ARG__C4_SET((h),(s)) |
| |
| #define | HPDI32_IRQ_CALLBACK_ARG__TR_RESET(h) HPDI32_IRQ_CALLBACK_ARG__C4_SET((h),HPDI32_IRQ_CALLBACK_ARG_DEFAULT) |
| |
| #define | HPDI32_IRQ_CALLBACK_ARG__TE_GET(h, g) HPDI32_IRQ_CALLBACK_ARG__C5_GET((h),(g)) |
| |
| #define | HPDI32_IRQ_CALLBACK_ARG__TE_SET(h, s) HPDI32_IRQ_CALLBACK_ARG__C5_SET((h),(s)) |
| |
| #define | HPDI32_IRQ_CALLBACK_ARG__TE_RESET(h) HPDI32_IRQ_CALLBACK_ARG__C5_SET((h),HPDI32_IRQ_CALLBACK_ARG_DEFAULT) |
| |
| #define | HPDI32_IRQ_CALLBACK_ARG__RE_GET(h, g) HPDI32_IRQ_CALLBACK_ARG__C6_GET((h),(g)) |
| |
| #define | HPDI32_IRQ_CALLBACK_ARG__RE_SET(h, s) HPDI32_IRQ_CALLBACK_ARG__C6_SET((h),(s)) |
| |
| #define | HPDI32_IRQ_CALLBACK_ARG__RE_RESET(h) HPDI32_IRQ_CALLBACK_ARG__C6_SET((h),HPDI32_IRQ_CALLBACK_ARG_DEFAULT) |
| |
| #define | HPDI32_IRQ_CALLBACK_ARG__GPIO_0_GET(h, g) HPDI32_IRQ_CALLBACK_ARG__C1_GET((h),(g)) |
| |
| #define | HPDI32_IRQ_CALLBACK_ARG__GPIO_0_SET(h, s) HPDI32_IRQ_CALLBACK_ARG__C1_SET((h),(s)) |
| |
| #define | HPDI32_IRQ_CALLBACK_ARG__GPIO_0_RESET(h) HPDI32_IRQ_CALLBACK_ARG__C1_SET((h),HPDI32_IRQ_CALLBACK_ARG_DEFAULT) |
| |
| #define | HPDI32_IRQ_CALLBACK_ARG__GPIO_1_GET(h, g) HPDI32_IRQ_CALLBACK_ARG__C2_GET((h),(g)) |
| |
| #define | HPDI32_IRQ_CALLBACK_ARG__GPIO_1_SET(h, s) HPDI32_IRQ_CALLBACK_ARG__C2_SET((h),(s)) |
| |
| #define | HPDI32_IRQ_CALLBACK_ARG__GPIO_1_RESET(h) HPDI32_IRQ_CALLBACK_ARG__C2_SET((h),HPDI32_IRQ_CALLBACK_ARG_DEFAULT) |
| |
| #define | HPDI32_IRQ_CALLBACK_ARG__GPIO_2_GET(h, g) HPDI32_IRQ_CALLBACK_ARG__C3_GET((h),(g)) |
| |
| #define | HPDI32_IRQ_CALLBACK_ARG__GPIO_2_SET(h, s) HPDI32_IRQ_CALLBACK_ARG__C3_SET((h),(s)) |
| |
| #define | HPDI32_IRQ_CALLBACK_ARG__GPIO_2_RESET(h) HPDI32_IRQ_CALLBACK_ARG__C3_SET((h),HPDI32_IRQ_CALLBACK_ARG_DEFAULT) |
| |
| #define | HPDI32_IRQ_CALLBACK_ARG__GPIO_3_GET(h, g) HPDI32_IRQ_CALLBACK_ARG__C4_GET((h),(g)) |
| |
| #define | HPDI32_IRQ_CALLBACK_ARG__GPIO_3_SET(h, s) HPDI32_IRQ_CALLBACK_ARG__C4_SET((h),(s)) |
| |
| #define | HPDI32_IRQ_CALLBACK_ARG__GPIO_3_RESET(h) HPDI32_IRQ_CALLBACK_ARG__C4_SET((h),HPDI32_IRQ_CALLBACK_ARG_DEFAULT) |
| |
| #define | HPDI32_IRQ_CALLBACK_ARG__GPIO_4_GET(h, g) HPDI32_IRQ_CALLBACK_ARG__C5_GET((h),(g)) |
| |
| #define | HPDI32_IRQ_CALLBACK_ARG__GPIO_4_SET(h, s) HPDI32_IRQ_CALLBACK_ARG__C5_SET((h),(s)) |
| |
| #define | HPDI32_IRQ_CALLBACK_ARG__GPIO_4_RESET(h) HPDI32_IRQ_CALLBACK_ARG__C5_SET((h),HPDI32_IRQ_CALLBACK_ARG_DEFAULT) |
| |
| #define | HPDI32_IRQ_CALLBACK_ARG__GPIO_5_GET(h, g) HPDI32_IRQ_CALLBACK_ARG__C6_GET((h),(g)) |
| |
| #define | HPDI32_IRQ_CALLBACK_ARG__GPIO_5_SET(h, s) HPDI32_IRQ_CALLBACK_ARG__C6_SET((h),(s)) |
| |
| #define | HPDI32_IRQ_CALLBACK_ARG__GPIO_5_RESET(h) HPDI32_IRQ_CALLBACK_ARG__C6_SET((h),HPDI32_IRQ_CALLBACK_ARG_DEFAULT) |
| |
| #define | HPDI32_IRQ_CALLBACK_ARG__GPIO_6H_GET(h, g) HPDI32_IRQ_CALLBACK_ARG__C0A_GET((h),(g)) |
| |
| #define | HPDI32_IRQ_CALLBACK_ARG__GPIO_6H_SET(h, s) HPDI32_IRQ_CALLBACK_ARG__C0A_SET((h),(s)) |
| |
| #define | HPDI32_IRQ_CALLBACK_ARG__GPIO_6H_RESET(h) HPDI32_IRQ_CALLBACK_ARG__C0A_SET((h),HPDI32_IRQ_CALLBACK_ARG_DEFAULT) |
| |
| #define | HPDI32_IRQ_CALLBACK_ARG__GPIO_6L_GET(h, g) HPDI32_IRQ_CALLBACK_ARG__C0I_GET((h),(g)) |
| |
| #define | HPDI32_IRQ_CALLBACK_ARG__GPIO_6L_SET(h, s) HPDI32_IRQ_CALLBACK_ARG__C0I_SET((h),(s)) |
| |
| #define | HPDI32_IRQ_CALLBACK_ARG__GPIO_6L_RESET(h) HPDI32_IRQ_CALLBACK_ARG__C0I_SET((h),HPDI32_IRQ_CALLBACK_ARG_DEFAULT) |
| |
| #define | HPDI32_IRQ_CALLBACK_FUNC_DEFAULT 0 |
| |
| #define | HPDI32_IRQ_CALLBACK_FUNC__GET(h, w, g) HPDI32_CONFIG_GET((h),HPDI32_IRQ_CALLBACK_FUNC,(w),(g)) |
| |
| #define | HPDI32_IRQ_CALLBACK_FUNC__SET(h, w, s) HPDI32_CONFIG_SET((h),HPDI32_IRQ_CALLBACK_FUNC,(w),(s)) |
| |
| #define | HPDI32_IRQ_CALLBACK_FUNC__RESET(h, w) HPDI32_CONFIG_SET((h),HPDI32_IRQ_CALLBACK_FUNC,(w),HPDI32_IRQ_CALLBACK_FUNC_DEFAULT) |
| |
| #define | HPDI32_IRQ_CALLBACK_FUNC__C0A_GET(h, g) HPDI32_IRQ_CALLBACK_FUNC__GET((h),HPDI32_WHICH_IRQ_C0A_,(g)) |
| |
| #define | HPDI32_IRQ_CALLBACK_FUNC__C0A_SET(h, s) HPDI32_IRQ_CALLBACK_FUNC__SET((h),HPDI32_WHICH_IRQ_C0A_,(s)) |
| |
| #define | HPDI32_IRQ_CALLBACK_FUNC__C0A_RESET(h) HPDI32_IRQ_CALLBACK_FUNC__SET((h),HPDI32_WHICH_IRQ_C0A_,HPDI32_IRQ_CALLBACK_FUNC_DEFAULT) |
| |
| #define | HPDI32_IRQ_CALLBACK_FUNC__C0I_GET(h, g) HPDI32_IRQ_CALLBACK_FUNC__GET((h),HPDI32_WHICH_IRQ_C0I_,(g)) |
| |
| #define | HPDI32_IRQ_CALLBACK_FUNC__C0I_SET(h, s) HPDI32_IRQ_CALLBACK_FUNC__SET((h),HPDI32_WHICH_IRQ_C0I_,(s)) |
| |
| #define | HPDI32_IRQ_CALLBACK_FUNC__C0I_RESET(h) HPDI32_IRQ_CALLBACK_FUNC__SET((h),HPDI32_WHICH_IRQ_C0I_,HPDI32_IRQ_CALLBACK_FUNC_DEFAULT) |
| |
| #define | HPDI32_IRQ_CALLBACK_FUNC__C1_GET(h, g) HPDI32_IRQ_CALLBACK_FUNC__GET((h),HPDI32_WHICH_IRQ_C1_,(g)) |
| |
| #define | HPDI32_IRQ_CALLBACK_FUNC__C1_SET(h, s) HPDI32_IRQ_CALLBACK_FUNC__SET((h),HPDI32_WHICH_IRQ_C1_,(s)) |
| |
| #define | HPDI32_IRQ_CALLBACK_FUNC__C1_RESET(h) HPDI32_IRQ_CALLBACK_FUNC__SET((h),HPDI32_WHICH_IRQ_C1_,HPDI32_IRQ_CALLBACK_FUNC_DEFAULT) |
| |
| #define | HPDI32_IRQ_CALLBACK_FUNC__C2_GET(h, g) HPDI32_IRQ_CALLBACK_FUNC__GET((h),HPDI32_WHICH_IRQ_C2_,(g)) |
| |
| #define | HPDI32_IRQ_CALLBACK_FUNC__C2_SET(h, s) HPDI32_IRQ_CALLBACK_FUNC__SET((h),HPDI32_WHICH_IRQ_C2_,(s)) |
| |
| #define | HPDI32_IRQ_CALLBACK_FUNC__C2_RESET(h) HPDI32_IRQ_CALLBACK_FUNC__SET((h),HPDI32_WHICH_IRQ_C2_,HPDI32_IRQ_CALLBACK_FUNC_DEFAULT) |
| |
| #define | HPDI32_IRQ_CALLBACK_FUNC__C3_GET(h, g) HPDI32_IRQ_CALLBACK_FUNC__GET((h),HPDI32_WHICH_IRQ_C3_,(g)) |
| |
| #define | HPDI32_IRQ_CALLBACK_FUNC__C3_SET(h, s) HPDI32_IRQ_CALLBACK_FUNC__SET((h),HPDI32_WHICH_IRQ_C3_,(s)) |
| |
| #define | HPDI32_IRQ_CALLBACK_FUNC__C3_RESET(h) HPDI32_IRQ_CALLBACK_FUNC__SET((h),HPDI32_WHICH_IRQ_C3_,HPDI32_IRQ_CALLBACK_FUNC_DEFAULT) |
| |
| #define | HPDI32_IRQ_CALLBACK_FUNC__C4_GET(h, g) HPDI32_IRQ_CALLBACK_FUNC__GET((h),HPDI32_WHICH_IRQ_C4_,(g)) |
| |
| #define | HPDI32_IRQ_CALLBACK_FUNC__C4_SET(h, s) HPDI32_IRQ_CALLBACK_FUNC__SET((h),HPDI32_WHICH_IRQ_C4_,(s)) |
| |
| #define | HPDI32_IRQ_CALLBACK_FUNC__C4_RESET(h) HPDI32_IRQ_CALLBACK_FUNC__SET((h),HPDI32_WHICH_IRQ_C4_,HPDI32_IRQ_CALLBACK_FUNC_DEFAULT) |
| |
| #define | HPDI32_IRQ_CALLBACK_FUNC__C5_GET(h, g) HPDI32_IRQ_CALLBACK_FUNC__GET((h),HPDI32_WHICH_IRQ_C5_,(g)) |
| |
| #define | HPDI32_IRQ_CALLBACK_FUNC__C5_SET(h, s) HPDI32_IRQ_CALLBACK_FUNC__SET((h),HPDI32_WHICH_IRQ_C5_,(s)) |
| |
| #define | HPDI32_IRQ_CALLBACK_FUNC__C5_RESET(h) HPDI32_IRQ_CALLBACK_FUNC__SET((h),HPDI32_WHICH_IRQ_C5_,HPDI32_IRQ_CALLBACK_FUNC_DEFAULT) |
| |
| #define | HPDI32_IRQ_CALLBACK_FUNC__C6_GET(h, g) HPDI32_IRQ_CALLBACK_FUNC__GET((h),HPDI32_WHICH_IRQ_C6_,(g)) |
| |
| #define | HPDI32_IRQ_CALLBACK_FUNC__C6_SET(h, s) HPDI32_IRQ_CALLBACK_FUNC__SET((h),HPDI32_WHICH_IRQ_C6_,(s)) |
| |
| #define | HPDI32_IRQ_CALLBACK_FUNC__C6_RESET(h) HPDI32_IRQ_CALLBACK_FUNC__SET((h),HPDI32_WHICH_IRQ_C6_,HPDI32_IRQ_CALLBACK_FUNC_DEFAULT) |
| |
| #define | HPDI32_IRQ_CALLBACK_FUNC__TX_E_GET(h, g) HPDI32_IRQ_CALLBACK_FUNC__GET((h),HPDI32_WHICH_IRQ_TX_E,(g)) |
| |
| #define | HPDI32_IRQ_CALLBACK_FUNC__TX_E_SET(h, s) HPDI32_IRQ_CALLBACK_FUNC__SET((h),HPDI32_WHICH_IRQ_TX_E,(s)) |
| |
| #define | HPDI32_IRQ_CALLBACK_FUNC__TX_E_RESET(h) HPDI32_IRQ_CALLBACK_FUNC__SET((h),HPDI32_WHICH_IRQ_TX_E,HPDI32_IRQ_CALLBACK_FUNC_DEFAULT) |
| |
| #define | HPDI32_IRQ_CALLBACK_FUNC__TX_AE_GET(h, g) HPDI32_IRQ_CALLBACK_FUNC__GET((h),HPDI32_WHICH_IRQ_TX_AE,(g)) |
| |
| #define | HPDI32_IRQ_CALLBACK_FUNC__TX_AE_SET(h, s) HPDI32_IRQ_CALLBACK_FUNC__SET((h),HPDI32_WHICH_IRQ_TX_AE,(s)) |
| |
| #define | HPDI32_IRQ_CALLBACK_FUNC__TX_AE_RESET(h) HPDI32_IRQ_CALLBACK_FUNC__SET((h),HPDI32_WHICH_IRQ_TX_AE,HPDI32_IRQ_CALLBACK_FUNC_DEFAULT) |
| |
| #define | HPDI32_IRQ_CALLBACK_FUNC__TX_AF_GET(h, g) HPDI32_IRQ_CALLBACK_FUNC__GET((h),HPDI32_WHICH_IRQ_TX_AF,(g)) |
| |
| #define | HPDI32_IRQ_CALLBACK_FUNC__TX_AF_SET(h, s) HPDI32_IRQ_CALLBACK_FUNC__SET((h),HPDI32_WHICH_IRQ_TX_AF,(s)) |
| |
| #define | HPDI32_IRQ_CALLBACK_FUNC__TX_AF_RESET(h) HPDI32_IRQ_CALLBACK_FUNC__SET((h),HPDI32_WHICH_IRQ_TX_AF,HPDI32_IRQ_CALLBACK_FUNC_DEFAULT) |
| |
| #define | HPDI32_IRQ_CALLBACK_FUNC__TX_F_GET(h, g) HPDI32_IRQ_CALLBACK_FUNC__GET((h),HPDI32_WHICH_IRQ_TX_F,(g)) |
| |
| #define | HPDI32_IRQ_CALLBACK_FUNC__TX_F_SET(h, s) HPDI32_IRQ_CALLBACK_FUNC__SET((h),HPDI32_WHICH_IRQ_TX_F,(s)) |
| |
| #define | HPDI32_IRQ_CALLBACK_FUNC__TX_F_RESET(h) HPDI32_IRQ_CALLBACK_FUNC__SET((h),HPDI32_WHICH_IRQ_TX_F,HPDI32_IRQ_CALLBACK_FUNC_DEFAULT) |
| |
| #define | HPDI32_IRQ_CALLBACK_FUNC__RX_E_GET(h, g) HPDI32_IRQ_CALLBACK_FUNC__GET((h),HPDI32_WHICH_IRQ_RX_E,(g)) |
| |
| #define | HPDI32_IRQ_CALLBACK_FUNC__RX_E_SET(h, s) HPDI32_IRQ_CALLBACK_FUNC__SET((h),HPDI32_WHICH_IRQ_RX_E,(s)) |
| |
| #define | HPDI32_IRQ_CALLBACK_FUNC__RX_E_RESET(h) HPDI32_IRQ_CALLBACK_FUNC__SET((h),HPDI32_WHICH_IRQ_RX_E,HPDI32_IRQ_CALLBACK_FUNC_DEFAULT) |
| |
| #define | HPDI32_IRQ_CALLBACK_FUNC__RX_AE_GET(h, g) HPDI32_IRQ_CALLBACK_FUNC__GET((h),HPDI32_WHICH_IRQ_RX_AE,(g)) |
| |
| #define | HPDI32_IRQ_CALLBACK_FUNC__RX_AE_SET(h, s) HPDI32_IRQ_CALLBACK_FUNC__SET((h),HPDI32_WHICH_IRQ_RX_AE,(s)) |
| |
| #define | HPDI32_IRQ_CALLBACK_FUNC__RX_AE_RESET(h) HPDI32_IRQ_CALLBACK_FUNC__SET((h),HPDI32_WHICH_IRQ_RX_AE,HPDI32_IRQ_CALLBACK_FUNC_DEFAULT) |
| |
| #define | HPDI32_IRQ_CALLBACK_FUNC__RX_AF_GET(h, g) HPDI32_IRQ_CALLBACK_FUNC__GET((h),HPDI32_WHICH_IRQ_RX_AF,(g)) |
| |
| #define | HPDI32_IRQ_CALLBACK_FUNC__RX_AF_SET(h, s) HPDI32_IRQ_CALLBACK_FUNC__SET((h),HPDI32_WHICH_IRQ_RX_AF,(s)) |
| |
| #define | HPDI32_IRQ_CALLBACK_FUNC__RX_AF_RESET(h) HPDI32_IRQ_CALLBACK_FUNC__SET((h),HPDI32_WHICH_IRQ_RX_AF,HPDI32_IRQ_CALLBACK_FUNC_DEFAULT) |
| |
| #define | HPDI32_IRQ_CALLBACK_FUNC__RX_F_GET(h, g) HPDI32_IRQ_CALLBACK_FUNC__GET((h),HPDI32_WHICH_IRQ_RX_F,(g)) |
| |
| #define | HPDI32_IRQ_CALLBACK_FUNC__RX_F_SET(h, s) HPDI32_IRQ_CALLBACK_FUNC__SET((h),HPDI32_WHICH_IRQ_RX_F,(s)) |
| |
| #define | HPDI32_IRQ_CALLBACK_FUNC__RX_F_RESET(h) HPDI32_IRQ_CALLBACK_FUNC__SET((h),HPDI32_WHICH_IRQ_RX_F,HPDI32_IRQ_CALLBACK_FUNC_DEFAULT) |
| |
| #define | HPDI32_IRQ_CALLBACK_FUNC__FVB_GET(h, g) HPDI32_IRQ_CALLBACK_FUNC__C0A_GET((h),(g)) |
| |
| #define | HPDI32_IRQ_CALLBACK_FUNC__FVB_SET(h, s) HPDI32_IRQ_CALLBACK_FUNC__C0A_SET((h),(s)) |
| |
| #define | HPDI32_IRQ_CALLBACK_FUNC__FVB_RESET(h) HPDI32_IRQ_CALLBACK_FUNC__C0A_SET((h),HPDI32_IRQ_CALLBACK_FUNC_DEFAULT) |
| |
| #define | HPDI32_IRQ_CALLBACK_FUNC__FVE_GET(h, g) HPDI32_IRQ_CALLBACK_FUNC__C0I_GET((h),(g)) |
| |
| #define | HPDI32_IRQ_CALLBACK_FUNC__FVE_SET(h, s) HPDI32_IRQ_CALLBACK_FUNC__C0I_SET((h),(s)) |
| |
| #define | HPDI32_IRQ_CALLBACK_FUNC__FVE_RESET(h) HPDI32_IRQ_CALLBACK_FUNC__C0I_SET((h),HPDI32_IRQ_CALLBACK_FUNC_DEFAULT) |
| |
| #define | HPDI32_IRQ_CALLBACK_FUNC__LV_GET(h, g) HPDI32_IRQ_CALLBACK_FUNC__C1_GET((h),(g)) |
| |
| #define | HPDI32_IRQ_CALLBACK_FUNC__LV_SET(h, s) HPDI32_IRQ_CALLBACK_FUNC__C1_SET((h),(s)) |
| |
| #define | HPDI32_IRQ_CALLBACK_FUNC__LV_RESET(h) HPDI32_IRQ_CALLBACK_FUNC__C1_SET((h),HPDI32_IRQ_CALLBACK_FUNC_DEFAULT) |
| |
| #define | HPDI32_IRQ_CALLBACK_FUNC__SV_GET(h, g) HPDI32_IRQ_CALLBACK_FUNC__C2_GET((h),(g)) |
| |
| #define | HPDI32_IRQ_CALLBACK_FUNC__SV_SET(h, s) HPDI32_IRQ_CALLBACK_FUNC__C2_SET((h),(s)) |
| |
| #define | HPDI32_IRQ_CALLBACK_FUNC__SV_RESET(h) HPDI32_IRQ_CALLBACK_FUNC__C2_SET((h),HPDI32_IRQ_CALLBACK_FUNC_DEFAULT) |
| |
| #define | HPDI32_IRQ_CALLBACK_FUNC__RR_GET(h, g) HPDI32_IRQ_CALLBACK_FUNC__C3_GET((h),(g)) |
| |
| #define | HPDI32_IRQ_CALLBACK_FUNC__RR_SET(h, s) HPDI32_IRQ_CALLBACK_FUNC__C3_SET((h),(s)) |
| |
| #define | HPDI32_IRQ_CALLBACK_FUNC__RR_RESET(h) HPDI32_IRQ_CALLBACK_FUNC__C3_SET((h),HPDI32_IRQ_CALLBACK_FUNC_DEFAULT) |
| |
| #define | HPDI32_IRQ_CALLBACK_FUNC__TR_GET(h, g) HPDI32_IRQ_CALLBACK_FUNC__C4_GET((h),(g)) |
| |
| #define | HPDI32_IRQ_CALLBACK_FUNC__TR_SET(h, s) HPDI32_IRQ_CALLBACK_FUNC__C4_SET((h),(s)) |
| |
| #define | HPDI32_IRQ_CALLBACK_FUNC__TR_RESET(h) HPDI32_IRQ_CALLBACK_FUNC__C4_SET((h),HPDI32_IRQ_CALLBACK_FUNC_DEFAULT) |
| |
| #define | HPDI32_IRQ_CALLBACK_FUNC__TE_GET(h, g) HPDI32_IRQ_CALLBACK_FUNC__C5_GET((h),(g)) |
| |
| #define | HPDI32_IRQ_CALLBACK_FUNC__TE_SET(h, s) HPDI32_IRQ_CALLBACK_FUNC__C5_SET((h),(s)) |
| |
| #define | HPDI32_IRQ_CALLBACK_FUNC__TE_RESET(h) HPDI32_IRQ_CALLBACK_FUNC__C5_SET((h),HPDI32_IRQ_CALLBACK_FUNC_DEFAULT) |
| |
| #define | HPDI32_IRQ_CALLBACK_FUNC__RE_GET(h, g) HPDI32_IRQ_CALLBACK_FUNC__C6_GET((h),(g)) |
| |
| #define | HPDI32_IRQ_CALLBACK_FUNC__RE_SET(h, s) HPDI32_IRQ_CALLBACK_FUNC__C6_SET((h),(s)) |
| |
| #define | HPDI32_IRQ_CALLBACK_FUNC__RE_RESET(h) HPDI32_IRQ_CALLBACK_FUNC__C6_SET((h),HPDI32_IRQ_CALLBACK_FUNC_DEFAULT) |
| |
| #define | HPDI32_IRQ_CALLBACK_FUNC__GPIO_0_GET(h, g) HPDI32_IRQ_CALLBACK_FUNC__C1_GET((h),(g)) |
| |
| #define | HPDI32_IRQ_CALLBACK_FUNC__GPIO_0_SET(h, s) HPDI32_IRQ_CALLBACK_FUNC__C1_SET((h),(s)) |
| |
| #define | HPDI32_IRQ_CALLBACK_FUNC__GPIO_0_RESET(h) HPDI32_IRQ_CALLBACK_FUNC__C1_SET((h),HPDI32_IRQ_CALLBACK_FUNC_DEFAULT) |
| |
| #define | HPDI32_IRQ_CALLBACK_FUNC__GPIO_1_GET(h, g) HPDI32_IRQ_CALLBACK_FUNC__C2_GET((h),(g)) |
| |
| #define | HPDI32_IRQ_CALLBACK_FUNC__GPIO_1_SET(h, s) HPDI32_IRQ_CALLBACK_FUNC__C2_SET((h),(s)) |
| |
| #define | HPDI32_IRQ_CALLBACK_FUNC__GPIO_1_RESET(h) HPDI32_IRQ_CALLBACK_FUNC__C2_SET((h),HPDI32_IRQ_CALLBACK_FUNC_DEFAULT) |
| |
| #define | HPDI32_IRQ_CALLBACK_FUNC__GPIO_2_GET(h, g) HPDI32_IRQ_CALLBACK_FUNC__C3_GET((h),(g)) |
| |
| #define | HPDI32_IRQ_CALLBACK_FUNC__GPIO_2_SET(h, s) HPDI32_IRQ_CALLBACK_FUNC__C3_SET((h),(s)) |
| |
| #define | HPDI32_IRQ_CALLBACK_FUNC__GPIO_2_RESET(h) HPDI32_IRQ_CALLBACK_FUNC__C3_SET((h),HPDI32_IRQ_CALLBACK_FUNC_DEFAULT) |
| |
| #define | HPDI32_IRQ_CALLBACK_FUNC__GPIO_3_GET(h, g) HPDI32_IRQ_CALLBACK_FUNC__C4_GET((h),(g)) |
| |
| #define | HPDI32_IRQ_CALLBACK_FUNC__GPIO_3_SET(h, s) HPDI32_IRQ_CALLBACK_FUNC__C4_SET((h),(s)) |
| |
| #define | HPDI32_IRQ_CALLBACK_FUNC__GPIO_3_RESET(h) HPDI32_IRQ_CALLBACK_FUNC__C4_SET((h),HPDI32_IRQ_CALLBACK_FUNC_DEFAULT) |
| |
| #define | HPDI32_IRQ_CALLBACK_FUNC__GPIO_4_GET(h, g) HPDI32_IRQ_CALLBACK_FUNC__C5_GET((h),(g)) |
| |
| #define | HPDI32_IRQ_CALLBACK_FUNC__GPIO_4_SET(h, s) HPDI32_IRQ_CALLBACK_FUNC__C5_SET((h),(s)) |
| |
| #define | HPDI32_IRQ_CALLBACK_FUNC__GPIO_4_RESET(h) HPDI32_IRQ_CALLBACK_FUNC__C5_SET((h),HPDI32_IRQ_CALLBACK_FUNC_DEFAULT) |
| |
| #define | HPDI32_IRQ_CALLBACK_FUNC__GPIO_5_GET(h, g) HPDI32_IRQ_CALLBACK_FUNC__C6_GET((h),(g)) |
| |
| #define | HPDI32_IRQ_CALLBACK_FUNC__GPIO_5_SET(h, s) HPDI32_IRQ_CALLBACK_FUNC__C6_SET((h),(s)) |
| |
| #define | HPDI32_IRQ_CALLBACK_FUNC__GPIO_5_RESET(h) HPDI32_IRQ_CALLBACK_FUNC__C6_SET((h),HPDI32_IRQ_CALLBACK_FUNC_DEFAULT) |
| |
| #define | HPDI32_IRQ_CALLBACK_FUNC__GPIO_6H_GET(h, g) HPDI32_IRQ_CALLBACK_FUNC__C0A_GET((h),(g)) |
| |
| #define | HPDI32_IRQ_CALLBACK_FUNC__GPIO_6H_SET(h, s) HPDI32_IRQ_CALLBACK_FUNC__C0A_SET((h),(s)) |
| |
| #define | HPDI32_IRQ_CALLBACK_FUNC__GPIO_6H_RESET(h) HPDI32_IRQ_CALLBACK_FUNC__C0A_SET((h),HPDI32_IRQ_CALLBACK_FUNC_DEFAULT) |
| |
| #define | HPDI32_IRQ_CALLBACK_FUNC__GPIO_6L_GET(h, g) HPDI32_IRQ_CALLBACK_FUNC__C0I_GET((h),(g)) |
| |
| #define | HPDI32_IRQ_CALLBACK_FUNC__GPIO_6L_SET(h, s) HPDI32_IRQ_CALLBACK_FUNC__C0I_SET((h),(s)) |
| |
| #define | HPDI32_IRQ_CALLBACK_FUNC__GPIO_6L_RESET(h) HPDI32_IRQ_CALLBACK_FUNC__C0I_SET((h),HPDI32_IRQ_CALLBACK_FUNC_DEFAULT) |
| |
| #define | HPDI32_IRQ_ENABLE_NO 0 |
| |
| #define | HPDI32_IRQ_ENABLE_YES 1 |
| |
| #define | HPDI32_IRQ_ENABLE_DEFAULT HPDI32_IRQ_ENABLE_NO |
| |
| #define | HPDI32_IRQ_ENABLE__GET(h, w, g) HPDI32_CONFIG_GET((h),HPDI32_IRQ_ENABLE,(w),(g)) |
| |
| #define | HPDI32_IRQ_ENABLE__SET(h, w, s) HPDI32_CONFIG_SET((h),HPDI32_IRQ_ENABLE,(w),(s)) |
| |
| #define | HPDI32_IRQ_ENABLE__RESET(h, w) HPDI32_CONFIG_SET((h),HPDI32_IRQ_ENABLE,(w),HPDI32_IRQ_ENABLE_DEFAULT) |
| |
| #define | HPDI32_IRQ_ENABLE__C0A_GET(h, g) HPDI32_IRQ_ENABLE__GET((h),HPDI32_WHICH_IRQ_C0A_,(g)) |
| |
| #define | HPDI32_IRQ_ENABLE__C0A_SET(h, s) HPDI32_IRQ_ENABLE__SET((h),HPDI32_WHICH_IRQ_C0A_,(s)) |
| |
| #define | HPDI32_IRQ_ENABLE__C0A_RESET(h) HPDI32_IRQ_ENABLE__SET((h),HPDI32_WHICH_IRQ_C0A_,HPDI32_IRQ_ENABLE_DEFAULT) |
| |
| #define | HPDI32_IRQ_ENABLE__C0A_NO(h) HPDI32_IRQ_ENABLE__C0A_SET((h),HPDI32_IRQ_ENABLE_NO) |
| |
| #define | HPDI32_IRQ_ENABLE__C0A_YES(h) HPDI32_IRQ_ENABLE__C0A_SET((h),HPDI32_IRQ_ENABLE_YES) |
| |
| #define | HPDI32_IRQ_ENABLE__C0I_GET(h, g) HPDI32_IRQ_ENABLE__GET((h),HPDI32_WHICH_IRQ_C0I_,(g)) |
| |
| #define | HPDI32_IRQ_ENABLE__C0I_SET(h, s) HPDI32_IRQ_ENABLE__SET((h),HPDI32_WHICH_IRQ_C0I_,(s)) |
| |
| #define | HPDI32_IRQ_ENABLE__C0I_RESET(h) HPDI32_IRQ_ENABLE__SET((h),HPDI32_WHICH_IRQ_C0I_,HPDI32_IRQ_ENABLE_DEFAULT) |
| |
| #define | HPDI32_IRQ_ENABLE__C0I_NO(h) HPDI32_IRQ_ENABLE__C0I_SET((h),HPDI32_IRQ_ENABLE_NO) |
| |
| #define | HPDI32_IRQ_ENABLE__C0I_YES(h) HPDI32_IRQ_ENABLE__C0I_SET((h),HPDI32_IRQ_ENABLE_YES) |
| |
| #define | HPDI32_IRQ_ENABLE__C1_GET(h, g) HPDI32_IRQ_ENABLE__GET((h),HPDI32_WHICH_IRQ_C1_,(g)) |
| |
| #define | HPDI32_IRQ_ENABLE__C1_SET(h, s) HPDI32_IRQ_ENABLE__SET((h),HPDI32_WHICH_IRQ_C1_,(s)) |
| |
| #define | HPDI32_IRQ_ENABLE__C1_RESET(h) HPDI32_IRQ_ENABLE__SET((h),HPDI32_WHICH_IRQ_C1_,HPDI32_IRQ_ENABLE_DEFAULT) |
| |
| #define | HPDI32_IRQ_ENABLE__C1_NO(h) HPDI32_IRQ_ENABLE__C1_SET((h),HPDI32_IRQ_ENABLE_NO) |
| |
| #define | HPDI32_IRQ_ENABLE__C1_YES(h) HPDI32_IRQ_ENABLE__C1_SET((h),HPDI32_IRQ_ENABLE_YES) |
| |
| #define | HPDI32_IRQ_ENABLE__C2_GET(h, g) HPDI32_IRQ_ENABLE__GET((h),HPDI32_WHICH_IRQ_C2_,(g)) |
| |
| #define | HPDI32_IRQ_ENABLE__C2_SET(h, s) HPDI32_IRQ_ENABLE__SET((h),HPDI32_WHICH_IRQ_C2_,(s)) |
| |
| #define | HPDI32_IRQ_ENABLE__C2_RESET(h) HPDI32_IRQ_ENABLE__SET((h),HPDI32_WHICH_IRQ_C2_,HPDI32_IRQ_ENABLE_DEFAULT) |
| |
| #define | HPDI32_IRQ_ENABLE__C2_NO(h) HPDI32_IRQ_ENABLE__C2_SET((h),HPDI32_IRQ_ENABLE_NO) |
| |
| #define | HPDI32_IRQ_ENABLE__C2_YES(h) HPDI32_IRQ_ENABLE__C2_SET((h),HPDI32_IRQ_ENABLE_YES) |
| |
| #define | HPDI32_IRQ_ENABLE__C3_GET(h, g) HPDI32_IRQ_ENABLE__GET((h),HPDI32_WHICH_IRQ_C3_,(g)) |
| |
| #define | HPDI32_IRQ_ENABLE__C3_SET(h, s) HPDI32_IRQ_ENABLE__SET((h),HPDI32_WHICH_IRQ_C3_,(s)) |
| |
| #define | HPDI32_IRQ_ENABLE__C3_RESET(h) HPDI32_IRQ_ENABLE__SET((h),HPDI32_WHICH_IRQ_C3_,HPDI32_IRQ_ENABLE_DEFAULT) |
| |
| #define | HPDI32_IRQ_ENABLE__C3_NO(h) HPDI32_IRQ_ENABLE__C3_SET((h),HPDI32_IRQ_ENABLE_NO) |
| |
| #define | HPDI32_IRQ_ENABLE__C3_YES(h) HPDI32_IRQ_ENABLE__C3_SET((h),HPDI32_IRQ_ENABLE_YES) |
| |
| #define | HPDI32_IRQ_ENABLE__C4_GET(h, g) HPDI32_IRQ_ENABLE__GET((h),HPDI32_WHICH_IRQ_C4_,(g)) |
| |
| #define | HPDI32_IRQ_ENABLE__C4_SET(h, s) HPDI32_IRQ_ENABLE__SET((h),HPDI32_WHICH_IRQ_C4_,(s)) |
| |
| #define | HPDI32_IRQ_ENABLE__C4_RESET(h) HPDI32_IRQ_ENABLE__SET((h),HPDI32_WHICH_IRQ_C4_,HPDI32_IRQ_ENABLE_DEFAULT) |
| |
| #define | HPDI32_IRQ_ENABLE__C4_NO(h) HPDI32_IRQ_ENABLE__C4_SET((h),HPDI32_IRQ_ENABLE_NO) |
| |
| #define | HPDI32_IRQ_ENABLE__C4_YES(h) HPDI32_IRQ_ENABLE__C4_SET((h),HPDI32_IRQ_ENABLE_YES) |
| |
| #define | HPDI32_IRQ_ENABLE__C5_GET(h, g) HPDI32_IRQ_ENABLE__GET((h),HPDI32_WHICH_IRQ_C5_,(g)) |
| |
| #define | HPDI32_IRQ_ENABLE__C5_SET(h, s) HPDI32_IRQ_ENABLE__SET((h),HPDI32_WHICH_IRQ_C5_,(s)) |
| |
| #define | HPDI32_IRQ_ENABLE__C5_RESET(h) HPDI32_IRQ_ENABLE__SET((h),HPDI32_WHICH_IRQ_C5_,HPDI32_IRQ_ENABLE_DEFAULT) |
| |
| #define | HPDI32_IRQ_ENABLE__C5_NO(h) HPDI32_IRQ_ENABLE__C5_SET((h),HPDI32_IRQ_ENABLE_NO) |
| |
| #define | HPDI32_IRQ_ENABLE__C5_YES(h) HPDI32_IRQ_ENABLE__C5_SET((h),HPDI32_IRQ_ENABLE_YES) |
| |
| #define | HPDI32_IRQ_ENABLE__C6_GET(h, g) HPDI32_IRQ_ENABLE__GET((h),HPDI32_WHICH_IRQ_C6_,(g)) |
| |
| #define | HPDI32_IRQ_ENABLE__C6_SET(h, s) HPDI32_IRQ_ENABLE__SET((h),HPDI32_WHICH_IRQ_C6_,(s)) |
| |
| #define | HPDI32_IRQ_ENABLE__C6_RESET(h) HPDI32_IRQ_ENABLE__SET((h),HPDI32_WHICH_IRQ_C6_,HPDI32_IRQ_ENABLE_DEFAULT) |
| |
| #define | HPDI32_IRQ_ENABLE__C6_NO(h) HPDI32_IRQ_ENABLE__C6_SET((h),HPDI32_IRQ_ENABLE_NO) |
| |
| #define | HPDI32_IRQ_ENABLE__C6_YES(h) HPDI32_IRQ_ENABLE__C6_SET((h),HPDI32_IRQ_ENABLE_YES) |
| |
| #define | HPDI32_IRQ_ENABLE__TX_E_GET(h, g) HPDI32_IRQ_ENABLE__GET((h),HPDI32_WHICH_IRQ_TX_E,(g)) |
| |
| #define | HPDI32_IRQ_ENABLE__TX_E_SET(h, s) HPDI32_IRQ_ENABLE__SET((h),HPDI32_WHICH_IRQ_TX_E,(s)) |
| |
| #define | HPDI32_IRQ_ENABLE__TX_E_RESET(h) HPDI32_IRQ_ENABLE__SET((h),HPDI32_WHICH_IRQ_TX_E,HPDI32_IRQ_ENABLE_DEFAULT) |
| |
| #define | HPDI32_IRQ_ENABLE__TX_E_NO(h) HPDI32_IRQ_ENABLE__TX_E_SET((h),HPDI32_IRQ_ENABLE_NO) |
| |
| #define | HPDI32_IRQ_ENABLE__TX_E_YES(h) HPDI32_IRQ_ENABLE__TX_E_SET((h),HPDI32_IRQ_ENABLE_YES) |
| |
| #define | HPDI32_IRQ_ENABLE__TX_AE_GET(h, g) HPDI32_IRQ_ENABLE__GET((h),HPDI32_WHICH_IRQ_TX_AE,(g)) |
| |
| #define | HPDI32_IRQ_ENABLE__TX_AE_SET(h, s) HPDI32_IRQ_ENABLE__SET((h),HPDI32_WHICH_IRQ_TX_AE,(s)) |
| |
| #define | HPDI32_IRQ_ENABLE__TX_AE_RESET(h) HPDI32_IRQ_ENABLE__SET((h),HPDI32_WHICH_IRQ_TX_AE,HPDI32_IRQ_ENABLE_DEFAULT) |
| |
| #define | HPDI32_IRQ_ENABLE__TX_AE_NO(h) HPDI32_IRQ_ENABLE__TX_AE_SET((h),HPDI32_IRQ_ENABLE_NO) |
| |
| #define | HPDI32_IRQ_ENABLE__TX_AE_YES(h) HPDI32_IRQ_ENABLE__TX_AE_SET((h),HPDI32_IRQ_ENABLE_YES) |
| |
| #define | HPDI32_IRQ_ENABLE__RX_AF_GET(h, g) HPDI32_IRQ_ENABLE__GET((h),HPDI32_WHICH_IRQ_RX_AF,(g)) |
| |
| #define | HPDI32_IRQ_ENABLE__RX_AF_SET(h, s) HPDI32_IRQ_ENABLE__SET((h),HPDI32_WHICH_IRQ_RX_AF,(s)) |
| |
| #define | HPDI32_IRQ_ENABLE__RX_AF_RESET(h) HPDI32_IRQ_ENABLE__SET((h),HPDI32_WHICH_IRQ_RX_AF,HPDI32_IRQ_ENABLE_DEFAULT) |
| |
| #define | HPDI32_IRQ_ENABLE__RX_AF_NO(h) HPDI32_IRQ_ENABLE__RX_AF_SET((h),HPDI32_IRQ_ENABLE_NO) |
| |
| #define | HPDI32_IRQ_ENABLE__RX_AF_YES(h) HPDI32_IRQ_ENABLE__RX_AF_SET((h),HPDI32_IRQ_ENABLE_YES) |
| |
| #define | HPDI32_IRQ_ENABLE__RX_F_GET(h, g) HPDI32_IRQ_ENABLE__GET((h),HPDI32_WHICH_IRQ_RX_F,(g)) |
| |
| #define | HPDI32_IRQ_ENABLE__RX_F_SET(h, s) HPDI32_IRQ_ENABLE__SET((h),HPDI32_WHICH_IRQ_RX_F,(s)) |
| |
| #define | HPDI32_IRQ_ENABLE__RX_F_RESET(h) HPDI32_IRQ_ENABLE__SET((h),HPDI32_WHICH_IRQ_RX_F,HPDI32_IRQ_ENABLE_DEFAULT) |
| |
| #define | HPDI32_IRQ_ENABLE__RX_F_NO(h) HPDI32_IRQ_ENABLE__RX_F_SET((h),HPDI32_IRQ_ENABLE_NO) |
| |
| #define | HPDI32_IRQ_ENABLE__RX_F_YES(h) HPDI32_IRQ_ENABLE__RX_F_SET((h),HPDI32_IRQ_ENABLE_YES) |
| |
| #define | HPDI32_IRQ_ENABLE__FVB_GET(h, g) HPDI32_IRQ_ENABLE__C0A_GET((h),(g)) |
| |
| #define | HPDI32_IRQ_ENABLE__FVB_SET(h, s) HPDI32_IRQ_ENABLE__C0A_SET((h),(s)) |
| |
| #define | HPDI32_IRQ_ENABLE__FVB_RESET(h) HPDI32_IRQ_ENABLE__C0A_SET((h),HPDI32_IRQ_ENABLE_DEFAULT) |
| |
| #define | HPDI32_IRQ_ENABLE__FVB_NO(h) HPDI32_IRQ_ENABLE__C0A_NO((h)) |
| |
| #define | HPDI32_IRQ_ENABLE__FVB_YES(h) HPDI32_IRQ_ENABLE__C0A_YES((h)) |
| |
| #define | HPDI32_IRQ_ENABLE__FVE_GET(h, g) HPDI32_IRQ_ENABLE__C0I_GET((h),(g)) |
| |
| #define | HPDI32_IRQ_ENABLE__FVE_SET(h, s) HPDI32_IRQ_ENABLE__C0I_SET((h),(s)) |
| |
| #define | HPDI32_IRQ_ENABLE__FVE_RESET(h) HPDI32_IRQ_ENABLE__C0I_SET((h),HPDI32_IRQ_ENABLE_DEFAULT) |
| |
| #define | HPDI32_IRQ_ENABLE__FVE_NO(h) HPDI32_IRQ_ENABLE__C0I_NO((h)) |
| |
| #define | HPDI32_IRQ_ENABLE__FVE_YES(h) HPDI32_IRQ_ENABLE__C0I_YES((h)) |
| |
| #define | HPDI32_IRQ_ENABLE__LV_GET(h, g) HPDI32_IRQ_ENABLE__C1_GET((h),(g)) |
| |
| #define | HPDI32_IRQ_ENABLE__LV_SET(h, s) HPDI32_IRQ_ENABLE__C1_SET((h),(s)) |
| |
| #define | HPDI32_IRQ_ENABLE__LV_RESET(h) HPDI32_IRQ_ENABLE__C1_SET((h),HPDI32_IRQ_ENABLE_DEFAULT) |
| |
| #define | HPDI32_IRQ_ENABLE__LV_NO(h) HPDI32_IRQ_ENABLE__C1_NO((h)) |
| |
| #define | HPDI32_IRQ_ENABLE__LV_YES(h) HPDI32_IRQ_ENABLE__C1_YES((h)) |
| |
| #define | HPDI32_IRQ_ENABLE__SV_GET(h, g) HPDI32_IRQ_ENABLE__C2_GET((h),(g)) |
| |
| #define | HPDI32_IRQ_ENABLE__SV_SET(h, s) HPDI32_IRQ_ENABLE__C2_SET((h),(s)) |
| |
| #define | HPDI32_IRQ_ENABLE__SV_RESET(h) HPDI32_IRQ_ENABLE__C2_SET((h),HPDI32_IRQ_ENABLE_DEFAULT) |
| |
| #define | HPDI32_IRQ_ENABLE__SV_NO(h) HPDI32_IRQ_ENABLE__C2_NO((h)) |
| |
| #define | HPDI32_IRQ_ENABLE__SV_YES(h) HPDI32_IRQ_ENABLE__C2_YES((h)) |
| |
| #define | HPDI32_IRQ_ENABLE__RR_GET(h, g) HPDI32_IRQ_ENABLE__C3_GET((h),(g)) |
| |
| #define | HPDI32_IRQ_ENABLE__RR_SET(h, s) HPDI32_IRQ_ENABLE__C3_SET((h),(s)) |
| |
| #define | HPDI32_IRQ_ENABLE__RR_RESET(h) HPDI32_IRQ_ENABLE__C3_SET((h),HPDI32_IRQ_ENABLE_DEFAULT) |
| |
| #define | HPDI32_IRQ_ENABLE__RR_NO(h) HPDI32_IRQ_ENABLE__C3_NO((h)) |
| |
| #define | HPDI32_IRQ_ENABLE__RR_YES(h) HPDI32_IRQ_ENABLE__C3_YES((h)) |
| |
| #define | HPDI32_IRQ_ENABLE__TR_GET(h, g) HPDI32_IRQ_ENABLE__C4_GET((h),(g)) |
| |
| #define | HPDI32_IRQ_ENABLE__TR_SET(h, s) HPDI32_IRQ_ENABLE__C4_SET((h),(s)) |
| |
| #define | HPDI32_IRQ_ENABLE__TR_RESET(h) HPDI32_IRQ_ENABLE__C4_SET((h),HPDI32_IRQ_ENABLE_DEFAULT) |
| |
| #define | HPDI32_IRQ_ENABLE__TR_NO(h) HPDI32_IRQ_ENABLE__C4_NO((h)) |
| |
| #define | HPDI32_IRQ_ENABLE__TR_YES(h) HPDI32_IRQ_ENABLE__C4_YES((h)) |
| |
| #define | HPDI32_IRQ_ENABLE__TE_GET(h, g) HPDI32_IRQ_ENABLE__C5_GET((h),(g)) |
| |
| #define | HPDI32_IRQ_ENABLE__TE_SET(h, s) HPDI32_IRQ_ENABLE__C5_SET((h),(s)) |
| |
| #define | HPDI32_IRQ_ENABLE__TE_RESET(h) HPDI32_IRQ_ENABLE__C5_SET((h),HPDI32_IRQ_ENABLE_DEFAULT) |
| |
| #define | HPDI32_IRQ_ENABLE__TE_NO(h) HPDI32_IRQ_ENABLE__C5_NO((h)) |
| |
| #define | HPDI32_IRQ_ENABLE__TE_YES(h) HPDI32_IRQ_ENABLE__C5_YES((h)) |
| |
| #define | HPDI32_IRQ_ENABLE__RE_GET(h, g) HPDI32_IRQ_ENABLE__C6_GET((h),(g)) |
| |
| #define | HPDI32_IRQ_ENABLE__RE_SET(h, s) HPDI32_IRQ_ENABLE__C6_SET((h),(s)) |
| |
| #define | HPDI32_IRQ_ENABLE__RE_RESET(h) HPDI32_IRQ_ENABLE__C6_SET((h),HPDI32_IRQ_ENABLE_DEFAULT) |
| |
| #define | HPDI32_IRQ_ENABLE__RE_NO(h) HPDI32_IRQ_ENABLE__C6_NO((h)) |
| |
| #define | HPDI32_IRQ_ENABLE__RE_YES(h) HPDI32_IRQ_ENABLE__C6_YES((h)) |
| |
| #define | HPDI32_IRQ_ENABLE__GPIO_0_GET(h, g) HPDI32_IRQ_ENABLE__C1_GET((h),(g)) |
| |
| #define | HPDI32_IRQ_ENABLE__GPIO_0_SET(h, s) HPDI32_IRQ_ENABLE__C1_SET((h),(s)) |
| |
| #define | HPDI32_IRQ_ENABLE__GPIO_0_RESET(h) HPDI32_IRQ_ENABLE__C1_SET((h),HPDI32_IRQ_ENABLE_DEFAULT) |
| |
| #define | HPDI32_IRQ_ENABLE__GPIO_0_NO(h) HPDI32_IRQ_ENABLE__C1_NO((h)) |
| |
| #define | HPDI32_IRQ_ENABLE__GPIO_0_YES(h) HPDI32_IRQ_ENABLE__C1_YES((h)) |
| |
| #define | HPDI32_IRQ_ENABLE__GPIO_1_GET(h, g) HPDI32_IRQ_ENABLE__C2_GET((h),(g)) |
| |
| #define | HPDI32_IRQ_ENABLE__GPIO_1_SET(h, s) HPDI32_IRQ_ENABLE__C2_SET((h),(s)) |
| |
| #define | HPDI32_IRQ_ENABLE__GPIO_1_RESET(h) HPDI32_IRQ_ENABLE__C2_SET((h),HPDI32_IRQ_ENABLE_DEFAULT) |
| |
| #define | HPDI32_IRQ_ENABLE__GPIO_1_NO(h) HPDI32_IRQ_ENABLE__C2_NO((h)) |
| |
| #define | HPDI32_IRQ_ENABLE__GPIO_1_YES(h) HPDI32_IRQ_ENABLE__C2_YES((h)) |
| |
| #define | HPDI32_IRQ_ENABLE__GPIO_2_GET(h, g) HPDI32_IRQ_ENABLE__C3_GET((h),(g)) |
| |
| #define | HPDI32_IRQ_ENABLE__GPIO_2_SET(h, s) HPDI32_IRQ_ENABLE__C3_SET((h),(s)) |
| |
| #define | HPDI32_IRQ_ENABLE__GPIO_2_RESET(h) HPDI32_IRQ_ENABLE__C3_SET((h),HPDI32_IRQ_ENABLE_DEFAULT) |
| |
| #define | HPDI32_IRQ_ENABLE__GPIO_2_NO(h) HPDI32_IRQ_ENABLE__C3_NO((h)) |
| |
| #define | HPDI32_IRQ_ENABLE__GPIO_2_YES(h) HPDI32_IRQ_ENABLE__C3_YES((h)) |
| |
| #define | HPDI32_IRQ_ENABLE__GPIO_3_GET(h, g) HPDI32_IRQ_ENABLE__C4_GET((h),(g)) |
| |
| #define | HPDI32_IRQ_ENABLE__GPIO_3_SET(h, s) HPDI32_IRQ_ENABLE__C4_SET((h),(s)) |
| |
| #define | HPDI32_IRQ_ENABLE__GPIO_3_RESET(h) HPDI32_IRQ_ENABLE__C4_SET((h),HPDI32_IRQ_ENABLE_DEFAULT) |
| |
| #define | HPDI32_IRQ_ENABLE__GPIO_3_NO(h) HPDI32_IRQ_ENABLE__C4_NO((h)) |
| |
| #define | HPDI32_IRQ_ENABLE__GPIO_3_YES(h) HPDI32_IRQ_ENABLE__C4_YES((h)) |
| |
| #define | HPDI32_IRQ_ENABLE__GPIO_4_GET(h, g) HPDI32_IRQ_ENABLE__C5_GET((h),(g)) |
| |
| #define | HPDI32_IRQ_ENABLE__GPIO_4_SET(h, s) HPDI32_IRQ_ENABLE__C5_SET((h),(s)) |
| |
| #define | HPDI32_IRQ_ENABLE__GPIO_4_RESET(h) HPDI32_IRQ_ENABLE__C5_SET((h),HPDI32_IRQ_ENABLE_DEFAULT) |
| |
| #define | HPDI32_IRQ_ENABLE__GPIO_4_NO(h) HPDI32_IRQ_ENABLE__C5_NO((h)) |
| |
| #define | HPDI32_IRQ_ENABLE__GPIO_4_YES(h) HPDI32_IRQ_ENABLE__C5_YES((h)) |
| |
| #define | HPDI32_IRQ_ENABLE__GPIO_5_GET(h, g) HPDI32_IRQ_ENABLE__C6_GET((h),(g)) |
| |
| #define | HPDI32_IRQ_ENABLE__GPIO_5_SET(h, s) HPDI32_IRQ_ENABLE__C6_SET((h),(s)) |
| |
| #define | HPDI32_IRQ_ENABLE__GPIO_5_RESET(h) HPDI32_IRQ_ENABLE__C6_SET((h),HPDI32_IRQ_ENABLE_DEFAULT) |
| |
| #define | HPDI32_IRQ_ENABLE__GPIO_5_NO(h) HPDI32_IRQ_ENABLE__C6_NO((h)) |
| |
| #define | HPDI32_IRQ_ENABLE__GPIO_5_YES(h) HPDI32_IRQ_ENABLE__C6_YES((h)) |
| |
| #define | HPDI32_IRQ_ENABLE__GPIO_6H_GET(h, g) HPDI32_IRQ_ENABLE__C0A_GET((h),(g)) |
| |
| #define | HPDI32_IRQ_ENABLE__GPIO_6H_SET(h, s) HPDI32_IRQ_ENABLE__C0A_SET((h),(s)) |
| |
| #define | HPDI32_IRQ_ENABLE__GPIO_6H_RESET(h) HPDI32_IRQ_ENABLE__C0A_SET((h),HPDI32_IRQ_ENABLE_DEFAULT) |
| |
| #define | HPDI32_IRQ_ENABLE__GPIO_6H_NO(h) HPDI32_IRQ_ENABLE__C0A_NO((h)) |
| |
| #define | HPDI32_IRQ_ENABLE__GPIO_6H_YES(h) HPDI32_IRQ_ENABLE__C0A_YES((h)) |
| |
| #define | HPDI32_IRQ_ENABLE__GPIO_6L_GET(h, g) HPDI32_IRQ_ENABLE__C0I_GET((h),(g)) |
| |
| #define | HPDI32_IRQ_ENABLE__GPIO_6L_SET(h, s) HPDI32_IRQ_ENABLE__C0I_SET((h),(s)) |
| |
| #define | HPDI32_IRQ_ENABLE__GPIO_6L_RESET(h) HPDI32_IRQ_ENABLE__C0I_SET((h),HPDI32_IRQ_ENABLE_DEFAULT) |
| |
| #define | HPDI32_IRQ_ENABLE__GPIO_6L_NO(h) HPDI32_IRQ_ENABLE__C0I_NO((h)) |
| |
| #define | HPDI32_IRQ_ENABLE__GPIO_6L_YES(h) HPDI32_IRQ_ENABLE__C0I_YES((h)) |
| |
| #define | HPDI32_IRQ_STATE_INACTIVE 0 |
| |
| #define | HPDI32_IRQ_STATE_ACTIVE 1 |
| |
| #define | HPDI32_IRQ_STATE__GET(h, w, g) HPDI32_CONFIG_GET((h),HPDI32_IRQ_STATE,(w),(g)) |
| |
| #define | HPDI32_IRQ_STATE__C0A_GET(h, g) HPDI32_IRQ_STATE__GET((h),HPDI32_WHICH_IRQ_C0A_,(g)) |
| |
| #define | HPDI32_IRQ_STATE__C0I_GET(h, g) HPDI32_IRQ_STATE__GET((h),HPDI32_WHICH_IRQ_C0I_,(g)) |
| |
| #define | HPDI32_IRQ_STATE__C1_GET(h, g) HPDI32_IRQ_STATE__GET((h),HPDI32_WHICH_IRQ_C1_,(g)) |
| |
| #define | HPDI32_IRQ_STATE__C2_GET(h, g) HPDI32_IRQ_STATE__GET((h),HPDI32_WHICH_IRQ_C2_,(g)) |
| |
| #define | HPDI32_IRQ_STATE__C3_GET(h, g) HPDI32_IRQ_STATE__GET((h),HPDI32_WHICH_IRQ_C3_,(g)) |
| |
| #define | HPDI32_IRQ_STATE__C4_GET(h, g) HPDI32_IRQ_STATE__GET((h),HPDI32_WHICH_IRQ_C4_,(g)) |
| |
| #define | HPDI32_IRQ_STATE__C5_GET(h, g) HPDI32_IRQ_STATE__GET((h),HPDI32_WHICH_IRQ_C5_,(g)) |
| |
| #define | HPDI32_IRQ_STATE__C6_GET(h, g) HPDI32_IRQ_STATE__GET((h),HPDI32_WHICH_IRQ_C6_,(g)) |
| |
| #define | HPDI32_IRQ_STATE__TX_E_GET(h, g) HPDI32_IRQ_STATE__GET((h),HPDI32_WHICH_IRQ_TX_E,(g)) |
| |
| #define | HPDI32_IRQ_STATE__TX_AE_GET(h, g) HPDI32_IRQ_STATE__GET((h),HPDI32_WHICH_IRQ_TX_AE,(g)) |
| |
| #define | HPDI32_IRQ_STATE__TX_AF_GET(h, g) HPDI32_IRQ_STATE__GET((h),HPDI32_WHICH_IRQ_TX_AF,(g)) |
| |
| #define | HPDI32_IRQ_STATE__TX_F_GET(h, g) HPDI32_IRQ_STATE__GET((h),HPDI32_WHICH_IRQ_TX_F,(g)) |
| |
| #define | HPDI32_IRQ_STATE__RX_E_GET(h, g) HPDI32_IRQ_STATE__GET((h),HPDI32_WHICH_IRQ_RX_E,(g)) |
| |
| #define | HPDI32_IRQ_STATE__RX_AE_GET(h, g) HPDI32_IRQ_STATE__GET((h),HPDI32_WHICH_IRQ_RX_AE,(g)) |
| |
| #define | HPDI32_IRQ_STATE__RX_AF_GET(h, g) HPDI32_IRQ_STATE__GET((h),HPDI32_WHICH_IRQ_RX_AF,(g)) |
| |
| #define | HPDI32_IRQ_STATE__RX_F_GET(h, g) HPDI32_IRQ_STATE__GET((h),HPDI32_WHICH_IRQ_RX_F,(g)) |
| |
| #define | HPDI32_IRQ_STATE__FVB_GET(h, g) HPDI32_IRQ_STATE__C0A_GET((h),(g)) |
| |
| #define | HPDI32_IRQ_STATE__FVE_GET(h, g) HPDI32_IRQ_STATE__C0I_GET((h),(g)) |
| |
| #define | HPDI32_IRQ_STATE__LV_GET(h, g) HPDI32_IRQ_STATE__C1_GET((h),(g)) |
| |
| #define | HPDI32_IRQ_STATE__SV_GET(h, g) HPDI32_IRQ_STATE__C2_GET((h),(g)) |
| |
| #define | HPDI32_IRQ_STATE__RR_GET(h, g) HPDI32_IRQ_STATE__C3_GET((h),(g)) |
| |
| #define | HPDI32_IRQ_STATE__TR_GET(h, g) HPDI32_IRQ_STATE__C4_GET((h),(g)) |
| |
| #define | HPDI32_IRQ_STATE__TE_GET(h, g) HPDI32_IRQ_STATE__C5_GET((h),(g)) |
| |
| #define | HPDI32_IRQ_STATE__RE_GET(h, g) HPDI32_IRQ_STATE__C6_GET((h),(g)) |
| |
| #define | HPDI32_IRQ_STATE__GPIO_0_GET(h, g) HPDI32_IRQ_STATE__C1_GET((h),(g)) |
| |
| #define | HPDI32_IRQ_STATE__GPIO_1_GET(h, g) HPDI32_IRQ_STATE__C2_GET((h),(g)) |
| |
| #define | HPDI32_IRQ_STATE__GPIO_2_GET(h, g) HPDI32_IRQ_STATE__C3_GET((h),(g)) |
| |
| #define | HPDI32_IRQ_STATE__GPIO_3_GET(h, g) HPDI32_IRQ_STATE__C4_GET((h),(g)) |
| |
| #define | HPDI32_IRQ_STATE__GPIO_4_GET(h, g) HPDI32_IRQ_STATE__C5_GET((h),(g)) |
| |
| #define | HPDI32_IRQ_STATE__GPIO_5_GET(h, g) HPDI32_IRQ_STATE__C6_GET((h),(g)) |
| |
| #define | HPDI32_IRQ_STATE__GPIO_6H_GET(h, g) HPDI32_IRQ_STATE__C0A_GET((h),(g)) |
| |
| #define | HPDI32_IRQ_STATE__GPIO_6L_GET(h, g) HPDI32_IRQ_STATE__C0I_GET((h),(g)) |
| |
| #define | HPDI32_IRQ_TRIGGER_CONFIG_EDGE_LOW 0 |
| |
| #define | HPDI32_IRQ_TRIGGER_CONFIG_EDGE_HI 1 |
| |
| #define | HPDI32_IRQ_TRIGGER_CONFIG_LEVEL_LOW 2 |
| |
| #define | HPDI32_IRQ_TRIGGER_CONFIG_LEVEL_HI 3 |
| |
| #define | HPDI32_IRQ_TRIGGER_CONFIG_DEFAULT HPDI32_IRQ_TRIGGER_CONFIG_EDGE_HI |
| |
| #define | HPDI32_IRQ_TRIGGER_CONFIG__GET(h, w, g) HPDI32_CONFIG_GET((h),HPDI32_IRQ_TRIGGER_CONFIG,(w),(g)) |
| |
| #define | HPDI32_IRQ_TRIGGER_CONFIG__SET(h, w, s) HPDI32_CONFIG_SET((h),HPDI32_IRQ_TRIGGER_CONFIG,(w),(s)) |
| |
| #define | HPDI32_IRQ_TRIGGER_CONFIG__RESET(h, w) HPDI32_CONFIG_SET((h),HPDI32_IRQ_TRIGGER_CONFIG,(w),HPDI32_IRQ_TRIGGER_CONFIG_DEFAULT) |
| |
| #define | HPDI32_IRQ_TRIGGER_CONFIG__C0A_GET(h, g) HPDI32_IRQ_TRIGGER_CONFIG__GET((h),HPDI32_WHICH_IRQ_C0A_,(g)) |
| |
| #define | HPDI32_IRQ_TRIGGER_CONFIG__C0A_SET(h, s) HPDI32_IRQ_TRIGGER_CONFIG__SET((h),HPDI32_WHICH_IRQ_C0A_,(s)) |
| |
| #define | HPDI32_IRQ_TRIGGER_CONFIG__C0A_RESET(h) HPDI32_IRQ_TRIGGER_CONFIG__SET((h),HPDI32_WHICH_IRQ_C0A_,HPDI32_IRQ_TRIGGER_CONFIG_DEFAULT) |
| |
| #define | HPDI32_IRQ_TRIGGER_CONFIG__C0A_EDGE_HI(h) HPDI32_IRQ_TRIGGER_CONFIG__C0A_SET((h),HPDI32_IRQ_TRIGGER_CONFIG_EDGE_HI) |
| |
| #define | HPDI32_IRQ_TRIGGER_CONFIG__C0A_EDGE_LOW(h) HPDI32_IRQ_TRIGGER_CONFIG__C0A_SET((h),HPDI32_IRQ_TRIGGER_CONFIG_EDGE_LOW) |
| |
| #define | HPDI32_IRQ_TRIGGER_CONFIG__C0A_LEV_HI(h) HPDI32_IRQ_TRIGGER_CONFIG__C0A_SET((h),HPDI32_IRQ_TRIGGER_CONFIG_LEVEL_HI) |
| |
| #define | HPDI32_IRQ_TRIGGER_CONFIG__C0A_LEV_LOW(h) HPDI32_IRQ_TRIGGER_CONFIG__C0A_SET((h),HPDI32_IRQ_TRIGGER_CONFIG_LEVEL_LOW) |
| |
| #define | HPDI32_IRQ_TRIGGER_CONFIG__C0I_GET(h, g) HPDI32_IRQ_TRIGGER_CONFIG__GET((h),HPDI32_WHICH_IRQ_C0I_,(g)) |
| |
| #define | HPDI32_IRQ_TRIGGER_CONFIG__C0I_SET(h, s) HPDI32_IRQ_TRIGGER_CONFIG__SET((h),HPDI32_WHICH_IRQ_C0I_,(s)) |
| |
| #define | HPDI32_IRQ_TRIGGER_CONFIG__C0I_RESET(h) HPDI32_IRQ_TRIGGER_CONFIG__SET((h),HPDI32_WHICH_IRQ_C0I_,HPDI32_IRQ_TRIGGER_CONFIG_DEFAULT) |
| |
| #define | HPDI32_IRQ_TRIGGER_CONFIG__C0I_EDGE_HI(h) HPDI32_IRQ_TRIGGER_CONFIG__C0I_SET((h),HPDI32_IRQ_TRIGGER_CONFIG_EDGE_HI) |
| |
| #define | HPDI32_IRQ_TRIGGER_CONFIG__C0I_EDGE_LOW(h) HPDI32_IRQ_TRIGGER_CONFIG__C0I_SET((h),HPDI32_IRQ_TRIGGER_CONFIG_EDGE_LOW) |
| |
| #define | HPDI32_IRQ_TRIGGER_CONFIG__C0I_LEV_HI(h) HPDI32_IRQ_TRIGGER_CONFIG__C0I_SET((h),HPDI32_IRQ_TRIGGER_CONFIG_LEVEL_HI) |
| |
| #define | HPDI32_IRQ_TRIGGER_CONFIG__C0I_LEV_LOW(h) HPDI32_IRQ_TRIGGER_CONFIG__C0I_SET((h),HPDI32_IRQ_TRIGGER_CONFIG_LEVEL_LOW) |
| |
| #define | HPDI32_IRQ_TRIGGER_CONFIG__C1_GET(h, g) HPDI32_IRQ_TRIGGER_CONFIG__GET((h),HPDI32_WHICH_IRQ_C1_,(g)) |
| |
| #define | HPDI32_IRQ_TRIGGER_CONFIG__C1_SET(h, s) HPDI32_IRQ_TRIGGER_CONFIG__SET((h),HPDI32_WHICH_IRQ_C1_,(s)) |
| |
| #define | HPDI32_IRQ_TRIGGER_CONFIG__C1_RESET(h) HPDI32_IRQ_TRIGGER_CONFIG__SET((h),HPDI32_WHICH_IRQ_C1_,HPDI32_IRQ_TRIGGER_CONFIG_DEFAULT) |
| |
| #define | HPDI32_IRQ_TRIGGER_CONFIG__C1_EDGE_HI(h) HPDI32_IRQ_TRIGGER_CONFIG__C1_SET((h),HPDI32_IRQ_TRIGGER_CONFIG_EDGE_HI) |
| |
| #define | HPDI32_IRQ_TRIGGER_CONFIG__C1_EDGE_LOW(h) HPDI32_IRQ_TRIGGER_CONFIG__C1_SET((h),HPDI32_IRQ_TRIGGER_CONFIG_EDGE_LOW) |
| |
| #define | HPDI32_IRQ_TRIGGER_CONFIG__C1_LEV_HI(h) HPDI32_IRQ_TRIGGER_CONFIG__C1_SET((h),HPDI32_IRQ_TRIGGER_CONFIG_LEVEL_HI) |
| |
| #define | HPDI32_IRQ_TRIGGER_CONFIG__C1_LEV_LOW(h) HPDI32_IRQ_TRIGGER_CONFIG__C1_SET((h),HPDI32_IRQ_TRIGGER_CONFIG_LEVEL_LOW) |
| |
| #define | HPDI32_IRQ_TRIGGER_CONFIG__C2_GET(h, g) HPDI32_IRQ_TRIGGER_CONFIG__GET((h),HPDI32_WHICH_IRQ_C2_,(g)) |
| |
| #define | HPDI32_IRQ_TRIGGER_CONFIG__C2_SET(h, s) HPDI32_IRQ_TRIGGER_CONFIG__SET((h),HPDI32_WHICH_IRQ_C2_,(s)) |
| |
| #define | HPDI32_IRQ_TRIGGER_CONFIG__C2_RESET(h) HPDI32_IRQ_TRIGGER_CONFIG__SET((h),HPDI32_WHICH_IRQ_C2_,HPDI32_IRQ_TRIGGER_CONFIG_DEFAULT) |
| |
| #define | HPDI32_IRQ_TRIGGER_CONFIG__C2_EDGE_HI(h) HPDI32_IRQ_TRIGGER_CONFIG__C2_SET((h),HPDI32_IRQ_TRIGGER_CONFIG_EDGE_HI) |
| |
| #define | HPDI32_IRQ_TRIGGER_CONFIG__C2_EDGE_LOW(h) HPDI32_IRQ_TRIGGER_CONFIG__C2_SET((h),HPDI32_IRQ_TRIGGER_CONFIG_EDGE_LOW) |
| |
| #define | HPDI32_IRQ_TRIGGER_CONFIG__C2_LEV_HI(h) HPDI32_IRQ_TRIGGER_CONFIG__C2_SET((h),HPDI32_IRQ_TRIGGER_CONFIG_LEVEL_HI) |
| |
| #define | HPDI32_IRQ_TRIGGER_CONFIG__C2_LEV_LOW(h) HPDI32_IRQ_TRIGGER_CONFIG__C2_SET((h),HPDI32_IRQ_TRIGGER_CONFIG_LEVEL_LOW) |
| |
| #define | HPDI32_IRQ_TRIGGER_CONFIG__C3_GET(h, g) HPDI32_IRQ_TRIGGER_CONFIG__GET((h),HPDI32_WHICH_IRQ_C3_,(g)) |
| |
| #define | HPDI32_IRQ_TRIGGER_CONFIG__C3_SET(h, s) HPDI32_IRQ_TRIGGER_CONFIG__SET((h),HPDI32_WHICH_IRQ_C3_,(s)) |
| |
| #define | HPDI32_IRQ_TRIGGER_CONFIG__C3_RESET(h) HPDI32_IRQ_TRIGGER_CONFIG__SET((h),HPDI32_WHICH_IRQ_C3_,HPDI32_IRQ_TRIGGER_CONFIG_DEFAULT) |
| |
| #define | HPDI32_IRQ_TRIGGER_CONFIG__C3_EDGE_HI(h) HPDI32_IRQ_TRIGGER_CONFIG__C3_SET((h),HPDI32_IRQ_TRIGGER_CONFIG_EDGE_HI) |
| |
| #define | HPDI32_IRQ_TRIGGER_CONFIG__C3_EDGE_LOW(h) HPDI32_IRQ_TRIGGER_CONFIG__C3_SET((h),HPDI32_IRQ_TRIGGER_CONFIG_EDGE_LOW) |
| |
| #define | HPDI32_IRQ_TRIGGER_CONFIG__C3_LEV_HI(h) HPDI32_IRQ_TRIGGER_CONFIG__C3_SET((h),HPDI32_IRQ_TRIGGER_CONFIG_LEVEL_HI) |
| |
| #define | HPDI32_IRQ_TRIGGER_CONFIG__C3_LEV_LOW(h) HPDI32_IRQ_TRIGGER_CONFIG__C3_SET((h),HPDI32_IRQ_TRIGGER_CONFIG_LEVEL_LOW) |
| |
| #define | HPDI32_IRQ_TRIGGER_CONFIG__C4_GET(h, g) HPDI32_IRQ_TRIGGER_CONFIG__GET((h),HPDI32_WHICH_IRQ_C4_,(g)) |
| |
| #define | HPDI32_IRQ_TRIGGER_CONFIG__C4_SET(h, s) HPDI32_IRQ_TRIGGER_CONFIG__SET((h),HPDI32_WHICH_IRQ_C4_,(s)) |
| |
| #define | HPDI32_IRQ_TRIGGER_CONFIG__C4_RESET(h) HPDI32_IRQ_TRIGGER_CONFIG__SET((h),HPDI32_WHICH_IRQ_C4_,HPDI32_IRQ_TRIGGER_CONFIG_DEFAULT) |
| |
| #define | HPDI32_IRQ_TRIGGER_CONFIG__C4_EDGE_HI(h) HPDI32_IRQ_TRIGGER_CONFIG__C4_SET((h),HPDI32_IRQ_TRIGGER_CONFIG_EDGE_HI) |
| |
| #define | HPDI32_IRQ_TRIGGER_CONFIG__C4_EDGE_LOW(h) HPDI32_IRQ_TRIGGER_CONFIG__C4_SET((h),HPDI32_IRQ_TRIGGER_CONFIG_EDGE_LOW) |
| |
| #define | HPDI32_IRQ_TRIGGER_CONFIG__C4_LEV_HI(h) HPDI32_IRQ_TRIGGER_CONFIG__C4_SET((h),HPDI32_IRQ_TRIGGER_CONFIG_LEVEL_HI) |
| |
| #define | HPDI32_IRQ_TRIGGER_CONFIG__C4_LEV_LOW(h) HPDI32_IRQ_TRIGGER_CONFIG__C4_SET((h),HPDI32_IRQ_TRIGGER_CONFIG_LEVEL_LOW) |
| |
| #define | HPDI32_IRQ_TRIGGER_CONFIG__C5_GET(h, g) HPDI32_IRQ_TRIGGER_CONFIG__GET((h),HPDI32_WHICH_IRQ_C5_,(g)) |
| |
| #define | HPDI32_IRQ_TRIGGER_CONFIG__C5_SET(h, s) HPDI32_IRQ_TRIGGER_CONFIG__SET((h),HPDI32_WHICH_IRQ_C5_,(s)) |
| |
| #define | HPDI32_IRQ_TRIGGER_CONFIG__C5_RESET(h) HPDI32_IRQ_TRIGGER_CONFIG__SET((h),HPDI32_WHICH_IRQ_C5_,HPDI32_IRQ_TRIGGER_CONFIG_DEFAULT) |
| |
| #define | HPDI32_IRQ_TRIGGER_CONFIG__C5_EDGE_HI(h) HPDI32_IRQ_TRIGGER_CONFIG__C5_SET((h),HPDI32_IRQ_TRIGGER_CONFIG_EDGE_HI) |
| |
| #define | HPDI32_IRQ_TRIGGER_CONFIG__C5_EDGE_LOW(h) HPDI32_IRQ_TRIGGER_CONFIG__C5_SET((h),HPDI32_IRQ_TRIGGER_CONFIG_EDGE_LOW) |
| |
| #define | HPDI32_IRQ_TRIGGER_CONFIG__C5_LEV_HI(h) HPDI32_IRQ_TRIGGER_CONFIG__C5_SET((h),HPDI32_IRQ_TRIGGER_CONFIG_LEVEL_HI) |
| |
| #define | HPDI32_IRQ_TRIGGER_CONFIG__C5_LEV_LOW(h) HPDI32_IRQ_TRIGGER_CONFIG__C5_SET((h),HPDI32_IRQ_TRIGGER_CONFIG_LEVEL_LOW) |
| |
| #define | HPDI32_IRQ_TRIGGER_CONFIG__C6_GET(h, g) HPDI32_IRQ_TRIGGER_CONFIG__GET((h),HPDI32_WHICH_IRQ_C6_,(g)) |
| |
| #define | HPDI32_IRQ_TRIGGER_CONFIG__C6_SET(h, s) HPDI32_IRQ_TRIGGER_CONFIG__SET((h),HPDI32_WHICH_IRQ_C6_,(s)) |
| |
| #define | HPDI32_IRQ_TRIGGER_CONFIG__C6_RESET(h) HPDI32_IRQ_TRIGGER_CONFIG__SET((h),HPDI32_WHICH_IRQ_C6_,HPDI32_IRQ_TRIGGER_CONFIG_DEFAULT) |
| |
| #define | HPDI32_IRQ_TRIGGER_CONFIG__C6_EDGE_HI(h) HPDI32_IRQ_TRIGGER_CONFIG__C6_SET((h),HPDI32_IRQ_TRIGGER_CONFIG_EDGE_HI) |
| |
| #define | HPDI32_IRQ_TRIGGER_CONFIG__C6_EDGE_LOW(h) HPDI32_IRQ_TRIGGER_CONFIG__C6_SET((h),HPDI32_IRQ_TRIGGER_CONFIG_EDGE_LOW) |
| |
| #define | HPDI32_IRQ_TRIGGER_CONFIG__C6_LEV_HI(h) HPDI32_IRQ_TRIGGER_CONFIG__C6_SET((h),HPDI32_IRQ_TRIGGER_CONFIG_LEVEL_HI) |
| |
| #define | HPDI32_IRQ_TRIGGER_CONFIG__C6_LEV_LOW(h) HPDI32_IRQ_TRIGGER_CONFIG__C6_SET((h),HPDI32_IRQ_TRIGGER_CONFIG_LEVEL_LOW) |
| |
| #define | HPDI32_IRQ_TRIGGER_CONFIG__TX_E_GET(h, g) HPDI32_IRQ_TRIGGER_CONFIG__GET((h),HPDI32_WHICH_IRQ_TX_E,(g)) |
| |
| #define | HPDI32_IRQ_TRIGGER_CONFIG__TX_E_SET(h, s) HPDI32_IRQ_TRIGGER_CONFIG__SET((h),HPDI32_WHICH_IRQ_TX_E,(s)) |
| |
| #define | HPDI32_IRQ_TRIGGER_CONFIG__TX_E_RESET(h) HPDI32_IRQ_TRIGGER_CONFIG__SET((h),HPDI32_WHICH_IRQ_TX_E,HPDI32_IRQ_TRIGGER_CONFIG_DEFAULT) |
| |
| #define | HPDI32_IRQ_TRIGGER_CONFIG__TX_E_EDGE_HI(h) HPDI32_IRQ_TRIGGER_CONFIG__TX_E_SET((h),HPDI32_IRQ_TRIGGER_CONFIG_EDGE_HI) |
| |
| #define | HPDI32_IRQ_TRIGGER_CONFIG__TX_E_EDGE_LOW(h) HPDI32_IRQ_TRIGGER_CONFIG__TX_E_SET((h),HPDI32_IRQ_TRIGGER_CONFIG_EDGE_LOW) |
| |
| #define | HPDI32_IRQ_TRIGGER_CONFIG__TX_E_LEV_HI(h) HPDI32_IRQ_TRIGGER_CONFIG__TX_E_SET((h),HPDI32_IRQ_TRIGGER_CONFIG_LEVEL_HI) |
| |
| #define | HPDI32_IRQ_TRIGGER_CONFIG__TX_E_LEV_LOW(h) HPDI32_IRQ_TRIGGER_CONFIG__TX_E_SET((h),HPDI32_IRQ_TRIGGER_CONFIG_LEVEL_LOW) |
| |
| #define | HPDI32_IRQ_TRIGGER_CONFIG__TX_AE_GET(h, g) HPDI32_IRQ_TRIGGER_CONFIG__GET((h),HPDI32_WHICH_IRQ_TX_AE,(g)) |
| |
| #define | HPDI32_IRQ_TRIGGER_CONFIG__TX_AE_SET(h, s) HPDI32_IRQ_TRIGGER_CONFIG__SET((h),HPDI32_WHICH_IRQ_TX_AE,(s)) |
| |
| #define | HPDI32_IRQ_TRIGGER_CONFIG__TX_AE_RESET(h) HPDI32_IRQ_TRIGGER_CONFIG__SET((h),HPDI32_WHICH_IRQ_TX_AE,HPDI32_IRQ_TRIGGER_CONFIG_DEFAULT) |
| |
| #define | HPDI32_IRQ_TRIGGER_CONFIG__TX_AE_EDGE_HI(h) HPDI32_IRQ_TRIGGER_CONFIG__TX_AE_SET((h),HPDI32_IRQ_TRIGGER_CONFIG_EDGE_HI) |
| |
| #define | HPDI32_IRQ_TRIGGER_CONFIG__TX_AE_EDGE_LOW(h) HPDI32_IRQ_TRIGGER_CONFIG__TX_AE_SET((h),HPDI32_IRQ_TRIGGER_CONFIG_EDGE_LOW) |
| |
| #define | HPDI32_IRQ_TRIGGER_CONFIG__TX_AE_LEV_HI(h) HPDI32_IRQ_TRIGGER_CONFIG__TX_AE_SET((h),HPDI32_IRQ_TRIGGER_CONFIG_LEVEL_HI) |
| |
| #define | HPDI32_IRQ_TRIGGER_CONFIG__TX_AE_LEV_LOW(h) HPDI32_IRQ_TRIGGER_CONFIG__TX_AE_SET((h),HPDI32_IRQ_TRIGGER_CONFIG_LEVEL_LOW) |
| |
| #define | HPDI32_IRQ_TRIGGER_CONFIG__RX_AF_GET(h, g) HPDI32_IRQ_TRIGGER_CONFIG__GET((h),HPDI32_WHICH_IRQ_RX_AF,(g)) |
| |
| #define | HPDI32_IRQ_TRIGGER_CONFIG__RX_AF_SET(h, s) HPDI32_IRQ_TRIGGER_CONFIG__SET((h),HPDI32_WHICH_IRQ_RX_AF,(s)) |
| |
| #define | HPDI32_IRQ_TRIGGER_CONFIG__RX_AF_RESET(h) HPDI32_IRQ_TRIGGER_CONFIG__SET((h),HPDI32_WHICH_IRQ_RX_AF,HPDI32_IRQ_TRIGGER_CONFIG_DEFAULT) |
| |
| #define | HPDI32_IRQ_TRIGGER_CONFIG__RX_AF_EDGE_HI(h) HPDI32_IRQ_TRIGGER_CONFIG__RX_AF_SET((h),HPDI32_IRQ_TRIGGER_CONFIG_EDGE_HI) |
| |
| #define | HPDI32_IRQ_TRIGGER_CONFIG__RX_AF_EDGE_LOW(h) HPDI32_IRQ_TRIGGER_CONFIG__RX_AF_SET((h),HPDI32_IRQ_TRIGGER_CONFIG_EDGE_LOW) |
| |
| #define | HPDI32_IRQ_TRIGGER_CONFIG__RX_AF_LEV_HI(h) HPDI32_IRQ_TRIGGER_CONFIG__RX_AF_SET((h),HPDI32_IRQ_TRIGGER_CONFIG_LEVEL_HI) |
| |
| #define | HPDI32_IRQ_TRIGGER_CONFIG__RX_AF_LEV_LOW(h) HPDI32_IRQ_TRIGGER_CONFIG__RX_AF_SET((h),HPDI32_IRQ_TRIGGER_CONFIG_LEVEL_LOW) |
| |
| #define | HPDI32_IRQ_TRIGGER_CONFIG__RX_F_GET(h, g) HPDI32_IRQ_TRIGGER_CONFIG__GET((h),HPDI32_WHICH_IRQ_RX_F,(g)) |
| |
| #define | HPDI32_IRQ_TRIGGER_CONFIG__RX_F_SET(h, s) HPDI32_IRQ_TRIGGER_CONFIG__SET((h),HPDI32_WHICH_IRQ_RX_F,(s)) |
| |
| #define | HPDI32_IRQ_TRIGGER_CONFIG__RX_F_RESET(h) HPDI32_IRQ_TRIGGER_CONFIG__SET((h),HPDI32_WHICH_IRQ_RX_F,HPDI32_IRQ_TRIGGER_CONFIG_DEFAULT) |
| |
| #define | HPDI32_IRQ_TRIGGER_CONFIG__RX_F_EDGE_HI(h) HPDI32_IRQ_TRIGGER_CONFIG__RX_F_SET((h),HPDI32_IRQ_TRIGGER_CONFIG_EDGE_HI) |
| |
| #define | HPDI32_IRQ_TRIGGER_CONFIG__RX_F_EDGE_LOW(h) HPDI32_IRQ_TRIGGER_CONFIG__RX_F_SET((h),HPDI32_IRQ_TRIGGER_CONFIG_EDGE_LOW) |
| |
| #define | HPDI32_IRQ_TRIGGER_CONFIG__RX_F_LEV_HI(h) HPDI32_IRQ_TRIGGER_CONFIG__RX_F_SET((h),HPDI32_IRQ_TRIGGER_CONFIG_LEVEL_HI) |
| |
| #define | HPDI32_IRQ_TRIGGER_CONFIG__RX_F_LEV_LOW(h) HPDI32_IRQ_TRIGGER_CONFIG__RX_F_SET((h),HPDI32_IRQ_TRIGGER_CONFIG_LEVEL_LOW) |
| |
| #define | HPDI32_IRQ_TRIGGER_CONFIG__FVB_GET(h, g) HPDI32_IRQ_TRIGGER_CONFIG__C0A_GET((h),(g)) |
| |
| #define | HPDI32_IRQ_TRIGGER_CONFIG__FVB_SET(h, s) HPDI32_IRQ_TRIGGER_CONFIG__C0A_SET((h),(s)) |
| |
| #define | HPDI32_IRQ_TRIGGER_CONFIG__FVB_RESET(h) HPDI32_IRQ_TRIGGER_CONFIG__C0A_SET((h),HPDI32_IRQ_TRIGGER_CONFIG_DEFAULT) |
| |
| #define | HPDI32_IRQ_TRIGGER_CONFIG__FVB_EDGE_HI(h) HPDI32_IRQ_TRIGGER_CONFIG__C0A_EDGE_HI((h)) |
| |
| #define | HPDI32_IRQ_TRIGGER_CONFIG__FVB_EDGE_LOW(h) HPDI32_IRQ_TRIGGER_CONFIG__C0A_EDGE_LOW((h)) |
| |
| #define | HPDI32_IRQ_TRIGGER_CONFIG__FVB_LEV_HI(h) HPDI32_IRQ_TRIGGER_CONFIG__C0A_LEV_HI((h)) |
| |
| #define | HPDI32_IRQ_TRIGGER_CONFIG__FVB_LEV_LOW(h) HPDI32_IRQ_TRIGGER_CONFIG__C0A_LEV_LOW((h)) |
| |
| #define | HPDI32_IRQ_TRIGGER_CONFIG__FVE_GET(h, g) HPDI32_IRQ_TRIGGER_CONFIG__C0I_GET((h),(g)) |
| |
| #define | HPDI32_IRQ_TRIGGER_CONFIG__FVE_SET(h, s) HPDI32_IRQ_TRIGGER_CONFIG__C0I_SET((h),(s)) |
| |
| #define | HPDI32_IRQ_TRIGGER_CONFIG__FVE_RESET(h) HPDI32_IRQ_TRIGGER_CONFIG__C0I_SET((h),HPDI32_IRQ_TRIGGER_CONFIG_DEFAULT) |
| |
| #define | HPDI32_IRQ_TRIGGER_CONFIG__FVE_EDGE_HI(h) HPDI32_IRQ_TRIGGER_CONFIG__C0I_EDGE_HI((h)) |
| |
| #define | HPDI32_IRQ_TRIGGER_CONFIG__FVE_EDGE_LOW(h) HPDI32_IRQ_TRIGGER_CONFIG__C0I_EDGE_LOW((h)) |
| |
| #define | HPDI32_IRQ_TRIGGER_CONFIG__FVE_LEV_HI(h) HPDI32_IRQ_TRIGGER_CONFIG__C0I_LEV_HI((h)) |
| |
| #define | HPDI32_IRQ_TRIGGER_CONFIG__FVE_LEV_LOW(h) HPDI32_IRQ_TRIGGER_CONFIG__C0I_LEV_LOW((h)) |
| |
| #define | HPDI32_IRQ_TRIGGER_CONFIG__LV_GET(h, g) HPDI32_IRQ_TRIGGER_CONFIG__C1_GET((h),(g)) |
| |
| #define | HPDI32_IRQ_TRIGGER_CONFIG__LV_SET(h, s) HPDI32_IRQ_TRIGGER_CONFIG__C1_SET((h),(s)) |
| |
| #define | HPDI32_IRQ_TRIGGER_CONFIG__LV_RESET(h) HPDI32_IRQ_TRIGGER_CONFIG__C1_SET((h),HPDI32_IRQ_TRIGGER_CONFIG_DEFAULT) |
| |
| #define | HPDI32_IRQ_TRIGGER_CONFIG__LV_EDGE_HI(h) HPDI32_IRQ_TRIGGER_CONFIG__C1_EDGE_HI((h)) |
| |
| #define | HPDI32_IRQ_TRIGGER_CONFIG__LV_EDGE_LOW(h) HPDI32_IRQ_TRIGGER_CONFIG__C1_EDGE_LOW((h)) |
| |
| #define | HPDI32_IRQ_TRIGGER_CONFIG__LV_LEV_HI(h) HPDI32_IRQ_TRIGGER_CONFIG__C1_LEV_HI((h)) |
| |
| #define | HPDI32_IRQ_TRIGGER_CONFIG__LV_LEV_LOW(h) HPDI32_IRQ_TRIGGER_CONFIG__C1_LEV_LOW((h)) |
| |
| #define | HPDI32_IRQ_TRIGGER_CONFIG__SV_GET(h, g) HPDI32_IRQ_TRIGGER_CONFIG__C2_GET((h),(g)) |
| |
| #define | HPDI32_IRQ_TRIGGER_CONFIG__SV_SET(h, s) HPDI32_IRQ_TRIGGER_CONFIG__C2_SET((h),(s)) |
| |
| #define | HPDI32_IRQ_TRIGGER_CONFIG__SV_RESET(h) HPDI32_IRQ_TRIGGER_CONFIG__C2_SET((h),HPDI32_IRQ_TRIGGER_CONFIG_DEFAULT) |
| |
| #define | HPDI32_IRQ_TRIGGER_CONFIG__SV_EDGE_HI(h) HPDI32_IRQ_TRIGGER_CONFIG__C2_EDGE_HI((h)) |
| |
| #define | HPDI32_IRQ_TRIGGER_CONFIG__SV_EDGE_LOW(h) HPDI32_IRQ_TRIGGER_CONFIG__C2_EDGE_LOW((h)) |
| |
| #define | HPDI32_IRQ_TRIGGER_CONFIG__SV_LEV_HI(h) HPDI32_IRQ_TRIGGER_CONFIG__C2_LEV_HI((h)) |
| |
| #define | HPDI32_IRQ_TRIGGER_CONFIG__SV_LEV_LOW(h) HPDI32_IRQ_TRIGGER_CONFIG__C2_LEV_LOW((h)) |
| |
| #define | HPDI32_IRQ_TRIGGER_CONFIG__RR_GET(h, g) HPDI32_IRQ_TRIGGER_CONFIG__C3_GET((h),(g)) |
| |
| #define | HPDI32_IRQ_TRIGGER_CONFIG__RR_SET(h, s) HPDI32_IRQ_TRIGGER_CONFIG__C3_SET((h),(s)) |
| |
| #define | HPDI32_IRQ_TRIGGER_CONFIG__RR_RESET(h) HPDI32_IRQ_TRIGGER_CONFIG__C3_SET((h),HPDI32_IRQ_TRIGGER_CONFIG_DEFAULT) |
| |
| #define | HPDI32_IRQ_TRIGGER_CONFIG__RR_EDGE_HI(h) HPDI32_IRQ_TRIGGER_CONFIG__C3_EDGE_HI((h)) |
| |
| #define | HPDI32_IRQ_TRIGGER_CONFIG__RR_EDGE_LOW(h) HPDI32_IRQ_TRIGGER_CONFIG__C3_EDGE_LOW((h)) |
| |
| #define | HPDI32_IRQ_TRIGGER_CONFIG__RR_LEV_HI(h) HPDI32_IRQ_TRIGGER_CONFIG__C3_LEV_HI((h)) |
| |
| #define | HPDI32_IRQ_TRIGGER_CONFIG__RR_LEV_LOW(h) HPDI32_IRQ_TRIGGER_CONFIG__C3_LEV_LOW((h)) |
| |
| #define | HPDI32_IRQ_TRIGGER_CONFIG__TR_GET(h, g) HPDI32_IRQ_TRIGGER_CONFIG__C4_GET((h),(g)) |
| |
| #define | HPDI32_IRQ_TRIGGER_CONFIG__TR_SET(h, s) HPDI32_IRQ_TRIGGER_CONFIG__C4_SET((h),(s)) |
| |
| #define | HPDI32_IRQ_TRIGGER_CONFIG__TR_RESET(h) HPDI32_IRQ_TRIGGER_CONFIG__C4_SET((h),HPDI32_IRQ_TRIGGER_CONFIG_DEFAULT) |
| |
| #define | HPDI32_IRQ_TRIGGER_CONFIG__TR_EDGE_HI(h) HPDI32_IRQ_TRIGGER_CONFIG__C4_EDGE_HI((h)) |
| |
| #define | HPDI32_IRQ_TRIGGER_CONFIG__TR_EDGE_LOW(h) HPDI32_IRQ_TRIGGER_CONFIG__C4_EDGE_LOW((h)) |
| |
| #define | HPDI32_IRQ_TRIGGER_CONFIG__TR_LEV_HI(h) HPDI32_IRQ_TRIGGER_CONFIG__C4_LEV_HI((h)) |
| |
| #define | HPDI32_IRQ_TRIGGER_CONFIG__TR_LEV_LOW(h) HPDI32_IRQ_TRIGGER_CONFIG__C4_LEV_LOW((h)) |
| |
| #define | HPDI32_IRQ_TRIGGER_CONFIG__TE_GET(h, g) HPDI32_IRQ_TRIGGER_CONFIG__C5_GET((h),(g)) |
| |
| #define | HPDI32_IRQ_TRIGGER_CONFIG__TE_SET(h, s) HPDI32_IRQ_TRIGGER_CONFIG__C5_SET((h),(s)) |
| |
| #define | HPDI32_IRQ_TRIGGER_CONFIG__TE_RESET(h) HPDI32_IRQ_TRIGGER_CONFIG__C5_SET((h),HPDI32_IRQ_TRIGGER_CONFIG_DEFAULT) |
| |
| #define | HPDI32_IRQ_TRIGGER_CONFIG__TE_EDGE_HI(h) HPDI32_IRQ_TRIGGER_CONFIG__C5_EDGE_HI((h)) |
| |
| #define | HPDI32_IRQ_TRIGGER_CONFIG__TE_EDGE_LOW(h) HPDI32_IRQ_TRIGGER_CONFIG__C5_EDGE_LOW((h)) |
| |
| #define | HPDI32_IRQ_TRIGGER_CONFIG__TE_LEV_HI(h) HPDI32_IRQ_TRIGGER_CONFIG__C5_LEV_HI((h)) |
| |
| #define | HPDI32_IRQ_TRIGGER_CONFIG__TE_LEV_LOW(h) HPDI32_IRQ_TRIGGER_CONFIG__C5_LEV_LOW((h)) |
| |
| #define | HPDI32_IRQ_TRIGGER_CONFIG__RE_GET(h, g) HPDI32_IRQ_TRIGGER_CONFIG__C6_GET((h),(g)) |
| |
| #define | HPDI32_IRQ_TRIGGER_CONFIG__RE_SET(h, s) HPDI32_IRQ_TRIGGER_CONFIG__C6_SET((h),(s)) |
| |
| #define | HPDI32_IRQ_TRIGGER_CONFIG__RE_RESET(h) HPDI32_IRQ_TRIGGER_CONFIG__C6_SET((h),HPDI32_IRQ_TRIGGER_CONFIG_DEFAULT) |
| |
| #define | HPDI32_IRQ_TRIGGER_CONFIG__RE_EDGE_HI(h) HPDI32_IRQ_TRIGGER_CONFIG__C6_EDGE_HI((h)) |
| |
| #define | HPDI32_IRQ_TRIGGER_CONFIG__RE_EDGE_LOW(h) HPDI32_IRQ_TRIGGER_CONFIG__C6_EDGE_LOW((h)) |
| |
| #define | HPDI32_IRQ_TRIGGER_CONFIG__RE_LEV_HI(h) HPDI32_IRQ_TRIGGER_CONFIG__C6_LEV_HI((h)) |
| |
| #define | HPDI32_IRQ_TRIGGER_CONFIG__RE_LEV_LOW(h) HPDI32_IRQ_TRIGGER_CONFIG__C6_LEV_LOW((h)) |
| |
| #define | HPDI32_IRQ_TRIGGER_CONFIG__GPIO_0_GET(h, g) HPDI32_IRQ_TRIGGER_CONFIG__C1_GET((h),(g)) |
| |
| #define | HPDI32_IRQ_TRIGGER_CONFIG__GPIO_0_SET(h, s) HPDI32_IRQ_TRIGGER_CONFIG__C1_SET((h),(s)) |
| |
| #define | HPDI32_IRQ_TRIGGER_CONFIG__GPIO_0_RESET(h) HPDI32_IRQ_TRIGGER_CONFIG__C1_SET((h),HPDI32_IRQ_TRIGGER_CONFIG_DEFAULT) |
| |
| #define | HPDI32_IRQ_TRIGGER_CONFIG__GPIO_0_EDGE_HI(h) HPDI32_IRQ_TRIGGER_CONFIG__C1_EDGE_HI((h)) |
| |
| #define | HPDI32_IRQ_TRIGGER_CONFIG__GPIO_0_EDGE_LOW(h) HPDI32_IRQ_TRIGGER_CONFIG__C1_EDGE_LOW((h)) |
| |
| #define | HPDI32_IRQ_TRIGGER_CONFIG__GPIO_0_LEV_HI(h) HPDI32_IRQ_TRIGGER_CONFIG__C1_LEV_HI((h)) |
| |
| #define | HPDI32_IRQ_TRIGGER_CONFIG__GPIO_0_LEV_LOW(h) HPDI32_IRQ_TRIGGER_CONFIG__C1_LEV_LOW((h)) |
| |
| #define | HPDI32_IRQ_TRIGGER_CONFIG__GPIO_1_GET(h, g) HPDI32_IRQ_TRIGGER_CONFIG__C2_GET((h),(g)) |
| |
| #define | HPDI32_IRQ_TRIGGER_CONFIG__GPIO_1_SET(h, s) HPDI32_IRQ_TRIGGER_CONFIG__C2_SET((h),(s)) |
| |
| #define | HPDI32_IRQ_TRIGGER_CONFIG__GPIO_1_RESET(h) HPDI32_IRQ_TRIGGER_CONFIG__C2_SET((h),HPDI32_IRQ_TRIGGER_CONFIG_DEFAULT) |
| |
| #define | HPDI32_IRQ_TRIGGER_CONFIG__GPIO_1_EDGE_HI(h) HPDI32_IRQ_TRIGGER_CONFIG__C2_EDGE_HI((h)) |
| |
| #define | HPDI32_IRQ_TRIGGER_CONFIG__GPIO_1_EDGE_LOW(h) HPDI32_IRQ_TRIGGER_CONFIG__C2_EDGE_LOW((h)) |
| |
| #define | HPDI32_IRQ_TRIGGER_CONFIG__GPIO_1_LEV_HI(h) HPDI32_IRQ_TRIGGER_CONFIG__C2_LEV_HI((h)) |
| |
| #define | HPDI32_IRQ_TRIGGER_CONFIG__GPIO_1_LEV_LOW(h) HPDI32_IRQ_TRIGGER_CONFIG__C2_LEV_LOW((h)) |
| |
| #define | HPDI32_IRQ_TRIGGER_CONFIG__GPIO_2_GET(h, g) HPDI32_IRQ_TRIGGER_CONFIG__C3_GET((h),(g)) |
| |
| #define | HPDI32_IRQ_TRIGGER_CONFIG__GPIO_2_SET(h, s) HPDI32_IRQ_TRIGGER_CONFIG__C3_SET((h),(s)) |
| |
| #define | HPDI32_IRQ_TRIGGER_CONFIG__GPIO_2_RESET(h) HPDI32_IRQ_TRIGGER_CONFIG__C3_SET((h),HPDI32_IRQ_TRIGGER_CONFIG_DEFAULT) |
| |
| #define | HPDI32_IRQ_TRIGGER_CONFIG__GPIO_2_EDGE_HI(h) HPDI32_IRQ_TRIGGER_CONFIG__C3_EDGE_HI((h)) |
| |
| #define | HPDI32_IRQ_TRIGGER_CONFIG__GPIO_2_EDGE_LOW(h) HPDI32_IRQ_TRIGGER_CONFIG__C3_EDGE_LOW((h)) |
| |
| #define | HPDI32_IRQ_TRIGGER_CONFIG__GPIO_2_LEV_HI(h) HPDI32_IRQ_TRIGGER_CONFIG__C3_LEV_HI((h)) |
| |
| #define | HPDI32_IRQ_TRIGGER_CONFIG__GPIO_2_LEV_LOW(h) HPDI32_IRQ_TRIGGER_CONFIG__C3_LEV_LOW((h)) |
| |
| #define | HPDI32_IRQ_TRIGGER_CONFIG__GPIO_3_GET(h, g) HPDI32_IRQ_TRIGGER_CONFIG__C4_GET((h),(g)) |
| |
| #define | HPDI32_IRQ_TRIGGER_CONFIG__GPIO_3_SET(h, s) HPDI32_IRQ_TRIGGER_CONFIG__C4_SET((h),(s)) |
| |
| #define | HPDI32_IRQ_TRIGGER_CONFIG__GPIO_3_RESET(h) HPDI32_IRQ_TRIGGER_CONFIG__C4_SET((h),HPDI32_IRQ_TRIGGER_CONFIG_DEFAULT) |
| |
| #define | HPDI32_IRQ_TRIGGER_CONFIG__GPIO_3_EDGE_HI(h) HPDI32_IRQ_TRIGGER_CONFIG__C4_EDGE_HI((h)) |
| |
| #define | HPDI32_IRQ_TRIGGER_CONFIG__GPIO_3_EDGE_LOW(h) HPDI32_IRQ_TRIGGER_CONFIG__C4_EDGE_LOW((h)) |
| |
| #define | HPDI32_IRQ_TRIGGER_CONFIG__GPIO_3_LEV_HI(h) HPDI32_IRQ_TRIGGER_CONFIG__C4_LEV_HI((h)) |
| |
| #define | HPDI32_IRQ_TRIGGER_CONFIG__GPIO_3_LEV_LOW(h) HPDI32_IRQ_TRIGGER_CONFIG__C4_LEV_LOW((h)) |
| |
| #define | HPDI32_IRQ_TRIGGER_CONFIG__GPIO_4_GET(h, g) HPDI32_IRQ_TRIGGER_CONFIG__C5_GET((h),(g)) |
| |
| #define | HPDI32_IRQ_TRIGGER_CONFIG__GPIO_4_SET(h, s) HPDI32_IRQ_TRIGGER_CONFIG__C5_SET((h),(s)) |
| |
| #define | HPDI32_IRQ_TRIGGER_CONFIG__GPIO_4_RESET(h) HPDI32_IRQ_TRIGGER_CONFIG__C5_SET((h),HPDI32_IRQ_TRIGGER_CONFIG_DEFAULT) |
| |
| #define | HPDI32_IRQ_TRIGGER_CONFIG__GPIO_4_EDGE_HI(h) HPDI32_IRQ_TRIGGER_CONFIG__C5_EDGE_HI((h)) |
| |
| #define | HPDI32_IRQ_TRIGGER_CONFIG__GPIO_4_EDGE_LOW(h) HPDI32_IRQ_TRIGGER_CONFIG__C5_EDGE_LOW((h)) |
| |
| #define | HPDI32_IRQ_TRIGGER_CONFIG__GPIO_4_LEV_HI(h) HPDI32_IRQ_TRIGGER_CONFIG__C5_LEV_HI((h)) |
| |
| #define | HPDI32_IRQ_TRIGGER_CONFIG__GPIO_4_LEV_LOW(h) HPDI32_IRQ_TRIGGER_CONFIG__C5_LEV_LOW((h)) |
| |
| #define | HPDI32_IRQ_TRIGGER_CONFIG__GPIO_5_GET(h, g) HPDI32_IRQ_TRIGGER_CONFIG__C6_GET((h),(g)) |
| |
| #define | HPDI32_IRQ_TRIGGER_CONFIG__GPIO_5_SET(h, s) HPDI32_IRQ_TRIGGER_CONFIG__C6_SET((h),(s)) |
| |
| #define | HPDI32_IRQ_TRIGGER_CONFIG__GPIO_5_RESET(h) HPDI32_IRQ_TRIGGER_CONFIG__C6_SET((h),HPDI32_IRQ_TRIGGER_CONFIG_DEFAULT) |
| |
| #define | HPDI32_IRQ_TRIGGER_CONFIG__GPIO_5_EDGE_HI(h) HPDI32_IRQ_TRIGGER_CONFIG__C6_EDGE_HI((h)) |
| |
| #define | HPDI32_IRQ_TRIGGER_CONFIG__GPIO_5_EDGE_LOW(h) HPDI32_IRQ_TRIGGER_CONFIG__C6_EDGE_LOW((h)) |
| |
| #define | HPDI32_IRQ_TRIGGER_CONFIG__GPIO_5_LEV_HI(h) HPDI32_IRQ_TRIGGER_CONFIG__C6_LEV_HI((h)) |
| |
| #define | HPDI32_IRQ_TRIGGER_CONFIG__GPIO_5_LEV_LOW(h) HPDI32_IRQ_TRIGGER_CONFIG__C6_LEV_LOW((h)) |
| |
| #define | HPDI32_IRQ_TRIGGER_CONFIG__GPIO_6H_GET(h, g) HPDI32_IRQ_TRIGGER_CONFIG__C0A_GET((h),(g)) |
| |
| #define | HPDI32_IRQ_TRIGGER_CONFIG__GPIO_6H_SET(h, s) HPDI32_IRQ_TRIGGER_CONFIG__C0A_SET((h),(s)) |
| |
| #define | HPDI32_IRQ_TRIGGER_CONFIG__GPIO_6H_RESET(h) HPDI32_IRQ_TRIGGER_CONFIG__C0A_SET((h),HPDI32_IRQ_TRIGGER_CONFIG_DEFAULT) |
| |
| #define | HPDI32_IRQ_TRIGGER_CONFIG__GPIO_6H_EDGE_HI(h) HPDI32_IRQ_TRIGGER_CONFIG__C0A_EDGE_HI((h)) |
| |
| #define | HPDI32_IRQ_TRIGGER_CONFIG__GPIO_6H_EDGE_LOW(h) HPDI32_IRQ_TRIGGER_CONFIG__C0A_EDGE_LOW((h)) |
| |
| #define | HPDI32_IRQ_TRIGGER_CONFIG__GPIO_6H_LEV_HI(h) HPDI32_IRQ_TRIGGER_CONFIG__C0A_LEV_HI((h)) |
| |
| #define | HPDI32_IRQ_TRIGGER_CONFIG__GPIO_6H_LEV_LOW(h) HPDI32_IRQ_TRIGGER_CONFIG__C0A_LEV_LOW((h)) |
| |
| #define | HPDI32_IRQ_TRIGGER_CONFIG__GPIO_6L_GET(h, g) HPDI32_IRQ_TRIGGER_CONFIG__C0I_GET((h),(g)) |
| |
| #define | HPDI32_IRQ_TRIGGER_CONFIG__GPIO_6L_SET(h, s) HPDI32_IRQ_TRIGGER_CONFIG__C0I_SET((h),(s)) |
| |
| #define | HPDI32_IRQ_TRIGGER_CONFIG__GPIO_6L_RESET(h) HPDI32_IRQ_TRIGGER_CONFIG__C0I_SET((h),HPDI32_IRQ_TRIGGER_CONFIG_DEFAULT) |
| |
| #define | HPDI32_IRQ_TRIGGER_CONFIG__GPIO_6L_EDGE_HI(h) HPDI32_IRQ_TRIGGER_CONFIG__C0I_EDGE_HI((h)) |
| |
| #define | HPDI32_IRQ_TRIGGER_CONFIG__GPIO_6L_EDGE_LOW(h) HPDI32_IRQ_TRIGGER_CONFIG__C0I_EDGE_LOW((h)) |
| |
| #define | HPDI32_IRQ_TRIGGER_CONFIG__GPIO_6L_LEV_HI(h) HPDI32_IRQ_TRIGGER_CONFIG__C0I_LEV_HI((h)) |
| |
| #define | HPDI32_IRQ_TRIGGER_CONFIG__GPIO_6L_LEV_LOW(h) HPDI32_IRQ_TRIGGER_CONFIG__C0I_LEV_LOW((h)) |
| |
| #define | HPDI32_MISC_ENCODE(i) HPDI32_CONFIG_ENCODE(HPDI32_CONFIG_GROUP_MISC, (i)) |
| |
| #define | HPDI32_MISC_BOARD_JUMPERS HPDI32_MISC_ENCODE(0) /* GET only */ |
| |
| #define | HPDI32_MISC_FAVOR_TX HPDI32_MISC_ENCODE(1) |
| |
| #define | HPDI32_MISC_FEATURES HPDI32_MISC_ENCODE(2) /* GET only */ |
| |
| #define | HPDI32_MISC_MAP_GSC_REGS HPDI32_MISC_ENCODE(3) |
| |
| #define | HPDI32_MISC_MAP_GSC_REGS_PTR HPDI32_MISC_ENCODE(4) /* GET only */ |
| |
| #define | HPDI32_MISC_MAP_PLX_REGS HPDI32_MISC_ENCODE(5) |
| |
| #define | HPDI32_MISC_PCI_BUS_WIDTH HPDI32_MISC_ENCODE(6) /* GET only */ |
| |
| #define | HPDI32_MISC_STRICT_ARGUMENTS HPDI32_MISC_ENCODE(7) |
| |
| #define | HPDI32_MISC_STRICT_CONFIG HPDI32_MISC_ENCODE(8) |
| |
| #define | HPDI32_MISC_TX_RX_TRI_STATE HPDI32_MISC_ENCODE(9) |
| |
| #define | HPDI32_MISC_BOARD_JUMPERS__GET(h, g) HPDI32_CONFIG_GET((h),HPDI32_MISC_BOARD_JUMPERS,0,(g)) |
| |
| #define | HPDI32_MISC_FAVOR_TX_DISABLE 0 |
| |
| #define | HPDI32_MISC_FAVOR_TX_ENABLE 1 |
| |
| #define | HPDI32_MISC_FAVOR_TX_DEFAULT HPDI32_MISC_FAVOR_TX_ENABLE |
| |
| #define | HPDI32_MISC_FAVOR_TX__GET(h, g) HPDI32_CONFIG_GET((h),HPDI32_MISC_FAVOR_TX,0,(g)) |
| |
| #define | HPDI32_MISC_FAVOR_TX__SET(h, s) HPDI32_CONFIG_SET((h),HPDI32_MISC_FAVOR_TX,0,(s)) |
| |
| #define | HPDI32_MISC_FAVOR_TX__NO(h) HPDI32_MISC_FAVOR_TX__SET((h),HPDI32_MISC_FAVOR_TX_DISABLE) |
| |
| #define | HPDI32_MISC_FAVOR_TX__YES(h) HPDI32_MISC_FAVOR_TX__SET((h),HPDI32_MISC_FAVOR_TX_ENABLE) |
| |
| #define | HPDI32_MISC_FEATURES_ABSENT 0 |
| |
| #define | HPDI32_MISC_FEATURES_PRESENT 1 |
| |
| #define | HPDI32_MISC_FEATURES_FSR 0 /* SET field: Is Feature Set Register present? */ |
| |
| #define | HPDI32_MISC_FEATURES_FIFO_SIZE 1 /* SET field: Are FIFO Size Registers present? */ |
| |
| #define | HPDI32_MISC_FEATURES_ICR 2 /* SET field: Are IELR and IHLR present? */ |
| |
| #define | HPDI32_MISC_FEATURES_GPIO_0_5 3 /* SET field: Is GPIO 0-5 supported? */ |
| |
| #define | HPDI32_MISC_FEATURES_GPIO_6 4 /* SET field: Is GPIO 6 supported? */ |
| |
| #define | HPDI32_MISC_FEATURES_DMA_CH1 5 /* SET field: Is DMA channel 1 supported? */ |
| |
| #define | HPDI32_MISC_FEATURES_OVR_UNDR_RUN 6 /* SET field: Are Over/Under Run bits present? */ |
| |
| #define | HPDI32_MISC_FEATURES_TX_AUTO_STOP 7 /* SET field: Is Tx Auto Stop (Tx Start Auto Clear Disable) present? */ |
| |
| #define | HPDI32_MISC_FEATURES_1_CYCLE_DISABLE 8 /* SET field: Is Single Cycle Disable present? */ |
| |
| #define | HPDI32_MISC_FEATURES_USER_JUMPERS 9 /* SET field: Are the User Jumpers present? */ |
| |
| #define | HPDI32_MISC_FEATURES_COUNT 10 /* SET field: How many feature entries are supported? */ |
| |
| #define | HPDI32_MISC_FEATURES_LAST_INDEX 10 |
| |
| #define | HPDI32_MISC_FEATURES__GET(h, s, g) HPDI32_CONFIG_SET_GET((h),HPDI32_MISC_FEATURES,0,(s),(g)) |
| |
| #define | HPDI32_MISC_FEATURES__COUNT(h, g) HPDI32_MISC_FEATURES__GET((h),HPDI32_MISC_FEATURES_COUNT,(g)) |
| |
| #define | HPDI32_MISC_FEATURES__DMA_CH1(h, g) HPDI32_MISC_FEATURES__GET((h),HPDI32_MISC_FEATURES_DMA_CH1,(g)) |
| |
| #define | HPDI32_MISC_FEATURES__FIFO_SIZE(h, g) HPDI32_MISC_FEATURES__GET((h),HPDI32_MISC_FEATURES_FIFO_SIZE,(g)) |
| |
| #define | HPDI32_MISC_FEATURES__FSR(h, g) HPDI32_MISC_FEATURES__GET((h),HPDI32_MISC_FEATURES_FSR,(g)) |
| |
| #define | HPDI32_MISC_FEATURES__GPIO_0_5(h, g) HPDI32_MISC_FEATURES__GET((h),HPDI32_MISC_FEATURES_GPIO_0_5,(g)) |
| |
| #define | HPDI32_MISC_FEATURES__GPIO_6(h, g) HPDI32_MISC_FEATURES__GET((h),HPDI32_MISC_FEATURES_GPIO_6,(g)) |
| |
| #define | HPDI32_MISC_FEATURES__ICR(h, g) HPDI32_MISC_FEATURES__GET((h),HPDI32_MISC_FEATURES_ICR,(g)) |
| |
| #define | HPDI32_MISC_FEATURES__OVR_UNDR_RUN(h, g) HPDI32_MISC_FEATURES__GET((h),HPDI32_MISC_FEATURES_OVR_UNDR_RUN,(g)) |
| |
| #define | HPDI32_MISC_FEATURES__TX_AUTO_STOP(h, g) HPDI32_MISC_FEATURES__GET((h),HPDI32_MISC_FEATURES_TX_AUTO_STOP,(g)) |
| |
| #define | HPDI32_MISC_FEATURES__1_CYCLE_DISABLE(h, g) HPDI32_MISC_FEATURES__GET((h),HPDI32_MISC_FEATURES_1_CYCLE_DISABLE,(g)) |
| |
| #define | HPDI32_MISC_FEATURES__USER_JUMPERS(h, g) HPDI32_MISC_FEATURES__GET((h),HPDI32_MISC_FEATURES_USER_JUMPERS,(g)) |
| |
| #define | HPDI32_MISC_MAP_GSC_REGS_DISABLE 0 |
| |
| #define | HPDI32_MISC_MAP_GSC_REGS_ENABLE 1 |
| |
| #define | HPDI32_MISC_MAP_GSC_REGS_DEFAULT HPDI32_MISC_MAP_GSC_REGS_ENABLE |
| |
| #define | HPDI32_MISC_MAP_GSC_REGS__GET(h, g) HPDI32_CONFIG_GET((h),HPDI32_MISC_MAP_GSC_REGS,0,(g)) |
| |
| #define | HPDI32_MISC_MAP_GSC_REGS__SET(h, s) HPDI32_CONFIG_SET((h),HPDI32_MISC_MAP_GSC_REGS,0,(s)) |
| |
| #define | HPDI32_MISC_MAP_GSC_REGS__RESET(h) HPDI32_CONFIG_SET((h),HPDI32_MISC_MAP_GSC_REGS,0,HPDI32_MISC_MAP_GSC_REGS_DEFAULT) |
| |
| #define | HPDI32_MISC_MAP_GSC_REGS__ENABLE(h) HPDI32_MISC_MAP_GSC_REGS__SET((h),HPDI32_MISC_MAP_GSC_REGS_ENABLE) |
| |
| #define | HPDI32_MISC_MAP_GSC_REGS_PTR__GET(h, g) HPDI32_CONFIG_GET((h),HPDI32_MISC_MAP_GSC_REGS_PTR,0,(g)) |
| |
| #define | HPDI32_MISC_MAP_PLX_REGS_DISABLE 0 |
| |
| #define | HPDI32_MISC_MAP_PLX_REGS_ENABLE 1 |
| |
| #define | HPDI32_MISC_MAP_PLX_REGS_DEFAULT HPDI32_MISC_MAP_PLX_REGS_ENABLE |
| |
| #define | HPDI32_MISC_MAP_PLX_REGS__GET(h, g) HPDI32_CONFIG_GET((h),HPDI32_MISC_MAP_PLX_REGS,0,(g)) |
| |
| #define | HPDI32_MISC_MAP_PLX_REGS__SET(h, s) HPDI32_CONFIG_SET((h),HPDI32_MISC_MAP_PLX_REGS,0,(s)) |
| |
| #define | HPDI32_MISC_MAP_PLX_REGS__RESET(h) HPDI32_MISC_MAP_PLX_REGS__SET((h),HPDI32_MISC_MAP_PLX_REGS_DEFAULT) |
| |
| #define | HPDI32_MISC_MAP_PLX_REGS__ENABLE(h) HPDI32_MISC_MAP_PLX_REGS__SET((h),HPDI32_MISC_MAP_PLX_REGS_ENABLE) |
| |
| #define | HPDI32_MISC_PCI_BUS_WIDTH_32 32 |
| |
| #define | HPDI32_MISC_PCI_BUS_WIDTH_64 64 |
| |
| #define | HPDI32_MISC_PCI_BUS_WIDTH__GET(h, g) HPDI32_CONFIG_GET((h),HPDI32_MISC_PCI_BUS_WIDTH,0,(g)) |
| |
| #define | HPDI32_MISC_STRICT_ARGUMENTS_DISABLE 0 |
| |
| #define | HPDI32_MISC_STRICT_ARGUMENTS_ENABLE 1 |
| |
| #define | HPDI32_MISC_STRICT_ARGUMENTS_DEFAULT HPDI32_MISC_STRICT_ARGUMENTS_DISABLE |
| |
| #define | HPDI32_MISC_STRICT_ARGUMENTS__GET(h, g) HPDI32_CONFIG_GET((h),HPDI32_MISC_STRICT_ARGUMENTS,0,(g)) |
| |
| #define | HPDI32_MISC_STRICT_ARGUMENTS__SET(h, s) HPDI32_CONFIG_SET((h),HPDI32_MISC_STRICT_ARGUMENTS,0,(s)) |
| |
| #define | HPDI32_MISC_STRICT_ARGUMENTS__RESET(h) HPDI32_CONFIG_SET((h),HPDI32_MISC_STRICT_ARGUMENTS,0,HPDI32_MISC_STRICT_ARGUMENTS_DEFAULT) |
| |
| #define | HPDI32_MISC_STRICT_ARGUMENTS__NO(h) HPDI32_MISC_STRICT_ARGUMENTS__SET((h),HPDI32_MISC_STRICT_ARGUMENTS_DISABLE) |
| |
| #define | HPDI32_MISC_STRICT_ARGUMENTS__YES(h) HPDI32_MISC_STRICT_ARGUMENTS__SET((h),HPDI32_MISC_STRICT_ARGUMENTS_ENABLE) |
| |
| #define | HPDI32_MISC_STRICT_CONFIG_DISABLE 0 |
| |
| #define | HPDI32_MISC_STRICT_CONFIG_ENABLE 1 |
| |
| #define | HPDI32_MISC_STRICT_CONFIG_DEFAULT HPDI32_MISC_STRICT_CONFIG_DISABLE |
| |
| #define | HPDI32_MISC_STRICT_CONFIG__GET(h, g) HPDI32_CONFIG_GET((h),HPDI32_MISC_STRICT_CONFIG,0,(g)) |
| |
| #define | HPDI32_MISC_STRICT_CONFIG__SET(h, s) HPDI32_CONFIG_SET((h),HPDI32_MISC_STRICT_CONFIG,0,(s)) |
| |
| #define | HPDI32_MISC_STRICT_CONFIG__RESET(h) HPDI32_CONFIG_SET((h),HPDI32_MISC_STRICT_CONFIG,0,HPDI32_MISC_STRICT_CONFIG_DEFAULT) |
| |
| #define | HPDI32_MISC_STRICT_CONFIG__NO(h) HPDI32_MISC_STRICT_CONFIG__SET((h),HPDI32_MISC_STRICT_CONFIG_DISABLE) |
| |
| #define | HPDI32_MISC_STRICT_CONFIG__YES(h) HPDI32_MISC_STRICT_CONFIG__SET((h),HPDI32_MISC_STRICT_CONFIG_ENABLE) |
| |
| #define | HPDI32_MISC_TX_RX_TRI_STATE_DISABLE 0 |
| |
| #define | HPDI32_MISC_TX_RX_TRI_STATE_ENABLE 1 |
| |
| #define | HPDI32_MISC_TX_RX_TRI_STATE_DEFAULT HPDI32_MISC_TX_RX_TRI_STATE_DISABLE |
| |
| #define | HPDI32_MISC_TX_RX_TRI_STATE__GET(h, g) HPDI32_CONFIG_GET((h),HPDI32_MISC_TX_RX_TRI_STATE,0,(g)) |
| |
| #define | HPDI32_MISC_TX_RX_TRI_STATE__RESET(h) HPDI32_CONFIG_SET((h),HPDI32_MISC_TX_RX_TRI_STATE,0,HPDI32_MISC_TX_RX_TRI_STATE_DEFAULT) |
| |
| #define | HPDI32_MISC_TX_RX_TRI_STATE__SET(h, s) HPDI32_CONFIG_SET((h),HPDI32_MISC_TX_RX_TRI_STATE,0,(s)) |
| |
| #define | HPDI32_MISC_TX_RX_TRI_STATE__NO(h) HPDI32_MISC_TX_RX_TRI_STATE__SET((h),HPDI32_MISC_TX_RX_TRI_STATE_DISABLE) |
| |
| #define | HPDI32_MISC_TX_RX_TRI_STATE__YES(h) HPDI32_MISC_TX_RX_TRI_STATE__SET((h),HPDI32_MISC_TX_RX_TRI_STATE_ENABLE) |
| |
| #define | HPDI32_RX_ENCODE(i) HPDI32_CONFIG_ENCODE(HPDI32_CONFIG_GROUP_RX, (i)) |
| |
| #define | HPDI32_RX_ENABLE HPDI32_RX_ENCODE(0) |
| |
| #define | HPDI32_RX_OVERRUN HPDI32_RX_ENCODE(1) |
| |
| #define | HPDI32_RX_ROW_COUNT HPDI32_RX_ENCODE(2) |
| |
| #define | HPDI32_RX_STATE HPDI32_RX_ENCODE(3) |
| |
| #define | HPDI32_RX_STATUS_COUNT HPDI32_RX_ENCODE(4) |
| |
| #define | HPDI32_RX_UNDER_RUN HPDI32_RX_ENCODE(5) |
| |
| #define | HPDI32_RX_ENABLE_NO 0 |
| |
| #define | HPDI32_RX_ENABLE_YES 1 |
| |
| #define | HPDI32_RX_ENABLE_DEFAULT HPDI32_RX_ENABLE_NO |
| |
| #define | HPDI32_RX_ENABLE__GET(h, g) HPDI32_CONFIG_GET((h),HPDI32_RX_ENABLE,0,(g)) |
| |
| #define | HPDI32_RX_ENABLE__SET(h, s) HPDI32_CONFIG_SET((h),HPDI32_RX_ENABLE,0,(s)) |
| |
| #define | HPDI32_RX_ENABLE__RESET(h) HPDI32_CONFIG_SET((h),HPDI32_RX_ENABLE,0,HPDI32_RX_ENABLE_DEFAULT) |
| |
| #define | HPDI32_RX_ENABLE__NO(h) HPDI32_RX_ENABLE__SET((h),HPDI32_RX_ENABLE_NO) |
| |
| #define | HPDI32_RX_ENABLE__YES(h) HPDI32_RX_ENABLE__SET((h),HPDI32_RX_ENABLE_YES) |
| |
| #define | HPDI32_RX_OVERRUN_IGNORE 0 /* SET option */ |
| |
| #define | HPDI32_RX_OVERRUN_CLEAR 1 /* SET option */ |
| |
| #define | HPDI32_RX_OVERRUN_DEFAULT HPDI32_RX_OVERRUN_CLEAR |
| |
| #define | HPDI32_RX_OVERRUN_NO 0 /* GET option */ |
| |
| #define | HPDI32_RX_OVERRUN_YES 1 /* GET option */ |
| |
| #define | HPDI32_RX_OVERRUN__GET(h, g) HPDI32_CONFIG_GET((h),HPDI32_RX_OVERRUN,0,(g)) |
| |
| #define | HPDI32_RX_OVERRUN__SET(h, s) HPDI32_CONFIG_SET((h),HPDI32_RX_OVERRUN,0,(s)) |
| |
| #define | HPDI32_RX_OVERRUN__CLEAR(h) HPDI32_RX_OVERRUN__SET((h),HPDI32_RX_OVERRUN_CLEAR) |
| |
| #define | HPDI32_RX_ROW_COUNT__GET(h, g) HPDI32_CONFIG_GET((h),HPDI32_RX_ROW_COUNT,0,(g)) |
| |
| #define | HPDI32_RX_STATE_ACTIVE 1 /* State GET option */ |
| |
| #define | HPDI32_RX_STATE_INACTIVE 0 /* State GET option */ |
| |
| #define | HPDI32_RX_STATE__GET(h, g) HPDI32_CONFIG_GET((h),HPDI32_RX_STATE,0,(g)) |
| |
| #define | HPDI32_RX_STATUS_COUNT__GET(h, g) HPDI32_CONFIG_GET((h),HPDI32_RX_STATUS_COUNT,0,(g)) |
| |
| #define | HPDI32_RX_UNDER_RUN_IGNORE 0 /* SET option */ |
| |
| #define | HPDI32_RX_UNDER_RUN_CLEAR 1 /* SET option */ |
| |
| #define | HPDI32_RX_UNDER_RUN_DEFAULT HPDI32_RX_UNDER_RUN_CLEAR |
| |
| #define | HPDI32_RX_UNDER_RUN_NO 0 /* GET option */ |
| |
| #define | HPDI32_RX_UNDER_RUN_YES 1 /* GET option */ |
| |
| #define | HPDI32_RX_UNDER_RUN__GET(h, g) HPDI32_CONFIG_GET((h),HPDI32_RX_UNDER_RUN,0,(g)) |
| |
| #define | HPDI32_RX_UNDER_RUN__SET(h, s) HPDI32_CONFIG_SET((h),HPDI32_RX_UNDER_RUN,0,(s)) |
| |
| #define | HPDI32_RX_UNDER_RUN__CLEAR(h) HPDI32_RX_UNDER_RUN__SET((h),HPDI32_RX_UNDER_RUN_CLEAR) |
| |
| #define | HPDI32_TX_ENCODE(i) HPDI32_CONFIG_ENCODE(HPDI32_CONFIG_GROUP_TX, (i)) |
| |
| #define | HPDI32_TX_AUTO_START HPDI32_TX_ENCODE( 0) |
| |
| #define | HPDI32_TX_AUTO_STOP HPDI32_TX_ENCODE( 1) |
| |
| #define | HPDI32_TX_CLOCK_DIVIDER HPDI32_TX_ENCODE( 2) |
| |
| #define | HPDI32_TX_ENABLE HPDI32_TX_ENCODE( 3) |
| |
| #define | HPDI32_TX_FLOW_CONTROL HPDI32_TX_ENCODE( 4) |
| |
| #define | HPDI32_TX_LINE_VALID_OFF_COUNT HPDI32_TX_ENCODE( 5) |
| |
| #define | HPDI32_TX_LINE_VALID_ON_COUNT HPDI32_TX_ENCODE( 6) |
| |
| #define | HPDI32_TX_OVERRUN HPDI32_TX_ENCODE( 7) |
| |
| #define | HPDI32_TX_REMOTE_THROTTLE HPDI32_TX_ENCODE( 8) |
| |
| #define | HPDI32_TX_REMOTE_THROTTLE_STATE HPDI32_TX_ENCODE( 9) |
| |
| #define | HPDI32_TX_STATE HPDI32_TX_ENCODE(10) |
| |
| #define | HPDI32_TX_STATUS_VALID_COUNT HPDI32_TX_ENCODE(11) |
| |
| #define | HPDI32_TX_STATUS_VALID_MIRROR HPDI32_TX_ENCODE(12) |
| |
| #define | HPDI32_TX_AUTO_START_NO 0 |
| |
| #define | HPDI32_TX_AUTO_START_YES 1 |
| |
| #define | HPDI32_TX_AUTO_START_DEFAULT HPDI32_TX_AUTO_START_YES |
| |
| #define | HPDI32_TX_AUTO_START__GET(h, g) HPDI32_CONFIG_GET((h),HPDI32_TX_AUTO_START,0,(g)) |
| |
| #define | HPDI32_TX_AUTO_START__SET(h, s) HPDI32_CONFIG_SET((h),HPDI32_TX_AUTO_START,0,(s)) |
| |
| #define | HPDI32_TX_AUTO_START__RESET(h) HPDI32_CONFIG_SET((h),HPDI32_TX_AUTO_START,0,HPDI32_TX_AUTO_START_DEFAULT) |
| |
| #define | HPDI32_TX_AUTO_START__NO(h) HPDI32_TX_AUTO_START__SET((h),HPDI32_TX_AUTO_START_NO) |
| |
| #define | HPDI32_TX_AUTO_START__YES(h) HPDI32_TX_AUTO_START__SET((h),HPDI32_TX_AUTO_START_YES) |
| |
| #define | HPDI32_TX_AUTO_STOP_NO 0 |
| |
| #define | HPDI32_TX_AUTO_STOP_YES 1 |
| |
| #define | HPDI32_TX_AUTO_STOP_DEFAULT HPDI32_TX_AUTO_STOP_NO |
| |
| #define | HPDI32_TX_AUTO_STOP__GET(h, g) HPDI32_CONFIG_GET((h),HPDI32_TX_AUTO_STOP,0,(g)) |
| |
| #define | HPDI32_TX_AUTO_STOP__SET(h, s) HPDI32_CONFIG_SET((h),HPDI32_TX_AUTO_STOP,0,(s)) |
| |
| #define | HPDI32_TX_AUTO_STOP__RESET(h) HPDI32_CONFIG_SET((h),HPDI32_TX_AUTO_STOP,0,HPDI32_TX_AUTO_STOP_DEFAULT) |
| |
| #define | HPDI32_TX_AUTO_STOP__NO(h) HPDI32_TX_AUTO_STOP__SET((h),HPDI32_TX_AUTO_STOP_NO) |
| |
| #define | HPDI32_TX_AUTO_STOP__YES(h) HPDI32_TX_AUTO_STOP__SET((h),HPDI32_TX_AUTO_STOP_YES) |
| |
| #define | HPDI32_TX_CLOCK_DIVIDER_MAX HPDI32_TCDR_DIV_MASK |
| |
| #define | HPDI32_TX_CLOCK_DIVIDER_DEFAULT 0x0 |
| |
| #define | HPDI32_TX_CLOCK_DIVIDER__GET(h, g) HPDI32_CONFIG_GET((h),HPDI32_TX_CLOCK_DIVIDER,0,(g)) |
| |
| #define | HPDI32_TX_CLOCK_DIVIDER__SET(h, s) HPDI32_CONFIG_SET((h),HPDI32_TX_CLOCK_DIVIDER,0,(s)) |
| |
| #define | HPDI32_TX_ENABLE_NO 0 |
| |
| #define | HPDI32_TX_ENABLE_YES 1 |
| |
| #define | HPDI32_TX_ENABLE_DEFAULT HPDI32_TX_ENABLE_NO |
| |
| #define | HPDI32_TX_ENABLE__GET(h, g) HPDI32_CONFIG_GET((h),HPDI32_TX_ENABLE,0,(g)) |
| |
| #define | HPDI32_TX_ENABLE__SET(h, s) HPDI32_CONFIG_SET((h),HPDI32_TX_ENABLE,0,(s)) |
| |
| #define | HPDI32_TX_ENABLE__RESET(h) HPDI32_CONFIG_SET((h),HPDI32_TX_ENABLE,0,HPDI32_TX_ENABLE_DEFAULT) |
| |
| #define | HPDI32_TX_ENABLE__NO(h) HPDI32_TX_ENABLE__SET((h),HPDI32_TX_ENABLE_NO) |
| |
| #define | HPDI32_TX_ENABLE__YES(h) HPDI32_TX_ENABLE__SET((h),HPDI32_TX_ENABLE_YES) |
| |
| #define | HPDI32_TX_FLOW_CONTROL_DISABLE 0 |
| |
| #define | HPDI32_TX_FLOW_CONTROL_ENABLE 1 |
| |
| #define | HPDI32_TX_FLOW_CONTROL_IGNORE GSC_NO_CHANGE |
| |
| #define | HPDI32_TX_FLOW_CONTROL_DEFAULT HPDI32_TX_FLOW_CONTROL_IGNORE |
| |
| #define | HPDI32_TX_FLOW_CONTROL__GET(h, g) HPDI32_CONFIG_GET((h),HPDI32_TX_FLOW_CONTROL,0,(g)) |
| |
| #define | HPDI32_TX_FLOW_CONTROL__SET(h, s) HPDI32_CONFIG_SET((h),HPDI32_TX_FLOW_CONTROL,0,(s)) |
| |
| #define | HPDI32_TX_FLOW_CONTROL__RESET(h) HPDI32_CONFIG_SET((h),HPDI32_TX_FLOW_CONTROL,0,HPDI32_TX_FLOW_CONTROL_DEFAULT) |
| |
| #define | HPDI32_TX_FLOW_CONTROL__STOP(h) HPDI32_TX_FLOW_CONTROL__SET((h),HPDI32_TX_FLOW_CONTROL_DISABLE) |
| |
| #define | HPDI32_TX_FLOW_CONTROL__START(h) HPDI32_TX_FLOW_CONTROL__SET((h),HPDI32_TX_FLOW_CONTROL_ENABLE) |
| |
| #define | HPDI32_TX_LINE_VALID_OFF_COUNT_DISABLE 0 |
| |
| #define | HPDI32_TX_LINE_VALID_OFF_COUNT_MAX HPDI32_TLILCR_COUNT_MASK |
| |
| #define | HPDI32_TX_LINE_VALID_OFF_COUNT_DEFAULT HPDI32_TX_LINE_VALID_OFF_COUNT_DISABLE |
| |
| #define | HPDI32_TX_LINE_VALID_OFF_COUNT__GET(h, g) HPDI32_CONFIG_GET((h),HPDI32_TX_LINE_VALID_OFF_COUNT,0,(g)) |
| |
| #define | HPDI32_TX_LINE_VALID_OFF_COUNT__SET(h, s) HPDI32_CONFIG_SET((h),HPDI32_TX_LINE_VALID_OFF_COUNT,0,(s)) |
| |
| #define | HPDI32_TX_LINE_VALID_OFF_COUNT__RESET(h) HPDI32_CONFIG_SET((h),HPDI32_TX_LINE_VALID_OFF_COUNT,0,HPDI32_TX_LINE_VALID_OFF_COUNT_DEFAULT) |
| |
| #define | HPDI32_TX_LINE_VALID_OFF_COUNT__DISABLE(h) HPDI32_TX_LINE_VALID_OFF_COUNT__SET((h),HPDI32_TX_LINE_VALID_OFF_COUNT_DISABLE) |
| |
| #define | HPDI32_TX_LINE_VALID_ON_COUNT_DISABLE 0 |
| |
| #define | HPDI32_TX_LINE_VALID_ON_COUNT_MAX 0xFFFFFFFFUL /* CONFLICTS WITH SPECIAL API VALUE!!! */ |
| |
| #define | HPDI32_TX_LINE_VALID_ON_COUNT_DEFAULT HPDI32_TX_LINE_VALID_ON_COUNT_DISABLE |
| |
| #define | HPDI32_TX_LINE_VALID_ON_COUNT__GET(h, g) HPDI32_CONFIG_GET((h),HPDI32_TX_LINE_VALID_ON_COUNT,0,(g)) |
| |
| #define | HPDI32_TX_LINE_VALID_ON_COUNT__SET(h, s) HPDI32_CONFIG_SET((h),HPDI32_TX_LINE_VALID_ON_COUNT,0,(s)) |
| |
| #define | HPDI32_TX_LINE_VALID_ON_COUNT__RESET(h) HPDI32_CONFIG_SET((h),HPDI32_TX_LINE_VALID_ON_COUNT,0,HPDI32_TX_LINE_VALID_ON_COUNT_DEFAULT) |
| |
| #define | HPDI32_TX_LINE_VALID_ON_COUNT__DISABLE(h) HPDI32_TX_LINE_VALID_ON_COUNT__SET((h),HPDI32_TX_LINE_VALID_ON_COUNT_DISABLE) |
| |
| #define | HPDI32_TX_OVERRUN_IGNORE 0 /* SET option */ |
| |
| #define | HPDI32_TX_OVERRUN_CLEAR 1 /* SET option */ |
| |
| #define | HPDI32_TX_OVERRUN_DEFAULT HPDI32_TX_OVERRUN_CLEAR |
| |
| #define | HPDI32_TX_OVERRUN_NO 0 /* GET option */ |
| |
| #define | HPDI32_TX_OVERRUN_YES 1 /* GET option */ |
| |
| #define | HPDI32_TX_OVERRUN__GET(h, g) HPDI32_CONFIG_GET((h),HPDI32_TX_OVERRUN,0,(g)) |
| |
| #define | HPDI32_TX_OVERRUN__SET(h, s) HPDI32_CONFIG_SET((h),HPDI32_TX_OVERRUN,0,(s)) |
| |
| #define | HPDI32_TX_OVERRUN__CLEAR(h) HPDI32_TX_OVERRUN__SET((h),HPDI32_TX_OVERRUN_CLEAR) |
| |
| #define | HPDI32_TX_REMOTE_THROTTLE_DISABLE 0 |
| |
| #define | HPDI32_TX_REMOTE_THROTTLE_ENABLE 1 |
| |
| #define | HPDI32_TX_REMOTE_THROTTLE_DEFAULT HPDI32_TX_REMOTE_THROTTLE_DISABLE |
| |
| #define | HPDI32_TX_REMOTE_THROTTLE__GET(h, g) HPDI32_CONFIG_GET((h),HPDI32_TX_REMOTE_THROTTLE,0,(g)) |
| |
| #define | HPDI32_TX_REMOTE_THROTTLE__SET(h, s) HPDI32_CONFIG_SET((h),HPDI32_TX_REMOTE_THROTTLE,0,(s)) |
| |
| #define | HPDI32_TX_REMOTE_THROTTLE__RESET(h) HPDI32_CONFIG_SET((h),HPDI32_TX_REMOTE_THROTTLE,0,HPDI32_TX_REMOTE_THROTTLE_DEFAULT) |
| |
| #define | HPDI32_TX_REMOTE_THROTTLE__DISABLE(h) HPDI32_TX_REMOTE_THROTTLE__SET((h),HPDI32_TX_REMOTE_THROTTLE_DISABLE) |
| |
| #define | HPDI32_TX_REMOTE_THROTTLE__ENABLE(h) HPDI32_TX_REMOTE_THROTTLE__SET((h),HPDI32_TX_REMOTE_THROTTLE_ENABLE) |
| |
| #define | HPDI32_TX_REMOTE_THROTTLE_STATE_INACTIVE 0 /* State GET option */ |
| |
| #define | HPDI32_TX_REMOTE_THROTTLE_STATE_ACTIVE 1 /* State GET option */ |
| |
| #define | HPDI32_TX_REMOTE_THROTTLE_STATE__GET(h, g) HPDI32_CONFIG_GET((h),HPDI32_TX_REMOTE_THROTTLE_STATE,0,(g)) |
| |
| #define | HPDI32_TX_STATE_INACTIVE 0 /* State GET option */ |
| |
| #define | HPDI32_TX_STATE_ACTIVE 1 /* State GET option */ |
| |
| #define | HPDI32_TX_STATE__GET(h, g) HPDI32_CONFIG_GET((h),HPDI32_TX_STATE,0,(g)) |
| |
| #define | HPDI32_TX_STATUS_VALID_COUNT_DISABLE 0 |
| |
| #define | HPDI32_TX_STATUS_VALID_COUNT_MAX 0xFFFFFFF0UL /* Less than max de to special API vale. */ |
| |
| #define | HPDI32_TX_STATUS_VALID_COUNT_DEFAULT HPDI32_TX_STATUS_VALID_COUNT_DISABLE |
| |
| #define | HPDI32_TX_STATUS_VALID_COUNT__GET(h, g) HPDI32_CONFIG_GET((h),HPDI32_TX_STATUS_VALID_COUNT,0,(g)) |
| |
| #define | HPDI32_TX_STATUS_VALID_COUNT__SET(h, s) HPDI32_CONFIG_SET((h),HPDI32_TX_STATUS_VALID_COUNT,0,(s)) |
| |
| #define | HPDI32_TX_STATUS_VALID_COUNT__RESET(h) HPDI32_CONFIG_SET((h),HPDI32_TX_STATUS_VALID_COUNT,0,HPDI32_TX_STATUS_VALID_COUNT_DEFAULT) |
| |
| #define | HPDI32_TX_STATUS_VALID_COUNT__DISABLE(h) HPDI32_TX_STATUS_VALID_COUNT__SET((h),HPDI32_TX_STATUS_VALID_COUNT_DISABLE) |
| |
| #define | HPDI32_TX_STATUS_VALID_MIRROR_DISABLE 0 |
| |
| #define | HPDI32_TX_STATUS_VALID_MIRROR_ENABLE 1 |
| |
| #define | HPDI32_TX_STATUS_VALID_MIRROR_DEFAULT HPDI32_TX_STATUS_VALID_MIRROR_DISABLE |
| |
| #define | HPDI32_TX_STATUS_VALID_MIRROR__GET(h, g) HPDI32_CONFIG_GET((h),HPDI32_TX_STATUS_VALID_MIRROR,0,(g)) |
| |
| #define | HPDI32_TX_STATUS_VALID_MIRROR__SET(h, s) HPDI32_CONFIG_SET((h),HPDI32_TX_STATUS_VALID_MIRROR,0,(s)) |
| |
| #define | HPDI32_TX_STATUS_VALID_MIRROR__RESET(h) HPDI32_CONFIG_SET((h),HPDI32_TX_STATUS_VALID_MIRROR,0,HPDI32_TX_STATUS_VALID_MIRROR_DEFAULT) |
| |
| #define | HPDI32_TX_STATUS_VALID_MIRROR__DISABLE(h) HPDI32_TX_STATUS_VALID_MIRROR__SET((h),HPDI32_TX_STATUS_VALID_MIRROR_DISABLE) |
| |
| #define | HPDI32_TX_STATUS_VALID_MIRROR__ENABLE(h) HPDI32_TX_STATUS_VALID_MIRROR__SET((h),HPDI32_TX_STATUS_VALID_MIRROR_ENABLE) |
| |
| #define | HPDI32_VERSION_GET_LIBRARY(h, b, s) hpdi32_version_get((h),GSC_VERSION_LIBRARY,(b),(s)) |
| |
| #define | HPDI32_VERSION_GET_DRIVER(h, b, s) hpdi32_version_get((h),GSC_VERSION_DRIVER,(b),(s)) |
| |
