#include <asm/types.h>
#include <linux/ioctl.h>
#include <linux/types.h>
#include "gsc_common.h"
#include "gsc_pci9080.h"
#include "gsc_pci9656.h"

Include dependency graph for hpdi32.h:

Macros
#define	HPDI32_BASE_NAME "hpdi32"

#define	HPDI32_DEV_BASE_NAME "/dev/" HPDI32_BASE_NAME

#define	HPDI32_IOCTL_REG_READ _IOWR(GSC_IOCTL, 0, gsc_reg_t)

#define	HPDI32_IOCTL_REG_WRITE _IOWR(GSC_IOCTL, 1, gsc_reg_t)

#define	HPDI32_IOCTL_REG_MOD _IOWR(GSC_IOCTL, 2, gsc_reg_t)

#define	HPDI32_IOCTL_QUERY _IOWR(GSC_IOCTL, 3, __s32)

#define	HPDI32_IOCTL_INITIALIZE _IO (GSC_IOCTL, 4)

#define	HPDI32_IOCTL_CABLE_CMD_MODE_0 _IOWR(GSC_IOCTL, 5, __s32)

#define	HPDI32_IOCTL_CABLE_CMD_MODE_1 _IOWR(GSC_IOCTL, 6, __s32)

#define	HPDI32_IOCTL_CABLE_CMD_MODE_2 _IOWR(GSC_IOCTL, 7, __s32)

#define	HPDI32_IOCTL_CABLE_CMD_MODE_3 _IOWR(GSC_IOCTL, 8, __s32)

#define	HPDI32_IOCTL_CABLE_CMD_MODE_4 _IOWR(GSC_IOCTL, 9, __s32)

#define	HPDI32_IOCTL_CABLE_CMD_MODE_5 _IOWR(GSC_IOCTL, 10, __s32)

#define	HPDI32_IOCTL_CABLE_CMD_MODE_6 _IOWR(GSC_IOCTL, 11, __s32)

#define	HPDI32_IOCTL_CABLE_CMD_STATE_0 _IOWR(GSC_IOCTL, 12, __s32)

#define	HPDI32_IOCTL_CABLE_CMD_STATE_1 _IOWR(GSC_IOCTL, 13, __s32)

#define	HPDI32_IOCTL_CABLE_CMD_STATE_2 _IOWR(GSC_IOCTL, 14, __s32)

#define	HPDI32_IOCTL_CABLE_CMD_STATE_3 _IOWR(GSC_IOCTL, 15, __s32)

#define	HPDI32_IOCTL_CABLE_CMD_STATE_4 _IOWR(GSC_IOCTL, 16, __s32)

#define	HPDI32_IOCTL_CABLE_CMD_STATE_5 _IOWR(GSC_IOCTL, 17, __s32)

#define	HPDI32_IOCTL_CABLE_CMD_STATE_6 _IOWR(GSC_IOCTL, 18, __s32)

#define	HPDI32_IOCTL_RX_AUTO_START _IOWR(GSC_IOCTL, 19, __s32)

#define	HPDI32_IOCTL_RX_ENABLE _IOWR(GSC_IOCTL, 20, __s32)

#define	HPDI32_IOCTL_RX_LINE_COUNT _IOR (GSC_IOCTL, 21, __u32)

#define	HPDI32_IOCTL_RX_STATUS_COUNT _IOR (GSC_IOCTL, 22, __u32)

#define	HPDI32_IOCTL_RX_FIFO_AE _IOWR(GSC_IOCTL, 23, __s32)

#define	HPDI32_IOCTL_RX_FIFO_AF _IOWR(GSC_IOCTL, 24, __s32)

#define	HPDI32_IOCTL_RX_FIFO_OVERRUN _IOWR(GSC_IOCTL, 25, __s32)

#define	HPDI32_IOCTL_RX_FIFO_RESET _IO (GSC_IOCTL, 26)

#define	HPDI32_IOCTL_RX_FIFO_STATUS _IOR (GSC_IOCTL, 27, __s32)

#define	HPDI32_IOCTL_RX_FIFO_UNDERRUN _IOWR(GSC_IOCTL, 28, __s32)

#define	HPDI32_IOCTL_RX_IO_ABORT _IOR (GSC_IOCTL, 29, __s32)

#define	HPDI32_IOCTL_RX_IO_DATA_SIZE _IOWR(GSC_IOCTL, 30, __s32)

#define	HPDI32_IOCTL_RX_IO_MODE _IOWR(GSC_IOCTL, 31, __s32)

#define	HPDI32_IOCTL_RX_IO_OVERRUN _IOWR(GSC_IOCTL, 32, __s32)

#define	HPDI32_IOCTL_RX_IO_PIO_THRESHOLD _IOWR(GSC_IOCTL, 33, __s32)

#define	HPDI32_IOCTL_RX_IO_TIMEOUT _IOWR(GSC_IOCTL, 34, __s32)

#define	HPDI32_IOCTL_RX_IO_UNDERRUN _IOWR(GSC_IOCTL, 35, __s32)

#define	HPDI32_IOCTL_TX_AUTO_START _IOWR(GSC_IOCTL, 36, __s32)

#define	HPDI32_IOCTL_TX_AUTO_STOP _IOWR(GSC_IOCTL, 37, __s32)

#define	HPDI32_IOCTL_TX_CLOCK_DIVIDER _IOWR(GSC_IOCTL, 38, __s32)

#define	HPDI32_IOCTL_TX_ENABLE _IOWR(GSC_IOCTL, 39, __s32)

#define	HPDI32_IOCTL_TX_FLOW_CONTROL _IOWR(GSC_IOCTL, 40, __s32)

#define	HPDI32_IOCTL_TX_LINE_VAL_OFF_CNT _IOWR(GSC_IOCTL, 41, __s32)

#define	HPDI32_IOCTL_TX_LINE_VAL_ON_CNT _IOWR(GSC_IOCTL, 42, __s32)

#define	HPDI32_IOCTL_TX_REMOTE_THROTTLE _IOWR(GSC_IOCTL, 43, __s32)

#define	HPDI32_IOCTL_TX_STATUS_VAL_CNT _IOWR(GSC_IOCTL, 44, __s32)

#define	HPDI32_IOCTL_TX_STATUS_VAL_MIR _IOWR(GSC_IOCTL, 45, __s32)

#define	HPDI32_IOCTL_TX_FIFO_AE _IOWR(GSC_IOCTL, 46, __s32)

#define	HPDI32_IOCTL_TX_FIFO_AF _IOWR(GSC_IOCTL, 47, __s32)

#define	HPDI32_IOCTL_TX_FIFO_OVERRUN _IOWR(GSC_IOCTL, 48, __s32)

#define	HPDI32_IOCTL_TX_FIFO_RESET _IO (GSC_IOCTL, 49)

#define	HPDI32_IOCTL_TX_FIFO_STATUS _IOR (GSC_IOCTL, 50, __s32)

#define	HPDI32_IOCTL_TX_IO_ABORT _IOR (GSC_IOCTL, 51, __s32)

#define	HPDI32_IOCTL_TX_IO_DATA_SIZE _IOWR(GSC_IOCTL, 52, __s32)

#define	HPDI32_IOCTL_TX_IO_MODE _IOWR(GSC_IOCTL, 53, __s32)

#define	HPDI32_IOCTL_TX_IO_PIO_THRESHOLD _IOWR(GSC_IOCTL, 54, __s32)

#define	HPDI32_IOCTL_TX_IO_OVERRUN _IOWR(GSC_IOCTL, 55, __s32)

#define	HPDI32_IOCTL_TX_IO_TIMEOUT _IOWR(GSC_IOCTL, 56, __s32)

#define	HPDI32_IOCTL_IRQ_CONFIG_EDGE _IOWR(GSC_IOCTL, 57, __s32)

#define	HPDI32_IOCTL_IRQ_CONFIG_HIGH _IOWR(GSC_IOCTL, 58, __s32)

#define	HPDI32_IOCTL_IRQ_ENABLE _IOWR(GSC_IOCTL, 59, __s32)

#define	HPDI32_IOCTL_TRISTATE_TE_RE _IOWR(GSC_IOCTL, 60, __s32)

#define	HPDI32_IOCTL_USER_JUMPERS _IOR (GSC_IOCTL, 61, __s32)

#define	HPDI32_IOCTL_WAIT_EVENT _IOWR(GSC_IOCTL, 62, gsc_wait_t)

#define	HPDI32_IOCTL_WAIT_CANCEL _IOWR(GSC_IOCTL, 63, gsc_wait_t)

#define	HPDI32_IOCTL_WAIT_STATUS _IOWR(GSC_IOCTL, 64, gsc_wait_t)

#define	HPDI32_GSC_FRR GSC_REG_ENCODE(GSC_REG_GSC, 4, 0x00)

#define	HPDI32_GSC_BCR GSC_REG_ENCODE(GSC_REG_GSC, 4, 0x04)

#define	HPDI32_GSC_BSR GSC_REG_ENCODE(GSC_REG_GSC, 4, 0x08)

#define	HPDI32_GSC_TAR GSC_REG_ENCODE(GSC_REG_GSC, 4, 0x0C)

#define	HPDI32_GSC_RAR GSC_REG_ENCODE(GSC_REG_GSC, 4, 0x10)

#define	HPDI32_GSC_FSR GSC_REG_ENCODE(GSC_REG_GSC, 4, 0x14)

#define	HPDI32_GSC_FDR GSC_REG_ENCODE(GSC_REG_GSC, 4, 0x18)

#define	HPDI32_GSC_TSVLCR GSC_REG_ENCODE(GSC_REG_GSC, 4, 0x1C)

#define	HPDI32_GSC_TLVLCR GSC_REG_ENCODE(GSC_REG_GSC, 4, 0x20)

#define	HPDI32_GSC_TLILCR GSC_REG_ENCODE(GSC_REG_GSC, 4, 0x24)

#define	HPDI32_GSC_RSCR GSC_REG_ENCODE(GSC_REG_GSC, 4, 0x28)

#define	HPDI32_GSC_RLCR GSC_REG_ENCODE(GSC_REG_GSC, 4, 0x2C)

#define	HPDI32_GSC_ICR GSC_REG_ENCODE(GSC_REG_GSC, 4, 0x30)

#define	HPDI32_GSC_ISR GSC_REG_ENCODE(GSC_REG_GSC, 4, 0x34)

#define	HPDI32_GSC_TCDR GSC_REG_ENCODE(GSC_REG_GSC, 4, 0x38)

#define	HPDI32_GSC_TFSR GSC_REG_ENCODE(GSC_REG_GSC, 4, 0x40)

#define	HPDI32_GSC_RFSR GSC_REG_ENCODE(GSC_REG_GSC, 4, 0x44)

#define	HPDI32_GSC_TFWR GSC_REG_ENCODE(GSC_REG_GSC, 4, 0x48)

#define	HPDI32_GSC_RFWR GSC_REG_ENCODE(GSC_REG_GSC, 4, 0x4C)

#define	HPDI32_GSC_IELR GSC_REG_ENCODE(GSC_REG_GSC, 4, 0x50)

#define	HPDI32_GSC_IHLR GSC_REG_ENCODE(GSC_REG_GSC, 4, 0x54)

#define	HPDI32_IOCTL_QUERY_ERROR (-1)

#define	HPDI32_QUERY_FF_UNKNOWN 0

#define	HPDI32_QUERY_FF_PCI 1

#define	HPDI32_QUERY_FF_PMC 2

#define	HPDI32_QUERY_FF_CPCI 3

#define	HPDI32_QUERY_FF_PC104P 4

#define	HPDI32_QUERY_XCVR_UNKNOWN 0

#define	HPDI32_QUERY_XCVR_PECL 1

#define	HPDI32_QUERY_XCVR_RS485 2

#define	HPDI32_CABLE_CMD_MODE_FC 0x000

#define	HPDI32_CABLE_CMD_MODE_IN 0x100

#define	HPDI32_CABLE_CMD_MODE_OUT_LO 0x001

#define	HPDI32_CABLE_CMD_MODE_OUT_HI 0x101

#define	HPDI32_CABLE_CMD_STATE_0 0

#define	HPDI32_CABLE_CMD_STATE_1 1

#define	HPDI32_AUTO_START_NO 0

#define	HPDI32_AUTO_START_YES 1

#define	HPDI32_AUTO_START_DEFAULT HPDI32_AUTO_START_YES

#define	HPDI32_RX_ENABLE_NO 0

#define	HPDI32_RX_ENABLE_YES 1

#define	HPDI32_FIFO_ERROR_CLEAR 1

#define	HPDI32_FIFO_ERROR_TEST (-1)

#define	HPDI32_FIFO_ERROR_NO 0

#define	HPDI32_FIFO_ERROR_YES 1

#define	HPDI32_FIFO_STATUS_EMPTY 0

#define	HPDI32_FIFO_STATUS_ALMOST_EMPTY 1

#define	HPDI32_FIFO_STATUS_MEDIUM 2

#define	HPDI32_FIFO_STATUS_ALMOST_FULL 3

#define	HPDI32_FIFO_STATUS_FULL 4

#define	HPDI32_IO_ABORT_NO 0

#define	HPDI32_IO_ABORT_YES 1

#define	HPDI32_IO_DATA_SIZE_8_BITS 8

#define	HPDI32_IO_DATA_SIZE_16_BITS 16

#define	HPDI32_IO_DATA_SIZE_32_BITS 32

#define	HPDI32_IO_DATA_SIZE_BITS_DEFAULT HPDI32_IO_DATA_SIZE_32_BITS

#define	HPDI32_IO_MODE_DEFAULT GSC_IO_MODE_DMDMA

#define	HPDI32_IO_ERROR_IGNORE 0

#define	HPDI32_IO_ERROR_CHECK 1

#define	HPDI32_IO_ERROR_DEFAULT HPDI32_IO_ERROR_CHECK

#define	HPDI32_IO_PIO_THRESHOLD_DEFAULT 32

#define	HPDI32_IO_TIMEOUT_NO_SLEEP 0

#define	HPDI32_IO_TIMEOUT_MIN 0

#define	HPDI32_IO_TIMEOUT_MAX 3600

#define	HPDI32_IO_TIMEOUT_DEFAULT 10

#define	HPDI32_AUTO_STOP_NO 1

#define	HPDI32_AUTO_STOP_YES 0

#define	HPDI32_TX_ENABLE_NO 0

#define	HPDI32_TX_ENABLE_YES 1

#define	HPDI32_TX_FLOW_CONTROL_STOP 0

#define	HPDI32_TX_FLOW_CONTROL_START 1

#define	HPDI32_TX_REMOTE_THROTTLE_NO 0

#define	HPDI32_TX_REMOTE_THROTTLE_YES 1

#define	HPDI32_TX_STATUS_VAL_MIR_NO 0

#define	HPDI32_TX_STATUS_VAL_MIR_YES 1

#define	HPDI32_IRQ_CC0_FV_S_GPIO6 0x00000001

#define	HPDI32_IRQ_CC0_FV_E_GPIO6 0x00000002

#define	HPDI32_IRQ_CC1_LV_GPIO0 0x00000004

#define	HPDI32_IRQ_CC2_SV_GPIO1 0x00000008

#define	HPDI32_IRQ_CC3_RR_GPIO2 0x00000010

#define	HPDI32_IRQ_CC4_TR_GPIO3 0x00000020

#define	HPDI32_IRQ_CC5_TE_GPIO4 0x00000040

#define	HPDI32_IRQ_CC6_RE_GPIO5 0x00000080

#define	HPDI32_IRQ_TX_FIFO_EMPTY 0x00000100

#define	HPDI32_IRQ_TX_FIFO_AE 0x00000200

#define	HPDI32_IRQ_TX_FIFO_AF 0x00000400

#define	HPDI32_IRQ_TX_FIFO_FULL 0x00000800

#define	HPDI32_IRQ_RX_FIFO_EMPTY 0x00001000

#define	HPDI32_IRQ_RX_FIFO_AE 0x00002000

#define	HPDI32_IRQ_RX_FIFO_AF 0x00004000

#define	HPDI32_IRQ_RX_FIFO_FULL 0x00008000

#define	HPDI32_IRQ_ALL 0x0000FFFF

#define	HPDI32_TRISTATE_TE_RE_NO 0

#define	HPDI32_TRISTATE_TE_RE_YES 1

#define	HPDI32_WAIT_GSC_CC0_FV_S_GPIO6 HPDI32_IRQ_CC0_FV_S_GPIO6

#define	HPDI32_WAIT_GSC_CC0_FV_E_GPIO6 HPDI32_IRQ_CC0_FV_E_GPIO6

#define	HPDI32_WAIT_GSC_CC1_LV_GPIO0 HPDI32_IRQ_CC1_LV_GPIO0

#define	HPDI32_WAIT_GSC_CC2_SV_GPIO1 HPDI32_IRQ_CC2_SV_GPIO1

#define	HPDI32_WAIT_GSC_CC3_RR_GPIO2 HPDI32_IRQ_CC3_RR_GPIO2

#define	HPDI32_WAIT_GSC_CC4_TR_GPIO3 HPDI32_IRQ_CC4_TR_GPIO3

#define	HPDI32_WAIT_GSC_CC5_TE_GPIO4 HPDI32_IRQ_CC5_TE_GPIO4

#define	HPDI32_WAIT_GSC_CC6_RE_GPIO5 HPDI32_IRQ_CC6_RE_GPIO5

#define	HPDI32_WAIT_GSC_TX_FIFO_EMPTY HPDI32_IRQ_TX_FIFO_EMPTY

#define	HPDI32_WAIT_GSC_TX_FIFO_AE HPDI32_IRQ_TX_FIFO_AE

#define	HPDI32_WAIT_GSC_TX_FIFO_AF HPDI32_IRQ_TX_FIFO_AF

#define	HPDI32_WAIT_GSC_TX_FIFO_FULL HPDI32_IRQ_TX_FIFO_FULL

#define	HPDI32_WAIT_GSC_RX_FIFO_EMPTY HPDI32_IRQ_RX_FIFO_EMPTY

#define	HPDI32_WAIT_GSC_RX_FIFO_AE HPDI32_IRQ_RX_FIFO_AE

#define	HPDI32_WAIT_GSC_RX_FIFO_AF HPDI32_IRQ_RX_FIFO_AF

#define	HPDI32_WAIT_GSC_RX_FIFO_FULL HPDI32_IRQ_RX_FIFO_FULL

#define	HPDI32_WAIT_GSC_ALL HPDI32_IRQ_ALL

#define	HPDI32_WAIT_ALT_ALL 0x0000

Macro Definition Documentation

◆ HPDI32_AUTO_START_DEFAULT

#define HPDI32_AUTO_START_DEFAULT HPDI32_AUTO_START_YES

◆ HPDI32_AUTO_START_NO

#define HPDI32_AUTO_START_NO 0

◆ HPDI32_AUTO_START_YES

#define HPDI32_AUTO_START_YES 1

◆ HPDI32_AUTO_STOP_NO

#define HPDI32_AUTO_STOP_NO 1

◆ HPDI32_AUTO_STOP_YES

#define HPDI32_AUTO_STOP_YES 0

◆ HPDI32_BASE_NAME

#define HPDI32_BASE_NAME "hpdi32"

◆ HPDI32_CABLE_CMD_MODE_FC

#define HPDI32_CABLE_CMD_MODE_FC 0x000

◆ HPDI32_CABLE_CMD_MODE_IN

#define HPDI32_CABLE_CMD_MODE_IN 0x100

◆ HPDI32_CABLE_CMD_MODE_OUT_HI

#define HPDI32_CABLE_CMD_MODE_OUT_HI 0x101

◆ HPDI32_CABLE_CMD_MODE_OUT_LO

#define HPDI32_CABLE_CMD_MODE_OUT_LO 0x001

◆ HPDI32_CABLE_CMD_STATE_0

#define HPDI32_CABLE_CMD_STATE_0 0

◆ HPDI32_CABLE_CMD_STATE_1

#define HPDI32_CABLE_CMD_STATE_1 1

◆ HPDI32_DEV_BASE_NAME

#define HPDI32_DEV_BASE_NAME "/dev/" HPDI32_BASE_NAME

◆ HPDI32_FIFO_ERROR_CLEAR

#define HPDI32_FIFO_ERROR_CLEAR 1

◆ HPDI32_FIFO_ERROR_NO

#define HPDI32_FIFO_ERROR_NO 0

◆ HPDI32_FIFO_ERROR_TEST

#define HPDI32_FIFO_ERROR_TEST (-1)

◆ HPDI32_FIFO_ERROR_YES

#define HPDI32_FIFO_ERROR_YES 1

◆ HPDI32_FIFO_STATUS_ALMOST_EMPTY

#define HPDI32_FIFO_STATUS_ALMOST_EMPTY 1

◆ HPDI32_FIFO_STATUS_ALMOST_FULL

#define HPDI32_FIFO_STATUS_ALMOST_FULL 3

◆ HPDI32_FIFO_STATUS_EMPTY

#define HPDI32_FIFO_STATUS_EMPTY 0

◆ HPDI32_FIFO_STATUS_FULL

#define HPDI32_FIFO_STATUS_FULL 4

◆ HPDI32_FIFO_STATUS_MEDIUM

#define HPDI32_FIFO_STATUS_MEDIUM 2

◆ HPDI32_GSC_BCR

#define HPDI32_GSC_BCR GSC_REG_ENCODE(GSC_REG_GSC, 4, 0x04)

◆ HPDI32_GSC_BSR

#define HPDI32_GSC_BSR GSC_REG_ENCODE(GSC_REG_GSC, 4, 0x08)

◆ HPDI32_GSC_FDR

#define HPDI32_GSC_FDR GSC_REG_ENCODE(GSC_REG_GSC, 4, 0x18)

◆ HPDI32_GSC_FRR

#define HPDI32_GSC_FRR GSC_REG_ENCODE(GSC_REG_GSC, 4, 0x00)

◆ HPDI32_GSC_FSR

#define HPDI32_GSC_FSR GSC_REG_ENCODE(GSC_REG_GSC, 4, 0x14)

◆ HPDI32_GSC_ICR

#define HPDI32_GSC_ICR GSC_REG_ENCODE(GSC_REG_GSC, 4, 0x30)

◆ HPDI32_GSC_IELR

#define HPDI32_GSC_IELR GSC_REG_ENCODE(GSC_REG_GSC, 4, 0x50)

◆ HPDI32_GSC_IHLR

#define HPDI32_GSC_IHLR GSC_REG_ENCODE(GSC_REG_GSC, 4, 0x54)

◆ HPDI32_GSC_ISR

#define HPDI32_GSC_ISR GSC_REG_ENCODE(GSC_REG_GSC, 4, 0x34)

◆ HPDI32_GSC_RAR

#define HPDI32_GSC_RAR GSC_REG_ENCODE(GSC_REG_GSC, 4, 0x10)

◆ HPDI32_GSC_RFSR

#define HPDI32_GSC_RFSR GSC_REG_ENCODE(GSC_REG_GSC, 4, 0x44)

◆ HPDI32_GSC_RFWR

#define HPDI32_GSC_RFWR GSC_REG_ENCODE(GSC_REG_GSC, 4, 0x4C)

◆ HPDI32_GSC_RLCR

#define HPDI32_GSC_RLCR GSC_REG_ENCODE(GSC_REG_GSC, 4, 0x2C)

◆ HPDI32_GSC_RSCR

#define HPDI32_GSC_RSCR GSC_REG_ENCODE(GSC_REG_GSC, 4, 0x28)

◆ HPDI32_GSC_TAR

#define HPDI32_GSC_TAR GSC_REG_ENCODE(GSC_REG_GSC, 4, 0x0C)

◆ HPDI32_GSC_TCDR

#define HPDI32_GSC_TCDR GSC_REG_ENCODE(GSC_REG_GSC, 4, 0x38)

◆ HPDI32_GSC_TFSR

#define HPDI32_GSC_TFSR GSC_REG_ENCODE(GSC_REG_GSC, 4, 0x40)

◆ HPDI32_GSC_TFWR

#define HPDI32_GSC_TFWR GSC_REG_ENCODE(GSC_REG_GSC, 4, 0x48)

◆ HPDI32_GSC_TLILCR

#define HPDI32_GSC_TLILCR GSC_REG_ENCODE(GSC_REG_GSC, 4, 0x24)

◆ HPDI32_GSC_TLVLCR

#define HPDI32_GSC_TLVLCR GSC_REG_ENCODE(GSC_REG_GSC, 4, 0x20)

◆ HPDI32_GSC_TSVLCR

#define HPDI32_GSC_TSVLCR GSC_REG_ENCODE(GSC_REG_GSC, 4, 0x1C)

◆ HPDI32_IO_ABORT_NO

#define HPDI32_IO_ABORT_NO 0

◆ HPDI32_IO_ABORT_YES

#define HPDI32_IO_ABORT_YES 1

◆ HPDI32_IO_DATA_SIZE_16_BITS

#define HPDI32_IO_DATA_SIZE_16_BITS 16

◆ HPDI32_IO_DATA_SIZE_32_BITS

#define HPDI32_IO_DATA_SIZE_32_BITS 32

◆ HPDI32_IO_DATA_SIZE_8_BITS

#define HPDI32_IO_DATA_SIZE_8_BITS 8

◆ HPDI32_IO_DATA_SIZE_BITS_DEFAULT

#define HPDI32_IO_DATA_SIZE_BITS_DEFAULT HPDI32_IO_DATA_SIZE_32_BITS

◆ HPDI32_IO_ERROR_CHECK

#define HPDI32_IO_ERROR_CHECK 1

◆ HPDI32_IO_ERROR_DEFAULT

#define HPDI32_IO_ERROR_DEFAULT HPDI32_IO_ERROR_CHECK

◆ HPDI32_IO_ERROR_IGNORE

#define HPDI32_IO_ERROR_IGNORE 0

◆ HPDI32_IO_MODE_DEFAULT

#define HPDI32_IO_MODE_DEFAULT GSC_IO_MODE_DMDMA

◆ HPDI32_IO_PIO_THRESHOLD_DEFAULT

#define HPDI32_IO_PIO_THRESHOLD_DEFAULT 32

◆ HPDI32_IO_TIMEOUT_DEFAULT

#define HPDI32_IO_TIMEOUT_DEFAULT 10

◆ HPDI32_IO_TIMEOUT_MAX

#define HPDI32_IO_TIMEOUT_MAX 3600

◆ HPDI32_IO_TIMEOUT_MIN

#define HPDI32_IO_TIMEOUT_MIN 0

◆ HPDI32_IO_TIMEOUT_NO_SLEEP

#define HPDI32_IO_TIMEOUT_NO_SLEEP 0

◆ HPDI32_IOCTL_CABLE_CMD_MODE_0

#define HPDI32_IOCTL_CABLE_CMD_MODE_0 _IOWR(GSC_IOCTL, 5, __s32)

◆ HPDI32_IOCTL_CABLE_CMD_MODE_1

#define HPDI32_IOCTL_CABLE_CMD_MODE_1 _IOWR(GSC_IOCTL, 6, __s32)

◆ HPDI32_IOCTL_CABLE_CMD_MODE_2

#define HPDI32_IOCTL_CABLE_CMD_MODE_2 _IOWR(GSC_IOCTL, 7, __s32)

◆ HPDI32_IOCTL_CABLE_CMD_MODE_3

#define HPDI32_IOCTL_CABLE_CMD_MODE_3 _IOWR(GSC_IOCTL, 8, __s32)

◆ HPDI32_IOCTL_CABLE_CMD_MODE_4

#define HPDI32_IOCTL_CABLE_CMD_MODE_4 _IOWR(GSC_IOCTL, 9, __s32)

◆ HPDI32_IOCTL_CABLE_CMD_MODE_5

#define HPDI32_IOCTL_CABLE_CMD_MODE_5 _IOWR(GSC_IOCTL, 10, __s32)

◆ HPDI32_IOCTL_CABLE_CMD_MODE_6

#define HPDI32_IOCTL_CABLE_CMD_MODE_6 _IOWR(GSC_IOCTL, 11, __s32)

◆ HPDI32_IOCTL_CABLE_CMD_STATE_0

#define HPDI32_IOCTL_CABLE_CMD_STATE_0 _IOWR(GSC_IOCTL, 12, __s32)

◆ HPDI32_IOCTL_CABLE_CMD_STATE_1

#define HPDI32_IOCTL_CABLE_CMD_STATE_1 _IOWR(GSC_IOCTL, 13, __s32)

◆ HPDI32_IOCTL_CABLE_CMD_STATE_2

#define HPDI32_IOCTL_CABLE_CMD_STATE_2 _IOWR(GSC_IOCTL, 14, __s32)

◆ HPDI32_IOCTL_CABLE_CMD_STATE_3

#define HPDI32_IOCTL_CABLE_CMD_STATE_3 _IOWR(GSC_IOCTL, 15, __s32)

◆ HPDI32_IOCTL_CABLE_CMD_STATE_4

#define HPDI32_IOCTL_CABLE_CMD_STATE_4 _IOWR(GSC_IOCTL, 16, __s32)

◆ HPDI32_IOCTL_CABLE_CMD_STATE_5

#define HPDI32_IOCTL_CABLE_CMD_STATE_5 _IOWR(GSC_IOCTL, 17, __s32)

◆ HPDI32_IOCTL_CABLE_CMD_STATE_6

#define HPDI32_IOCTL_CABLE_CMD_STATE_6 _IOWR(GSC_IOCTL, 18, __s32)

◆ HPDI32_IOCTL_INITIALIZE

#define HPDI32_IOCTL_INITIALIZE _IO (GSC_IOCTL, 4)

◆ HPDI32_IOCTL_IRQ_CONFIG_EDGE

#define HPDI32_IOCTL_IRQ_CONFIG_EDGE _IOWR(GSC_IOCTL, 57, __s32)

◆ HPDI32_IOCTL_IRQ_CONFIG_HIGH

#define HPDI32_IOCTL_IRQ_CONFIG_HIGH _IOWR(GSC_IOCTL, 58, __s32)

◆ HPDI32_IOCTL_IRQ_ENABLE

#define HPDI32_IOCTL_IRQ_ENABLE _IOWR(GSC_IOCTL, 59, __s32)

◆ HPDI32_IOCTL_QUERY

#define HPDI32_IOCTL_QUERY _IOWR(GSC_IOCTL, 3, __s32)

◆ HPDI32_IOCTL_QUERY_ERROR

#define HPDI32_IOCTL_QUERY_ERROR (-1)

◆ HPDI32_IOCTL_REG_MOD

#define HPDI32_IOCTL_REG_MOD _IOWR(GSC_IOCTL, 2, gsc_reg_t)

◆ HPDI32_IOCTL_REG_READ

#define HPDI32_IOCTL_REG_READ _IOWR(GSC_IOCTL, 0, gsc_reg_t)

◆ HPDI32_IOCTL_REG_WRITE

#define HPDI32_IOCTL_REG_WRITE _IOWR(GSC_IOCTL, 1, gsc_reg_t)

◆ HPDI32_IOCTL_RX_AUTO_START

#define HPDI32_IOCTL_RX_AUTO_START _IOWR(GSC_IOCTL, 19, __s32)

◆ HPDI32_IOCTL_RX_ENABLE

#define HPDI32_IOCTL_RX_ENABLE _IOWR(GSC_IOCTL, 20, __s32)

◆ HPDI32_IOCTL_RX_FIFO_AE

#define HPDI32_IOCTL_RX_FIFO_AE _IOWR(GSC_IOCTL, 23, __s32)

◆ HPDI32_IOCTL_RX_FIFO_AF

#define HPDI32_IOCTL_RX_FIFO_AF _IOWR(GSC_IOCTL, 24, __s32)

◆ HPDI32_IOCTL_RX_FIFO_OVERRUN

#define HPDI32_IOCTL_RX_FIFO_OVERRUN _IOWR(GSC_IOCTL, 25, __s32)

◆ HPDI32_IOCTL_RX_FIFO_RESET

#define HPDI32_IOCTL_RX_FIFO_RESET _IO (GSC_IOCTL, 26)

◆ HPDI32_IOCTL_RX_FIFO_STATUS

#define HPDI32_IOCTL_RX_FIFO_STATUS _IOR (GSC_IOCTL, 27, __s32)

◆ HPDI32_IOCTL_RX_FIFO_UNDERRUN

#define HPDI32_IOCTL_RX_FIFO_UNDERRUN _IOWR(GSC_IOCTL, 28, __s32)

◆ HPDI32_IOCTL_RX_IO_ABORT

#define HPDI32_IOCTL_RX_IO_ABORT _IOR (GSC_IOCTL, 29, __s32)

◆ HPDI32_IOCTL_RX_IO_DATA_SIZE

#define HPDI32_IOCTL_RX_IO_DATA_SIZE _IOWR(GSC_IOCTL, 30, __s32)

◆ HPDI32_IOCTL_RX_IO_MODE

#define HPDI32_IOCTL_RX_IO_MODE _IOWR(GSC_IOCTL, 31, __s32)

◆ HPDI32_IOCTL_RX_IO_OVERRUN

#define HPDI32_IOCTL_RX_IO_OVERRUN _IOWR(GSC_IOCTL, 32, __s32)

◆ HPDI32_IOCTL_RX_IO_PIO_THRESHOLD

#define HPDI32_IOCTL_RX_IO_PIO_THRESHOLD _IOWR(GSC_IOCTL, 33, __s32)

◆ HPDI32_IOCTL_RX_IO_TIMEOUT

#define HPDI32_IOCTL_RX_IO_TIMEOUT _IOWR(GSC_IOCTL, 34, __s32)

◆ HPDI32_IOCTL_RX_IO_UNDERRUN

#define HPDI32_IOCTL_RX_IO_UNDERRUN _IOWR(GSC_IOCTL, 35, __s32)

◆ HPDI32_IOCTL_RX_LINE_COUNT

#define HPDI32_IOCTL_RX_LINE_COUNT _IOR (GSC_IOCTL, 21, __u32)

◆ HPDI32_IOCTL_RX_STATUS_COUNT

#define HPDI32_IOCTL_RX_STATUS_COUNT _IOR (GSC_IOCTL, 22, __u32)

◆ HPDI32_IOCTL_TRISTATE_TE_RE

#define HPDI32_IOCTL_TRISTATE_TE_RE _IOWR(GSC_IOCTL, 60, __s32)

◆ HPDI32_IOCTL_TX_AUTO_START

#define HPDI32_IOCTL_TX_AUTO_START _IOWR(GSC_IOCTL, 36, __s32)

◆ HPDI32_IOCTL_TX_AUTO_STOP

#define HPDI32_IOCTL_TX_AUTO_STOP _IOWR(GSC_IOCTL, 37, __s32)

◆ HPDI32_IOCTL_TX_CLOCK_DIVIDER

#define HPDI32_IOCTL_TX_CLOCK_DIVIDER _IOWR(GSC_IOCTL, 38, __s32)

◆ HPDI32_IOCTL_TX_ENABLE

#define HPDI32_IOCTL_TX_ENABLE _IOWR(GSC_IOCTL, 39, __s32)

◆ HPDI32_IOCTL_TX_FIFO_AE

#define HPDI32_IOCTL_TX_FIFO_AE _IOWR(GSC_IOCTL, 46, __s32)

◆ HPDI32_IOCTL_TX_FIFO_AF

#define HPDI32_IOCTL_TX_FIFO_AF _IOWR(GSC_IOCTL, 47, __s32)

◆ HPDI32_IOCTL_TX_FIFO_OVERRUN

#define HPDI32_IOCTL_TX_FIFO_OVERRUN _IOWR(GSC_IOCTL, 48, __s32)

◆ HPDI32_IOCTL_TX_FIFO_RESET

#define HPDI32_IOCTL_TX_FIFO_RESET _IO (GSC_IOCTL, 49)

◆ HPDI32_IOCTL_TX_FIFO_STATUS

#define HPDI32_IOCTL_TX_FIFO_STATUS _IOR (GSC_IOCTL, 50, __s32)

◆ HPDI32_IOCTL_TX_FLOW_CONTROL

#define HPDI32_IOCTL_TX_FLOW_CONTROL _IOWR(GSC_IOCTL, 40, __s32)

◆ HPDI32_IOCTL_TX_IO_ABORT

#define HPDI32_IOCTL_TX_IO_ABORT _IOR (GSC_IOCTL, 51, __s32)

◆ HPDI32_IOCTL_TX_IO_DATA_SIZE

#define HPDI32_IOCTL_TX_IO_DATA_SIZE _IOWR(GSC_IOCTL, 52, __s32)

◆ HPDI32_IOCTL_TX_IO_MODE

#define HPDI32_IOCTL_TX_IO_MODE _IOWR(GSC_IOCTL, 53, __s32)

◆ HPDI32_IOCTL_TX_IO_OVERRUN

#define HPDI32_IOCTL_TX_IO_OVERRUN _IOWR(GSC_IOCTL, 55, __s32)

◆ HPDI32_IOCTL_TX_IO_PIO_THRESHOLD

#define HPDI32_IOCTL_TX_IO_PIO_THRESHOLD _IOWR(GSC_IOCTL, 54, __s32)

◆ HPDI32_IOCTL_TX_IO_TIMEOUT

#define HPDI32_IOCTL_TX_IO_TIMEOUT _IOWR(GSC_IOCTL, 56, __s32)

◆ HPDI32_IOCTL_TX_LINE_VAL_OFF_CNT

#define HPDI32_IOCTL_TX_LINE_VAL_OFF_CNT _IOWR(GSC_IOCTL, 41, __s32)

◆ HPDI32_IOCTL_TX_LINE_VAL_ON_CNT

#define HPDI32_IOCTL_TX_LINE_VAL_ON_CNT _IOWR(GSC_IOCTL, 42, __s32)

◆ HPDI32_IOCTL_TX_REMOTE_THROTTLE

#define HPDI32_IOCTL_TX_REMOTE_THROTTLE _IOWR(GSC_IOCTL, 43, __s32)

◆ HPDI32_IOCTL_TX_STATUS_VAL_CNT

#define HPDI32_IOCTL_TX_STATUS_VAL_CNT _IOWR(GSC_IOCTL, 44, __s32)

◆ HPDI32_IOCTL_TX_STATUS_VAL_MIR

#define HPDI32_IOCTL_TX_STATUS_VAL_MIR _IOWR(GSC_IOCTL, 45, __s32)

◆ HPDI32_IOCTL_USER_JUMPERS

#define HPDI32_IOCTL_USER_JUMPERS _IOR (GSC_IOCTL, 61, __s32)

◆ HPDI32_IOCTL_WAIT_CANCEL

#define HPDI32_IOCTL_WAIT_CANCEL _IOWR(GSC_IOCTL, 63, gsc_wait_t)

◆ HPDI32_IOCTL_WAIT_EVENT

#define HPDI32_IOCTL_WAIT_EVENT _IOWR(GSC_IOCTL, 62, gsc_wait_t)

◆ HPDI32_IOCTL_WAIT_STATUS

#define HPDI32_IOCTL_WAIT_STATUS _IOWR(GSC_IOCTL, 64, gsc_wait_t)

◆ HPDI32_IRQ_ALL

#define HPDI32_IRQ_ALL 0x0000FFFF

◆ HPDI32_IRQ_CC0_FV_E_GPIO6

#define HPDI32_IRQ_CC0_FV_E_GPIO6 0x00000002

◆ HPDI32_IRQ_CC0_FV_S_GPIO6

#define HPDI32_IRQ_CC0_FV_S_GPIO6 0x00000001

◆ HPDI32_IRQ_CC1_LV_GPIO0

#define HPDI32_IRQ_CC1_LV_GPIO0 0x00000004

◆ HPDI32_IRQ_CC2_SV_GPIO1

#define HPDI32_IRQ_CC2_SV_GPIO1 0x00000008

◆ HPDI32_IRQ_CC3_RR_GPIO2

#define HPDI32_IRQ_CC3_RR_GPIO2 0x00000010

◆ HPDI32_IRQ_CC4_TR_GPIO3

#define HPDI32_IRQ_CC4_TR_GPIO3 0x00000020

◆ HPDI32_IRQ_CC5_TE_GPIO4

#define HPDI32_IRQ_CC5_TE_GPIO4 0x00000040

◆ HPDI32_IRQ_CC6_RE_GPIO5

#define HPDI32_IRQ_CC6_RE_GPIO5 0x00000080

◆ HPDI32_IRQ_RX_FIFO_AE

#define HPDI32_IRQ_RX_FIFO_AE 0x00002000

◆ HPDI32_IRQ_RX_FIFO_AF

#define HPDI32_IRQ_RX_FIFO_AF 0x00004000

◆ HPDI32_IRQ_RX_FIFO_EMPTY

#define HPDI32_IRQ_RX_FIFO_EMPTY 0x00001000

◆ HPDI32_IRQ_RX_FIFO_FULL

#define HPDI32_IRQ_RX_FIFO_FULL 0x00008000

◆ HPDI32_IRQ_TX_FIFO_AE

#define HPDI32_IRQ_TX_FIFO_AE 0x00000200

◆ HPDI32_IRQ_TX_FIFO_AF

#define HPDI32_IRQ_TX_FIFO_AF 0x00000400

◆ HPDI32_IRQ_TX_FIFO_EMPTY

#define HPDI32_IRQ_TX_FIFO_EMPTY 0x00000100

◆ HPDI32_IRQ_TX_FIFO_FULL

#define HPDI32_IRQ_TX_FIFO_FULL 0x00000800

◆ HPDI32_QUERY_FF_CPCI

#define HPDI32_QUERY_FF_CPCI 3

◆ HPDI32_QUERY_FF_PC104P

#define HPDI32_QUERY_FF_PC104P 4

◆ HPDI32_QUERY_FF_PCI

#define HPDI32_QUERY_FF_PCI 1

◆ HPDI32_QUERY_FF_PMC

#define HPDI32_QUERY_FF_PMC 2

◆ HPDI32_QUERY_FF_UNKNOWN

#define HPDI32_QUERY_FF_UNKNOWN 0

◆ HPDI32_QUERY_XCVR_PECL

#define HPDI32_QUERY_XCVR_PECL 1

◆ HPDI32_QUERY_XCVR_RS485

#define HPDI32_QUERY_XCVR_RS485 2

◆ HPDI32_QUERY_XCVR_UNKNOWN

#define HPDI32_QUERY_XCVR_UNKNOWN 0

◆ HPDI32_RX_ENABLE_NO

#define HPDI32_RX_ENABLE_NO 0

◆ HPDI32_RX_ENABLE_YES

#define HPDI32_RX_ENABLE_YES 1

◆ HPDI32_TRISTATE_TE_RE_NO

#define HPDI32_TRISTATE_TE_RE_NO 0

◆ HPDI32_TRISTATE_TE_RE_YES

#define HPDI32_TRISTATE_TE_RE_YES 1

◆ HPDI32_TX_ENABLE_NO

#define HPDI32_TX_ENABLE_NO 0

◆ HPDI32_TX_ENABLE_YES

#define HPDI32_TX_ENABLE_YES 1

◆ HPDI32_TX_FLOW_CONTROL_START

#define HPDI32_TX_FLOW_CONTROL_START 1

◆ HPDI32_TX_FLOW_CONTROL_STOP

#define HPDI32_TX_FLOW_CONTROL_STOP 0

◆ HPDI32_TX_REMOTE_THROTTLE_NO

#define HPDI32_TX_REMOTE_THROTTLE_NO 0

◆ HPDI32_TX_REMOTE_THROTTLE_YES

#define HPDI32_TX_REMOTE_THROTTLE_YES 1

◆ HPDI32_TX_STATUS_VAL_MIR_NO

#define HPDI32_TX_STATUS_VAL_MIR_NO 0

◆ HPDI32_TX_STATUS_VAL_MIR_YES

#define HPDI32_TX_STATUS_VAL_MIR_YES 1

◆ HPDI32_WAIT_ALT_ALL

#define HPDI32_WAIT_ALT_ALL 0x0000

◆ HPDI32_WAIT_GSC_ALL

#define HPDI32_WAIT_GSC_ALL HPDI32_IRQ_ALL

◆ HPDI32_WAIT_GSC_CC0_FV_E_GPIO6

#define HPDI32_WAIT_GSC_CC0_FV_E_GPIO6 HPDI32_IRQ_CC0_FV_E_GPIO6

◆ HPDI32_WAIT_GSC_CC0_FV_S_GPIO6

#define HPDI32_WAIT_GSC_CC0_FV_S_GPIO6 HPDI32_IRQ_CC0_FV_S_GPIO6

◆ HPDI32_WAIT_GSC_CC1_LV_GPIO0

#define HPDI32_WAIT_GSC_CC1_LV_GPIO0 HPDI32_IRQ_CC1_LV_GPIO0

◆ HPDI32_WAIT_GSC_CC2_SV_GPIO1

#define HPDI32_WAIT_GSC_CC2_SV_GPIO1 HPDI32_IRQ_CC2_SV_GPIO1

◆ HPDI32_WAIT_GSC_CC3_RR_GPIO2

#define HPDI32_WAIT_GSC_CC3_RR_GPIO2 HPDI32_IRQ_CC3_RR_GPIO2

◆ HPDI32_WAIT_GSC_CC4_TR_GPIO3

#define HPDI32_WAIT_GSC_CC4_TR_GPIO3 HPDI32_IRQ_CC4_TR_GPIO3

◆ HPDI32_WAIT_GSC_CC5_TE_GPIO4

#define HPDI32_WAIT_GSC_CC5_TE_GPIO4 HPDI32_IRQ_CC5_TE_GPIO4

◆ HPDI32_WAIT_GSC_CC6_RE_GPIO5

#define HPDI32_WAIT_GSC_CC6_RE_GPIO5 HPDI32_IRQ_CC6_RE_GPIO5

◆ HPDI32_WAIT_GSC_RX_FIFO_AE

#define HPDI32_WAIT_GSC_RX_FIFO_AE HPDI32_IRQ_RX_FIFO_AE

◆ HPDI32_WAIT_GSC_RX_FIFO_AF

#define HPDI32_WAIT_GSC_RX_FIFO_AF HPDI32_IRQ_RX_FIFO_AF

◆ HPDI32_WAIT_GSC_RX_FIFO_EMPTY

#define HPDI32_WAIT_GSC_RX_FIFO_EMPTY HPDI32_IRQ_RX_FIFO_EMPTY

◆ HPDI32_WAIT_GSC_RX_FIFO_FULL

#define HPDI32_WAIT_GSC_RX_FIFO_FULL HPDI32_IRQ_RX_FIFO_FULL

◆ HPDI32_WAIT_GSC_TX_FIFO_AE

#define HPDI32_WAIT_GSC_TX_FIFO_AE HPDI32_IRQ_TX_FIFO_AE

◆ HPDI32_WAIT_GSC_TX_FIFO_AF

#define HPDI32_WAIT_GSC_TX_FIFO_AF HPDI32_IRQ_TX_FIFO_AF

◆ HPDI32_WAIT_GSC_TX_FIFO_EMPTY

#define HPDI32_WAIT_GSC_TX_FIFO_EMPTY HPDI32_IRQ_TX_FIFO_EMPTY

◆ HPDI32_WAIT_GSC_TX_FIFO_FULL

#define HPDI32_WAIT_GSC_TX_FIFO_FULL HPDI32_IRQ_TX_FIFO_FULL

Enumeration Type Documentation

◆ aiss8ao4_query_t

enum aiss8ao4_query_t

Enumerator
HPDI32_QUERY_BSR_D18_XCVR
HPDI32_QUERY_BUS_WIDTH
HPDI32_QUERY_CLOCK_MAX
HPDI32_QUERY_COUNT
HPDI32_QUERY_DEVICE_TYPE
HPDI32_QUERY_DMDMA_1
HPDI32_QUERY_FEATURE_SET_REG
HPDI32_QUERY_FIFO_SIZE_REGS
HPDI32_QUERY_FIFO_SIZE_RX
HPDI32_QUERY_FIFO_SIZE_TX
HPDI32_QUERY_FIFO_WORDS_REGS
HPDI32_QUERY_FORM_FACTOR
HPDI32_QUERY_GPIO_0_5
HPDI32_QUERY_GPIO_6
HPDI32_QUERY_IRQ_CONFIG_REGS
HPDI32_QUERY_OVER_UNDER_RUN
HPDI32_QUERY_SINGLE_CYC_DIS
HPDI32_QUERY_TX_AUTO_STOP
HPDI32_QUERY_TX_CLOCK_DIV_MAX
HPDI32_QUERY_TX_CLOCK_DIV_MIN
HPDI32_QUERY_USER_JUMPERS
HPDI32_QUERY_XCVR_TYPE
HPDI32_IOCTL_QUERY_LAST

Enumerations
enum	aiss8ao4_query_t { HPDI32_QUERY_BSR_D18_XCVR, HPDI32_QUERY_BUS_WIDTH, HPDI32_QUERY_CLOCK_MAX, HPDI32_QUERY_COUNT, HPDI32_QUERY_DEVICE_TYPE, HPDI32_QUERY_DMDMA_1, HPDI32_QUERY_FEATURE_SET_REG, HPDI32_QUERY_FIFO_SIZE_REGS, HPDI32_QUERY_FIFO_SIZE_RX, HPDI32_QUERY_FIFO_SIZE_TX, HPDI32_QUERY_FIFO_WORDS_REGS, HPDI32_QUERY_FORM_FACTOR, HPDI32_QUERY_GPIO_0_5, HPDI32_QUERY_GPIO_6, HPDI32_QUERY_IRQ_CONFIG_REGS, HPDI32_QUERY_OVER_UNDER_RUN, HPDI32_QUERY_SINGLE_CYC_DIS, HPDI32_QUERY_TX_AUTO_STOP, HPDI32_QUERY_TX_CLOCK_DIV_MAX, HPDI32_QUERY_TX_CLOCK_DIV_MIN, HPDI32_QUERY_USER_JUMPERS, HPDI32_QUERY_XCVR_TYPE, HPDI32_IOCTL_QUERY_LAST }

Macros

Enumerations