#include <asm/types.h>#include <linux/ioctl.h>#include "gsc_common.h"
Include dependency graph for gsc_driver.h:
This graph shows which files directly or indirectly include this file:
Classes | |
| struct | gsc_drv_bar_t |
| struct | gsc_drv_dma_t |
| struct | gsc_drv_reg_t |
| struct | gsc_drv_irq_t |
| struct | gsc_drv_mem_t |
| struct | gsc_drv_version_t |
Macros | |
| #define | GSC_DATA_TYPES_NOT_NEEDED |
| #define | GSC_DRV_INTERFACE_VERSION 2 |
| #define | GSC_IOCTL_VERSION_GET _IOR( 'g', 0, gsc_drv_version_t) |
| #define | GSC_IOCTL_BAR_INFO_GET _IOWR('g', 1, gsc_drv_bar_t) |
| #define | GSC_IOCTL_REG_MOD _IOWR('g', 2, gsc_drv_reg_t) |
| #define | GSC_IOCTL_REG_READ _IOWR('g', 3, gsc_drv_reg_t) |
| #define | GSC_IOCTL_REG_WRITE _IOWR('g', 4, gsc_drv_reg_t) |
| #define | GSC_IOCTL_MEM_ALLOC _IOWR('g', 5, gsc_drv_mem_t) |
| #define | GSC_IOCTL_MEM_FREE _IOWR('g', 6, gsc_drv_mem_t) |
| #define | GSC_IOCTL_MEM_INFO _IOWR('g', 7, gsc_drv_mem_t) |
| #define | GSC_IOCTL_IRQ_DISABLE _IOWR('g', 8, gsc_drv_irq_t) |
| #define | GSC_IOCTL_IRQ_ENABLE _IOWR('g', 9, gsc_drv_irq_t) |
| #define | GSC_IOCTL_IRQ_NOTIFY _IOWR('g',10, gsc_drv_irq_t) |
| #define | GSC_IOCTL_IRQ_STATUS _IOR( 'g',11, gsc_drv_irq_t) |
| #define | GSC_IOCTL_IRQ_WAIT _IOWR('g',12, gsc_drv_irq_t) |
| #define | GSC_IOCTL_IRQ_WAIT_CANCEL _IOWR('g',13, gsc_drv_irq_t) |
| #define | GSC_IOCTL_DMA_ABORT _IOWR('g',14, gsc_drv_dma_t) |
| #define | GSC_IOCTL_DMA_CLOSE _IOWR('g',15, gsc_drv_dma_t) |
| #define | GSC_IOCTL_DMA_OPEN _IOWR('g',16, gsc_drv_dma_t) |
| #define | GSC_IOCTL_DMA_STATUS _IOWR('g',17, gsc_drv_dma_t) |
| #define | GSC_IOCTL_DMA_XFER _IOWR('g',18, gsc_drv_dma_t) |
| #define | GSC_MEM_ALLOC_MAX 32 |
| #define | GSC_IRQ_PCI 0x00000001 |
| #define | GSC_IRQ_DMA0 0x00000002 |
| #define | GSC_IRQ_DMA1 0x00000004 |
| #define | GSC_IRQ_LOCAL 0x00000008 |
| #define | GSC_IRQ_MASK 0x0000000F |
| #define | GSC_DMA_OPEN_PRI_MASK 0x00000003 |
| #define | GSC_DMA_OPEN_PRI_CH_0 0x00000001 /* Channel 0 */ |
| #define | GSC_DMA_OPEN_PRI_CH_1 0x00000002 /* Channel 1 */ |
| #define | GSC_DMA_OPEN_PRI_SHARE 0x00000003 /* Shared priority */ |
| #define | GSC_DMA_OPEN_SIZE_MASK 0x0000000C |
| #define | GSC_DMA_OPEN_SIZE_8_BITS 0x00000004 /* 8-bits */ |
| #define | GSC_DMA_OPEN_SIZE_16_BITS 0x00000008 /* 16-bits */ |
| #define | GSC_DMA_OPEN_SIZE_32_BITS 0x0000000C /* 32-bits */ |
| #define | GSC_DMA_OPEN_MEM_MASK 0x00000030 |
| #define | GSC_DMA_OPEN_MEM_BLOCK 0x00000010 /* single fixed block */ |
| #define | GSC_DMA_OPEN_MEM_SGL 0x00000020 /* scatter gather list */ |
| #define | GSC_DMA_OPEN_XFER_MASK 0x000000C0 |
| #define | GSC_DMA_OPEN_XFER_DEMAND 0x00000040 /* demand mode */ |
| #define | GSC_DMA_OPEN_XFER_FORCE 0x00000080 /* forced transfer */ |
| #define | GSC_DMA_OPEN_LADRS_MASK 0x00000300 |
| #define | GSC_DMA_OPEN_LADRS_FIXED 0x00000100 /* FIFO like */ |
| #define | GSC_DMA_OPEN_LADRS_INC 0x00000200 /* memory like */ |
| #define | GSC_DMA_OPEN_BTERM_INPUT 0x00010000 /* yes or no */ |
| #define | GSC_DMA_OPEN_EOT_PIN 0x00020000 /* yes or no */ |
| #define | GSC_DMA_OPEN_LOCAL_BURST 0x00040000 /* yes or no */ |
| #define | GSC_DMA_OPEN_READY_INPUT 0x00080000 /* yes or no */ |
| #define | GSC_DMA_OPEN_STOP_XFER_MODE 0x00100000 /* yes or no */ |
| #define | GSC_DMA_OPEN_WR_INVAL_MODE 0x00200000 /* yes or no */ |
| #define | GSC_DMA_XFER_DIR_TO_DEVICE 0x04000000 /* A DIR is required. */ |
| #define | GSC_DMA_XFER_DIR_TO_HOST 0x08000000 /* A DIR is required. */ |
| #define | GSC_DMA_STATUS_BUSY 0x40000000 /* STATUS */ |
| #define | GSC_DMA_STATUS_IDLE 0x80000000 /* STATUS */ |
Macro Definition Documentation
◆ GSC_DATA_TYPES_NOT_NEEDED
| #define GSC_DATA_TYPES_NOT_NEEDED |
◆ GSC_DMA_OPEN_BTERM_INPUT
| #define GSC_DMA_OPEN_BTERM_INPUT 0x00010000 /* yes or no */ |
◆ GSC_DMA_OPEN_EOT_PIN
| #define GSC_DMA_OPEN_EOT_PIN 0x00020000 /* yes or no */ |
◆ GSC_DMA_OPEN_LADRS_FIXED
| #define GSC_DMA_OPEN_LADRS_FIXED 0x00000100 /* FIFO like */ |
◆ GSC_DMA_OPEN_LADRS_INC
| #define GSC_DMA_OPEN_LADRS_INC 0x00000200 /* memory like */ |
◆ GSC_DMA_OPEN_LADRS_MASK
| #define GSC_DMA_OPEN_LADRS_MASK 0x00000300 |
◆ GSC_DMA_OPEN_LOCAL_BURST
| #define GSC_DMA_OPEN_LOCAL_BURST 0x00040000 /* yes or no */ |
◆ GSC_DMA_OPEN_MEM_BLOCK
| #define GSC_DMA_OPEN_MEM_BLOCK 0x00000010 /* single fixed block */ |
◆ GSC_DMA_OPEN_MEM_MASK
| #define GSC_DMA_OPEN_MEM_MASK 0x00000030 |
◆ GSC_DMA_OPEN_MEM_SGL
| #define GSC_DMA_OPEN_MEM_SGL 0x00000020 /* scatter gather list */ |
◆ GSC_DMA_OPEN_PRI_CH_0
| #define GSC_DMA_OPEN_PRI_CH_0 0x00000001 /* Channel 0 */ |
◆ GSC_DMA_OPEN_PRI_CH_1
| #define GSC_DMA_OPEN_PRI_CH_1 0x00000002 /* Channel 1 */ |
◆ GSC_DMA_OPEN_PRI_MASK
| #define GSC_DMA_OPEN_PRI_MASK 0x00000003 |
◆ GSC_DMA_OPEN_PRI_SHARE
| #define GSC_DMA_OPEN_PRI_SHARE 0x00000003 /* Shared priority */ |
◆ GSC_DMA_OPEN_READY_INPUT
| #define GSC_DMA_OPEN_READY_INPUT 0x00080000 /* yes or no */ |
◆ GSC_DMA_OPEN_SIZE_16_BITS
| #define GSC_DMA_OPEN_SIZE_16_BITS 0x00000008 /* 16-bits */ |
◆ GSC_DMA_OPEN_SIZE_32_BITS
| #define GSC_DMA_OPEN_SIZE_32_BITS 0x0000000C /* 32-bits */ |
◆ GSC_DMA_OPEN_SIZE_8_BITS
| #define GSC_DMA_OPEN_SIZE_8_BITS 0x00000004 /* 8-bits */ |
◆ GSC_DMA_OPEN_SIZE_MASK
| #define GSC_DMA_OPEN_SIZE_MASK 0x0000000C |
◆ GSC_DMA_OPEN_STOP_XFER_MODE
| #define GSC_DMA_OPEN_STOP_XFER_MODE 0x00100000 /* yes or no */ |
◆ GSC_DMA_OPEN_WR_INVAL_MODE
| #define GSC_DMA_OPEN_WR_INVAL_MODE 0x00200000 /* yes or no */ |
◆ GSC_DMA_OPEN_XFER_DEMAND
| #define GSC_DMA_OPEN_XFER_DEMAND 0x00000040 /* demand mode */ |
◆ GSC_DMA_OPEN_XFER_FORCE
| #define GSC_DMA_OPEN_XFER_FORCE 0x00000080 /* forced transfer */ |
◆ GSC_DMA_OPEN_XFER_MASK
| #define GSC_DMA_OPEN_XFER_MASK 0x000000C0 |
◆ GSC_DMA_STATUS_BUSY
| #define GSC_DMA_STATUS_BUSY 0x40000000 /* STATUS */ |
◆ GSC_DMA_STATUS_IDLE
| #define GSC_DMA_STATUS_IDLE 0x80000000 /* STATUS */ |
◆ GSC_DMA_XFER_DIR_TO_DEVICE
| #define GSC_DMA_XFER_DIR_TO_DEVICE 0x04000000 /* A DIR is required. */ |
◆ GSC_DMA_XFER_DIR_TO_HOST
| #define GSC_DMA_XFER_DIR_TO_HOST 0x08000000 /* A DIR is required. */ |
◆ GSC_DRV_INTERFACE_VERSION
| #define GSC_DRV_INTERFACE_VERSION 2 |
◆ GSC_IOCTL_BAR_INFO_GET
| #define GSC_IOCTL_BAR_INFO_GET _IOWR('g', 1, gsc_drv_bar_t) |
◆ GSC_IOCTL_DMA_ABORT
| #define GSC_IOCTL_DMA_ABORT _IOWR('g',14, gsc_drv_dma_t) |
◆ GSC_IOCTL_DMA_CLOSE
| #define GSC_IOCTL_DMA_CLOSE _IOWR('g',15, gsc_drv_dma_t) |
◆ GSC_IOCTL_DMA_OPEN
| #define GSC_IOCTL_DMA_OPEN _IOWR('g',16, gsc_drv_dma_t) |
◆ GSC_IOCTL_DMA_STATUS
| #define GSC_IOCTL_DMA_STATUS _IOWR('g',17, gsc_drv_dma_t) |
◆ GSC_IOCTL_DMA_XFER
| #define GSC_IOCTL_DMA_XFER _IOWR('g',18, gsc_drv_dma_t) |
◆ GSC_IOCTL_IRQ_DISABLE
| #define GSC_IOCTL_IRQ_DISABLE _IOWR('g', 8, gsc_drv_irq_t) |
◆ GSC_IOCTL_IRQ_ENABLE
| #define GSC_IOCTL_IRQ_ENABLE _IOWR('g', 9, gsc_drv_irq_t) |
◆ GSC_IOCTL_IRQ_NOTIFY
| #define GSC_IOCTL_IRQ_NOTIFY _IOWR('g',10, gsc_drv_irq_t) |
◆ GSC_IOCTL_IRQ_STATUS
| #define GSC_IOCTL_IRQ_STATUS _IOR( 'g',11, gsc_drv_irq_t) |
◆ GSC_IOCTL_IRQ_WAIT
| #define GSC_IOCTL_IRQ_WAIT _IOWR('g',12, gsc_drv_irq_t) |
◆ GSC_IOCTL_IRQ_WAIT_CANCEL
| #define GSC_IOCTL_IRQ_WAIT_CANCEL _IOWR('g',13, gsc_drv_irq_t) |
◆ GSC_IOCTL_MEM_ALLOC
| #define GSC_IOCTL_MEM_ALLOC _IOWR('g', 5, gsc_drv_mem_t) |
◆ GSC_IOCTL_MEM_FREE
| #define GSC_IOCTL_MEM_FREE _IOWR('g', 6, gsc_drv_mem_t) |
◆ GSC_IOCTL_MEM_INFO
| #define GSC_IOCTL_MEM_INFO _IOWR('g', 7, gsc_drv_mem_t) |
◆ GSC_IOCTL_REG_MOD
| #define GSC_IOCTL_REG_MOD _IOWR('g', 2, gsc_drv_reg_t) |
◆ GSC_IOCTL_REG_READ
| #define GSC_IOCTL_REG_READ _IOWR('g', 3, gsc_drv_reg_t) |
◆ GSC_IOCTL_REG_WRITE
| #define GSC_IOCTL_REG_WRITE _IOWR('g', 4, gsc_drv_reg_t) |
◆ GSC_IOCTL_VERSION_GET
| #define GSC_IOCTL_VERSION_GET _IOR( 'g', 0, gsc_drv_version_t) |
◆ GSC_IRQ_DMA0
| #define GSC_IRQ_DMA0 0x00000002 |
◆ GSC_IRQ_DMA1
| #define GSC_IRQ_DMA1 0x00000004 |
◆ GSC_IRQ_LOCAL
| #define GSC_IRQ_LOCAL 0x00000008 |
◆ GSC_IRQ_MASK
| #define GSC_IRQ_MASK 0x0000000F |
◆ GSC_IRQ_PCI
| #define GSC_IRQ_PCI 0x00000001 |
◆ GSC_MEM_ALLOC_MAX
| #define GSC_MEM_ALLOC_MAX 32 |
